i2c-sh_mobile.c 20.3 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
/*
 * SuperH Mobile I2C Controller
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * Portions of the code based on out-of-tree driver i2c-sh7343.c
 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
30
#include <linux/of_i2c.h>
31
#include <linux/err.h>
32
#include <linux/pm_runtime.h>
33 34
#include <linux/clk.h>
#include <linux/io.h>
35
#include <linux/slab.h>
36
#include <linux/i2c/i2c-sh_mobile.h>
37

38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106
/* Transmit operation:                                                      */
/*                                                                          */
/* 0 byte transmit                                                          */
/* BUS:     S     A8     ACK   P                                            */
/* IRQ:       DTE   WAIT                                                    */
/* ICIC:                                                                    */
/* ICCR: 0x94 0x90                                                          */
/* ICDR:      A8                                                            */
/*                                                                          */
/* 1 byte transmit                                                          */
/* BUS:     S     A8     ACK   D8(1)   ACK   P                              */
/* IRQ:       DTE   WAIT         WAIT                                       */
/* ICIC:      -DTE                                                          */
/* ICCR: 0x94       0x90                                                    */
/* ICDR:      A8    D8(1)                                                   */
/*                                                                          */
/* 2 byte transmit                                                          */
/* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P                */
/* IRQ:       DTE   WAIT         WAIT          WAIT                         */
/* ICIC:      -DTE                                                          */
/* ICCR: 0x94                    0x90                                       */
/* ICDR:      A8    D8(1)        D8(2)                                      */
/*                                                                          */
/* 3 bytes or more, +---------+ gets repeated                               */
/*                                                                          */
/*                                                                          */
/* Receive operation:                                                       */
/*                                                                          */
/* 0 byte receive - not supported since slave may hold SDA low              */
/*                                                                          */
/* 1 byte receive       [TX] | [RX]                                         */
/* BUS:     S     A8     ACK | D8(1)   ACK   P                              */
/* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
/* ICIC:      -DTE           |   +DTE                                       */
/* ICCR: 0x94       0x81     |   0xc0                                       */
/* ICDR:      A8             |            D8(1)                             */
/*                                                                          */
/* 2 byte receive        [TX]| [RX]                                         */
/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P                */
/* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
/* ICIC:      -DTE           |                 +DTE                         */
/* ICCR: 0x94       0x81     |                 0xc0                         */
/* ICDR:      A8             |                 D8(1)    D8(2)               */
/*                                                                          */
/* 3 byte receive       [TX] | [RX]                                         */
/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
/* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
/* ICIC:      -DTE           |                              +DTE            */
/* ICCR: 0x94       0x81     |                              0xc0            */
/* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
/*                                                                          */
/* 4 bytes or more, this part is repeated    +---------+                    */
/*                                                                          */
/*                                                                          */
/* Interrupt order and BUSY flag                                            */
/*     ___                                                 _                */
/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
/* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
/*                                                                          */
/*        S   D7  D6  D5  D4  D3  D2  D1  D0              P                 */
/*                                           ___                            */
/* WAIT IRQ ________________________________/   \___________                */
/* TACK IRQ ____________________________________/   \_______                */
/* DTE  IRQ __________________________________________/   \_                */
/* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
/*         _______________________________________________                  */
/* BUSY __/                                               \_                */
/*                                                                          */

107 108
enum sh_mobile_i2c_op {
	OP_START = 0,
109 110
	OP_TX_FIRST,
	OP_TX,
111 112
	OP_TX_STOP,
	OP_TX_TO_RX,
113
	OP_RX,
114
	OP_RX_STOP,
115
	OP_RX_STOP_DATA,
116 117 118 119 120 121
};

struct sh_mobile_i2c_data {
	struct device *dev;
	void __iomem *reg;
	struct i2c_adapter adap;
122
	unsigned long bus_speed;
123
	struct clk *clk;
124
	u_int8_t icic;
125 126
	u_int8_t iccl;
	u_int8_t icch;
127
	u_int8_t flags;
128 129 130 131 132 133 134 135

	spinlock_t lock;
	wait_queue_head_t wait;
	struct i2c_msg *msg;
	int pos;
	int sr;
};

136 137
#define IIC_FLAG_HAS_ICIC67	(1 << 0)

138 139 140
#define NORMAL_SPEED		100000 /* FAST_SPEED 400000 */

/* Register offsets */
141 142 143 144 145 146
#define ICDR			0x00
#define ICCR			0x04
#define ICSR			0x08
#define ICIC			0x0c
#define ICCL			0x10
#define ICCH			0x14
147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163

/* Register bits */
#define ICCR_ICE		0x80
#define ICCR_RACK		0x40
#define ICCR_TRS		0x10
#define ICCR_BBSY		0x04
#define ICCR_SCP		0x01

#define ICSR_SCLM		0x80
#define ICSR_SDAM		0x40
#define SW_DONE			0x20
#define ICSR_BUSY		0x10
#define ICSR_AL			0x08
#define ICSR_TACK		0x04
#define ICSR_WAIT		0x02
#define ICSR_DTE		0x01

164 165
#define ICIC_ICCLB8		0x80
#define ICIC_ICCHB8		0x40
166 167 168 169 170
#define ICIC_ALE		0x08
#define ICIC_TACKE		0x04
#define ICIC_WAITE		0x02
#define ICIC_DTEE		0x01

171 172
static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
{
173 174 175
	if (offs == ICIC)
		data |= pd->icic;

176 177 178 179 180 181 182 183 184 185 186 187 188 189
	iowrite8(data, pd->reg + offs);
}

static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
{
	return ioread8(pd->reg + offs);
}

static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
			unsigned char set, unsigned char clr)
{
	iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
}

190 191
static void activate_ch(struct sh_mobile_i2c_data *pd)
{
192 193 194 195 196
	unsigned long i2c_clk;
	u_int32_t num;
	u_int32_t denom;
	u_int32_t tmp;

197 198
	/* Wake up device and enable clock */
	pm_runtime_get_sync(pd->dev);
199 200
	clk_enable(pd->clk);

201 202 203 204 205 206 207 208 209
	/* Get clock rate after clock is enabled */
	i2c_clk = clk_get_rate(pd->clk);

	/* Calculate the value for iccl. From the data sheet:
	 * iccl = (p clock / transfer rate) * (L / (L + H))
	 * where L and H are the SCL low/high ratio (5/4 in this case).
	 * We also round off the result.
	 */
	num = i2c_clk * 5;
210
	denom = pd->bus_speed * 9;
211 212 213 214 215 216
	tmp = num * 10 / denom;
	if (tmp % 10 >= 5)
		pd->iccl = (u_int8_t)((num/denom) + 1);
	else
		pd->iccl = (u_int8_t)(num/denom);

217 218 219 220 221 222 223 224
	/* one more bit of ICCL in ICIC */
	if (pd->flags & IIC_FLAG_HAS_ICIC67) {
		if ((num/denom) > 0xff)
			pd->icic |= ICIC_ICCLB8;
		else
			pd->icic &= ~ICIC_ICCLB8;
	}

225 226 227 228 229 230 231 232 233
	/* Calculate the value for icch. From the data sheet:
	   icch = (p clock / transfer rate) * (H / (L + H)) */
	num = i2c_clk * 4;
	tmp = num * 10 / denom;
	if (tmp % 10 >= 5)
		pd->icch = (u_int8_t)((num/denom) + 1);
	else
		pd->icch = (u_int8_t)(num/denom);

234 235 236 237 238 239 240 241
	/* one more bit of ICCH in ICIC */
	if (pd->flags & IIC_FLAG_HAS_ICIC67) {
		if ((num/denom) > 0xff)
			pd->icic |= ICIC_ICCHB8;
		else
			pd->icic &= ~ICIC_ICCHB8;
	}

242
	/* Enable channel and configure rx ack */
243
	iic_set_clr(pd, ICCR, ICCR_ICE, 0);
244 245

	/* Mask all interrupts */
246
	iic_wr(pd, ICIC, 0);
247 248

	/* Set the clock */
249 250
	iic_wr(pd, ICCL, pd->iccl);
	iic_wr(pd, ICCH, pd->icch);
251 252 253 254 255
}

static void deactivate_ch(struct sh_mobile_i2c_data *pd)
{
	/* Clear/disable interrupts */
256 257
	iic_wr(pd, ICSR, 0);
	iic_wr(pd, ICIC, 0);
258 259

	/* Disable channel */
260
	iic_set_clr(pd, ICCR, 0, ICCR_ICE);
261

262
	/* Disable clock and mark device as idle */
263
	clk_disable(pd->clk);
264
	pm_runtime_put_sync(pd->dev);
265 266 267 268 269 270 271 272 273 274 275 276 277
}

static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
			    enum sh_mobile_i2c_op op, unsigned char data)
{
	unsigned char ret = 0;
	unsigned long flags;

	dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);

	spin_lock_irqsave(&pd->lock, flags);

	switch (op) {
278
	case OP_START: /* issue start and trigger DTE interrupt */
279
		iic_wr(pd, ICCR, 0x94);
280
		break;
281
	case OP_TX_FIRST: /* disable DTE interrupt and write data */
282 283
		iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
		iic_wr(pd, ICDR, data);
284
		break;
285
	case OP_TX: /* write data */
286
		iic_wr(pd, ICDR, data);
287
		break;
288
	case OP_TX_STOP: /* write data and issue a stop afterwards */
289 290
		iic_wr(pd, ICDR, data);
		iic_wr(pd, ICCR, 0x90);
291 292
		break;
	case OP_TX_TO_RX: /* select read mode */
293
		iic_wr(pd, ICCR, 0x81);
294
		break;
295
	case OP_RX: /* just read data */
296
		ret = iic_rd(pd, ICDR);
297
		break;
298
	case OP_RX_STOP: /* enable DTE interrupt, issue stop */
299 300 301
		iic_wr(pd, ICIC,
		       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
		iic_wr(pd, ICCR, 0xc0);
302 303
		break;
	case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
304 305 306 307
		iic_wr(pd, ICIC,
		       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
		ret = iic_rd(pd, ICDR);
		iic_wr(pd, ICCR, 0xc0);
308 309 310 311 312 313 314 315 316
		break;
	}

	spin_unlock_irqrestore(&pd->lock, flags);

	dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
	return ret;
}

317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397
static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
{
	if (pd->pos == -1)
		return 1;

	return 0;
}

static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
{
	if (pd->pos == (pd->msg->len - 1))
		return 1;

	return 0;
}

static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
				   unsigned char *buf)
{
	switch (pd->pos) {
	case -1:
		*buf = (pd->msg->addr & 0x7f) << 1;
		*buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
		break;
	default:
		*buf = pd->msg->buf[pd->pos];
	}
}

static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
{
	unsigned char data;

	if (pd->pos == pd->msg->len)
		return 1;

	sh_mobile_i2c_get_data(pd, &data);

	if (sh_mobile_i2c_is_last_byte(pd))
		i2c_op(pd, OP_TX_STOP, data);
	else if (sh_mobile_i2c_is_first_byte(pd))
		i2c_op(pd, OP_TX_FIRST, data);
	else
		i2c_op(pd, OP_TX, data);

	pd->pos++;
	return 0;
}

static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
{
	unsigned char data;
	int real_pos;

	do {
		if (pd->pos <= -1) {
			sh_mobile_i2c_get_data(pd, &data);

			if (sh_mobile_i2c_is_first_byte(pd))
				i2c_op(pd, OP_TX_FIRST, data);
			else
				i2c_op(pd, OP_TX, data);
			break;
		}

		if (pd->pos == 0) {
			i2c_op(pd, OP_TX_TO_RX, 0);
			break;
		}

		real_pos = pd->pos - 2;

		if (pd->pos == pd->msg->len) {
			if (real_pos < 0) {
				i2c_op(pd, OP_RX_STOP, 0);
				break;
			}
			data = i2c_op(pd, OP_RX_STOP_DATA, 0);
		} else
			data = i2c_op(pd, OP_RX, 0);

398 399
		if (real_pos >= 0)
			pd->msg->buf[real_pos] = data;
400 401 402 403 404 405
	} while (0);

	pd->pos++;
	return pd->pos == (pd->msg->len + 2);
}

406 407 408 409
static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
{
	struct platform_device *dev = dev_id;
	struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
410 411
	unsigned char sr;
	int wakeup;
412

413
	sr = iic_rd(pd, ICSR);
414
	pd->sr |= sr; /* remember state */
415 416

	dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
417 418
	       (pd->msg->flags & I2C_M_RD) ? "read" : "write",
	       pd->pos, pd->msg->len);
419 420

	if (sr & (ICSR_AL | ICSR_TACK)) {
421
		/* don't interrupt transaction - continue to issue stop */
422
		iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
423 424 425 426 427
		wakeup = 0;
	} else if (pd->msg->flags & I2C_M_RD)
		wakeup = sh_mobile_i2c_isr_rx(pd);
	else
		wakeup = sh_mobile_i2c_isr_tx(pd);
428

429
	if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
430
		iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
431 432 433 434 435 436 437 438 439 440 441

	if (wakeup) {
		pd->sr |= SW_DONE;
		wake_up(&pd->wait);
	}

	return IRQ_HANDLED;
}

static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
{
442 443 444 445 446
	if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
		dev_err(pd->dev, "Unsupported zero length i2c read\n");
		return -EIO;
	}

447
	/* Initialize channel registers */
448
	iic_set_clr(pd, ICCR, 0, ICCR_ICE);
449 450

	/* Enable channel and configure rx ack */
451
	iic_set_clr(pd, ICCR, ICCR_ICE, 0);
452 453

	/* Set the clock */
454 455
	iic_wr(pd, ICCL, pd->iccl);
	iic_wr(pd, ICCH, pd->icch);
456 457 458 459 460

	pd->msg = usr_msg;
	pd->pos = -1;
	pd->sr = 0;

461
	/* Enable all interrupts to begin with */
462
	iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494
	return 0;
}

static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
			      struct i2c_msg *msgs,
			      int num)
{
	struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
	struct i2c_msg	*msg;
	int err = 0;
	u_int8_t val;
	int i, k, retry_count;

	activate_ch(pd);

	/* Process all messages */
	for (i = 0; i < num; i++) {
		msg = &msgs[i];

		err = start_ch(pd, msg);
		if (err)
			break;

		i2c_op(pd, OP_START, 0);

		/* The interrupt handler takes care of the rest... */
		k = wait_event_timeout(pd->wait,
				       pd->sr & (ICSR_TACK | SW_DONE),
				       5 * HZ);
		if (!k)
			dev_err(pd->dev, "Transfer request timed out\n");

495
		retry_count = 1000;
496
again:
497
		val = iic_rd(pd, ICSR);
498 499 500 501 502 503 504

		dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);

		/* the interrupt handler may wake us up before the
		 * transfer is finished, so poll the hardware
		 * until we're done.
		 */
505 506
		if (val & ICSR_BUSY) {
			udelay(10);
507 508 509 510 511 512 513
			if (retry_count--)
				goto again;

			err = -EIO;
			dev_err(pd->dev, "Polling timed out\n");
			break;
		}
514 515 516 517 518 519

		/* handle missing acknowledge and arbitration lost */
		if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
			err = -EIO;
			break;
		}
520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542
	}

	deactivate_ch(pd);

	if (!err)
		err = num;
	return err;
}

static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static struct i2c_algorithm sh_mobile_i2c_algorithm = {
	.functionality	= sh_mobile_i2c_func,
	.master_xfer	= sh_mobile_i2c_xfer,
};

static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
{
	struct resource *res;
	int ret = -ENXIO;
543
	int n, k = 0;
544 545 546

	while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
		for (n = res->start; hook && n <= res->end; n++) {
547
			if (request_irq(n, sh_mobile_i2c_isr, 0,
548 549 550 551
					dev_name(&dev->dev), dev)) {
				for (n--; n >= res->start; n--)
					free_irq(n, dev);

552
				goto rollback;
553
			}
554 555 556 557 558 559 560 561 562 563
		}
		k++;
	}

	if (hook)
		return k > 0 ? 0 : -ENOENT;

	ret = 0;

 rollback:
564 565 566 567 568 569
	k--;

	while (k >= 0) {
		res = platform_get_resource(dev, IORESOURCE_IRQ, k);
		for (n = res->start; n <= res->end; n++)
			free_irq(n, dev);
570

571
		k--;
572 573 574 575 576 577 578
	}

	return ret;
}

static int sh_mobile_i2c_probe(struct platform_device *dev)
{
579
	struct i2c_sh_mobile_platform_data *pdata = dev->dev.platform_data;
580 581 582 583 584 585 586 587 588 589 590 591
	struct sh_mobile_i2c_data *pd;
	struct i2c_adapter *adap;
	struct resource *res;
	int size;
	int ret;

	pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
	if (pd == NULL) {
		dev_err(&dev->dev, "cannot allocate private data\n");
		return -ENOMEM;
	}

592
	pd->clk = clk_get(&dev->dev, NULL);
593
	if (IS_ERR(pd->clk)) {
594
		dev_err(&dev->dev, "cannot get clock\n");
595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614
		ret = PTR_ERR(pd->clk);
		goto err;
	}

	ret = sh_mobile_i2c_hook_irqs(dev, 1);
	if (ret) {
		dev_err(&dev->dev, "cannot request IRQ\n");
		goto err_clk;
	}

	pd->dev = &dev->dev;
	platform_set_drvdata(dev, pd);

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		dev_err(&dev->dev, "cannot find IO resource\n");
		ret = -ENOENT;
		goto err_irq;
	}

J
Julia Lawall 已提交
615
	size = resource_size(res);
616 617 618 619 620 621 622 623

	pd->reg = ioremap(res->start, size);
	if (pd->reg == NULL) {
		dev_err(&dev->dev, "cannot map IO\n");
		ret = -ENXIO;
		goto err_irq;
	}

624 625 626 627 628
	/* Use platformd data bus speed or NORMAL_SPEED */
	pd->bus_speed = NORMAL_SPEED;
	if (pdata && pdata->bus_speed)
		pd->bus_speed = pdata->bus_speed;

629 630 631 632 633 634
	/* The IIC blocks on SH-Mobile ARM processors
	 * come with two new bits in ICIC.
	 */
	if (size > 0x17)
		pd->flags |= IIC_FLAG_HAS_ICIC67;

635 636 637 638 639 640 641 642 643 644 645 646 647
	/* Enable Runtime PM for this device.
	 *
	 * Also tell the Runtime PM core to ignore children
	 * for this device since it is valid for us to suspend
	 * this I2C master driver even though the slave devices
	 * on the I2C bus may not be suspended.
	 *
	 * The state of the I2C hardware bus is unaffected by
	 * the Runtime PM state.
	 */
	pm_suspend_ignore_children(&dev->dev, true);
	pm_runtime_enable(&dev->dev);

648 649 650 651 652 653 654 655 656
	/* setup the private data */
	adap = &pd->adap;
	i2c_set_adapdata(adap, pd);

	adap->owner = THIS_MODULE;
	adap->algo = &sh_mobile_i2c_algorithm;
	adap->dev.parent = &dev->dev;
	adap->retries = 5;
	adap->nr = dev->id;
657
	adap->dev.of_node = dev->dev.of_node;
658 659 660

	strlcpy(adap->name, dev->name, sizeof(adap->name));

661 662
	spin_lock_init(&pd->lock);
	init_waitqueue_head(&pd->wait);
663 664 665 666 667 668 669

	ret = i2c_add_numbered_adapter(adap);
	if (ret < 0) {
		dev_err(&dev->dev, "cannot add numbered adapter\n");
		goto err_all;
	}

670 671
	dev_info(&dev->dev, "I2C adapter %d with bus speed %lu Hz\n",
		 adap->nr, pd->bus_speed);
672 673

	of_i2c_register_devices(adap);
674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694
	return 0;

 err_all:
	iounmap(pd->reg);
 err_irq:
	sh_mobile_i2c_hook_irqs(dev, 0);
 err_clk:
	clk_put(pd->clk);
 err:
	kfree(pd);
	return ret;
}

static int sh_mobile_i2c_remove(struct platform_device *dev)
{
	struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);

	i2c_del_adapter(&pd->adap);
	iounmap(pd->reg);
	sh_mobile_i2c_hook_irqs(dev, 0);
	clk_put(pd->clk);
695
	pm_runtime_disable(&dev->dev);
696 697 698 699
	kfree(pd);
	return 0;
}

700 701 702 703 704 705 706 707 708 709 710 711
static int sh_mobile_i2c_runtime_nop(struct device *dev)
{
	/* Runtime PM callback shared between ->runtime_suspend()
	 * and ->runtime_resume(). Simply returns success.
	 *
	 * This driver re-initializes all registers after
	 * pm_runtime_get_sync() anyway so there is no need
	 * to save and restore registers here.
	 */
	return 0;
}

712
static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
713 714 715 716
	.runtime_suspend = sh_mobile_i2c_runtime_nop,
	.runtime_resume = sh_mobile_i2c_runtime_nop,
};

717 718 719 720 721 722
static const struct of_device_id sh_mobile_i2c_dt_ids[] __devinitconst = {
	{ .compatible = "renesas,rmobile-iic", },
	{},
};
MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);

723 724 725 726
static struct platform_driver sh_mobile_i2c_driver = {
	.driver		= {
		.name		= "i2c-sh_mobile",
		.owner		= THIS_MODULE,
727
		.pm		= &sh_mobile_i2c_dev_pm_ops,
728
		.of_match_table = sh_mobile_i2c_dt_ids,
729 730 731 732 733 734 735 736 737 738 739 740 741 742 743
	},
	.probe		= sh_mobile_i2c_probe,
	.remove		= sh_mobile_i2c_remove,
};

static int __init sh_mobile_i2c_adap_init(void)
{
	return platform_driver_register(&sh_mobile_i2c_driver);
}

static void __exit sh_mobile_i2c_adap_exit(void)
{
	platform_driver_unregister(&sh_mobile_i2c_driver);
}

744
subsys_initcall(sh_mobile_i2c_adap_init);
745 746 747 748 749
module_exit(sh_mobile_i2c_adap_exit);

MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
MODULE_AUTHOR("Magnus Damm");
MODULE_LICENSE("GPL v2");
750
MODULE_ALIAS("platform:i2c-sh_mobile");
新手
引导
客服 返回
顶部