bnx2x_link.c 358.5 KB
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/* Copyright 2008-2011 Broadcom Corporation
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 *
 * Unless you and Broadcom execute a separate written software license
 * agreement governing use of this software, this software is licensed to you
 * under the terms of the GNU General Public License version 2, available
 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
 *
 * Notwithstanding the above, under no circumstances may you combine this
 * software in any way with any other Broadcom software provided under a
 * license other than the GPL, without Broadcom's express prior written
 * consent.
 *
 * Written by Yaniv Rosner
 *
 */

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/mutex.h>

#include "bnx2x.h"
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#include "bnx2x_cmn.h"

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/********************************************************/
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#define ETH_HLEN			14
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/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
#define ETH_OVREHEAD			(ETH_HLEN + 8 + 8)
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#define ETH_MIN_PACKET_SIZE		60
#define ETH_MAX_PACKET_SIZE		1500
#define ETH_MAX_JUMBO_PACKET_SIZE	9600
#define MDIO_ACCESS_TIMEOUT		1000
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#define BMAC_CONTROL_RX_ENABLE		2
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#define WC_LANE_MAX			4
#define I2C_SWITCH_WIDTH		2
#define I2C_BSC0			0
#define I2C_BSC1			1
#define I2C_WA_RETRY_CNT		3
#define MCPR_IMC_COMMAND_READ_OP	1
#define MCPR_IMC_COMMAND_WRITE_OP	2
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/* LED Blink rate that will achieve ~15.9Hz */
#define LED_BLINK_RATE_VAL_E3		354
#define LED_BLINK_RATE_VAL_E1X_E2	480
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/***********************************************************/
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/*			Shortcut definitions		   */
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/***********************************************************/

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#define NIG_LATCH_BC_ENABLE_MI_INT 0

#define NIG_STATUS_EMAC0_MI_INT \
		NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
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#define NIG_STATUS_XGXS0_LINK10G \
		NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
#define NIG_STATUS_XGXS0_LINK_STATUS \
		NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
		NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
#define NIG_STATUS_SERDES0_LINK_STATUS \
		NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
#define NIG_MASK_MI_INT \
		NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
#define NIG_MASK_XGXS0_LINK10G \
		NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
#define NIG_MASK_XGXS0_LINK_STATUS \
		NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
#define NIG_MASK_SERDES0_LINK_STATUS \
		NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS

#define MDIO_AN_CL73_OR_37_COMPLETE \
		(MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
		 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)

#define XGXS_RESET_BITS \
	(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
	 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
	 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
	 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
	 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)

#define SERDES_RESET_BITS \
	(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
	 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
	 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
	 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)

#define AUTONEG_CL37		SHARED_HW_CFG_AN_ENABLE_CL37
#define AUTONEG_CL73		SHARED_HW_CFG_AN_ENABLE_CL73
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#define AUTONEG_BAM		SHARED_HW_CFG_AN_ENABLE_BAM
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#define AUTONEG_PARALLEL \
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				SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
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#define AUTONEG_SGMII_FIBER_AUTODET \
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				SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
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#define AUTONEG_REMOTE_PHY	SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
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#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
			MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
			MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
#define GP_STATUS_SPEED_MASK \
			MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
#define GP_STATUS_10M	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
#define GP_STATUS_100M	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
#define GP_STATUS_1G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
#define GP_STATUS_2_5G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
#define GP_STATUS_5G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
#define GP_STATUS_6G	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
#define GP_STATUS_10G_HIG \
			MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
#define GP_STATUS_10G_CX4 \
			MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
#define GP_STATUS_10G_KX4 \
			MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
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#define	GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
#define	GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
#define	GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
#define	GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
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#define LINK_10THD		LINK_STATUS_SPEED_AND_DUPLEX_10THD
#define LINK_10TFD		LINK_STATUS_SPEED_AND_DUPLEX_10TFD
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#define LINK_100TXHD		LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
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#define LINK_100T4		LINK_STATUS_SPEED_AND_DUPLEX_100T4
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#define LINK_100TXFD		LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
#define LINK_1000THD		LINK_STATUS_SPEED_AND_DUPLEX_1000THD
#define LINK_1000TFD		LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
#define LINK_1000XFD		LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
#define LINK_2500THD		LINK_STATUS_SPEED_AND_DUPLEX_2500THD
#define LINK_2500TFD		LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
#define LINK_2500XFD		LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
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#define LINK_10GTFD		LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
#define LINK_10GXFD		LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
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#define LINK_20GTFD		LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
#define LINK_20GXFD		LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
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/* */
#define SFP_EEPROM_CON_TYPE_ADDR		0x2
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	#define SFP_EEPROM_CON_TYPE_VAL_LC	0x7
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	#define SFP_EEPROM_CON_TYPE_VAL_COPPER	0x21

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#define SFP_EEPROM_COMP_CODE_ADDR		0x3
	#define SFP_EEPROM_COMP_CODE_SR_MASK	(1<<4)
	#define SFP_EEPROM_COMP_CODE_LR_MASK	(1<<5)
	#define SFP_EEPROM_COMP_CODE_LRM_MASK	(1<<6)

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#define SFP_EEPROM_FC_TX_TECH_ADDR		0x8
	#define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
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	#define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
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#define SFP_EEPROM_OPTIONS_ADDR			0x40
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	#define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
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#define SFP_EEPROM_OPTIONS_SIZE			2
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#define EDC_MODE_LINEAR				0x0022
#define EDC_MODE_LIMITING				0x0044
#define EDC_MODE_PASSIVE_DAC			0x0055
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/* BRB thresholds for E2*/
#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE		170
#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE		0

#define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE		250
#define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE		0

#define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE		10
#define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE		90

#define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE			50
#define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE		250

/* BRB thresholds for E3A0 */
#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE		290
#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE		0

#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE		410
#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE		0

#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE		10
#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE		170

#define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE		50
#define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE		410


/* BRB thresholds for E3B0 2 port mode*/
#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE		1025
#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE	0

#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE		1025
#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE	0

#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE		10
#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE	1025

#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE		50
#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE	1025

/* only for E3B0*/
#define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR			1025
#define PFC_E3B0_2P_BRB_FULL_LB_XON_THR			1025

/* Lossy +Lossless GUARANTIED == GUART */
#define PFC_E3B0_2P_MIX_PAUSE_LB_GUART			284
/* Lossless +Lossless*/
#define PFC_E3B0_2P_PAUSE_LB_GUART			236
/* Lossy +Lossy*/
#define PFC_E3B0_2P_NON_PAUSE_LB_GUART			342

/* Lossy +Lossless*/
#define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART		284
/* Lossless +Lossless*/
#define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART		236
/* Lossy +Lossy*/
#define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART		336
#define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST		80

#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART		0
#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST		0

/* BRB thresholds for E3B0 4 port mode */
#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE		304
#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE	0

#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE		384
#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE	0

#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE		10
#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE	304

#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE		50
#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE	384


/* only for E3B0*/
#define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR			304
#define PFC_E3B0_4P_BRB_FULL_LB_XON_THR			384
#define PFC_E3B0_4P_LB_GUART				120

#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART		120
#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST		80

#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART		80
#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST		120

#define DCBX_INVALID_COS					(0xFF)

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#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND		(0x5000)
#define ETS_BW_LIMIT_CREDIT_WEIGHT		(0x5000)
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#define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS		(1360)
#define ETS_E3B0_NIG_MIN_W_VAL_20GBPS			(2720)
#define ETS_E3B0_PBF_MIN_W_VAL				(10000)

#define MAX_PACKET_SIZE					(9700)
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#define WC_UC_TIMEOUT					100
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/**********************************************************/
/*                     INTERFACE                          */
/**********************************************************/
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#define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
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	bnx2x_cl45_write(_bp, _phy, \
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		(_phy)->def_md_devad, \
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		(_bank + (_addr & 0xf)), \
		_val)

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#define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
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	bnx2x_cl45_read(_bp, _phy, \
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		(_phy)->def_md_devad, \
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		(_bank + (_addr & 0xf)), \
		_val)

static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
{
	u32 val = REG_RD(bp, reg);

	val |= bits;
	REG_WR(bp, reg, val);
	return val;
}

static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
{
	u32 val = REG_RD(bp, reg);

	val &= ~bits;
	REG_WR(bp, reg, val);
	return val;
}

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/******************************************************************/
/*			EPIO/GPIO section			  */
/******************************************************************/
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static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
{
	u32 epio_mask, gp_oenable;
	*en = 0;
	/* Sanity check */
	if (epio_pin > 31) {
		DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
		return;
	}

	epio_mask = 1 << epio_pin;
	/* Set this EPIO to output */
	gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
	REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);

	*en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
}
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static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
{
	u32 epio_mask, gp_output, gp_oenable;

	/* Sanity check */
	if (epio_pin > 31) {
		DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
		return;
	}
	DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
	epio_mask = 1 << epio_pin;
	/* Set this EPIO to output */
	gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
	if (en)
		gp_output |= epio_mask;
	else
		gp_output &= ~epio_mask;

	REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);

	/* Set the value for this EPIO */
	gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
	REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
}

static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
{
	if (pin_cfg == PIN_CFG_NA)
		return;
	if (pin_cfg >= PIN_CFG_EPIO0) {
		bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
	} else {
		u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
		u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
		bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
	}
}

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static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
{
	if (pin_cfg == PIN_CFG_NA)
		return -EINVAL;
	if (pin_cfg >= PIN_CFG_EPIO0) {
		bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
	} else {
		u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
		u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
		*val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
	}
	return 0;

}
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/******************************************************************/
/*				ETS section			  */
/******************************************************************/
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static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
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{
	/* ETS disabled configuration*/
	struct bnx2x *bp = params->bp;

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	DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
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	/*
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	 * mapping between entry  priority to client number (0,1,2 -debug and
	 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
	 * 3bits client num.
	 *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
	 * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
	 */

	REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
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	/*
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	 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
	 * as strict.  Bits 0,1,2 - debug and management entries, 3 -
	 * COS0 entry, 4 - COS1 entry.
	 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
	 * bit4   bit3	  bit2   bit1	  bit0
	 * MCP and debug are strict
	 */

	REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
	/* defines which entries (clients) are subjected to WFQ arbitration */
	REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
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	/*
	 * For strict priority entries defines the number of consecutive
	 * slots for the highest priority.
	 */
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	REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
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	/*
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	 * mapping between the CREDIT_WEIGHT registers and actual client
	 * numbers
	 */
	REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
	REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
	REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);

	REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
	REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
	REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
	/* ETS mode disable */
	REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
420
	/*
421 422 423 424 425 426 427 428 429 430 431
	 * If ETS mode is enabled (there is no strict priority) defines a WFQ
	 * weight for COS0/COS1.
	 */
	REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
	REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
	/* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
	REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
	REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
	/* Defines the number of consecutive slots for the strict priority */
	REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
}
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/******************************************************************************
* Description:
*	Getting min_w_val will be set according to line speed .
*.
******************************************************************************/
static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
{
	u32 min_w_val = 0;
	/* Calculate min_w_val.*/
	if (vars->link_up) {
		if (SPEED_20000 == vars->line_speed)
			min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
		else
			min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
	} else
		min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
	/**
	 *  If the link isn't up (static configuration for example ) The
	 *  link will be according to 20GBPS.
	*/
	return min_w_val;
}
/******************************************************************************
* Description:
*	Getting credit upper bound form min_w_val.
*.
******************************************************************************/
static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
{
	const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
						MAX_PACKET_SIZE);
	return credit_upper_bound;
}
/******************************************************************************
* Description:
*	Set credit upper bound for NIG.
*.
******************************************************************************/
static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
	const struct link_params *params,
	const u32 min_w_val)
{
	struct bnx2x *bp = params->bp;
	const u8 port = params->port;
	const u32 credit_upper_bound =
	    bnx2x_ets_get_credit_upper_bound(min_w_val);

	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
		NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
		   NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
		   NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
		   NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
		   NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
		   NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);

	if (0 == port) {
		REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
			credit_upper_bound);
		REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
			credit_upper_bound);
		REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
			credit_upper_bound);
	}
}
/******************************************************************************
* Description:
*	Will return the NIG ETS registers to init values.Except
*	credit_upper_bound.
*	That isn't used in this configuration (No WFQ is enabled) and will be
*	configured acording to spec
*.
******************************************************************************/
static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
					const struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	const u8 port = params->port;
	const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
	/**
	 * mapping between entry  priority to client number (0,1,2 -debug and
	 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
	 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
	 * reset value or init tool
	 */
	if (port) {
		REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
		REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
	} else {
		REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
		REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
	}
	/**
	* For strict priority entries defines the number of consecutive
	* slots for the highest priority.
	*/
	/* TODO_ETS - Should be done by reset value or init tool */
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
		   NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
	/**
	 * mapping between the CREDIT_WEIGHT registers and actual client
	 * numbers
	 */
	/* TODO_ETS - Should be done by reset value or init tool */
	if (port) {
		/*Port 1 has 6 COS*/
		REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
		REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
	} else {
		/*Port 0 has 9 COS*/
		REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
		       0x43210876);
		REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
	}

	/**
	 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
	 * as strict.  Bits 0,1,2 - debug and management entries, 3 -
	 * COS0 entry, 4 - COS1 entry.
	 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
	 * bit4   bit3	  bit2   bit1	  bit0
	 * MCP and debug are strict
	 */
	if (port)
		REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
	else
		REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
	/* defines which entries (clients) are subjected to WFQ arbitration */
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
		   NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);

	/**
	* Please notice the register address are note continuous and a
	* for here is note appropriate.In 2 port mode port0 only COS0-5
	* can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
	* port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
	* are never used for WFQ
	*/
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
	if (0 == port) {
		REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
		REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
		REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
	}

	bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
}
/******************************************************************************
* Description:
*	Set credit upper bound for PBF.
*.
******************************************************************************/
static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
	const struct link_params *params,
	const u32 min_w_val)
{
	struct bnx2x *bp = params->bp;
	const u32 credit_upper_bound =
	    bnx2x_ets_get_credit_upper_bound(min_w_val);
	const u8 port = params->port;
	u32 base_upper_bound = 0;
	u8 max_cos = 0;
	u8 i = 0;
	/**
	* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
	* port mode port1 has COS0-2 that can be used for WFQ.
	*/
	if (0 == port) {
		base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
		max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
	} else {
		base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
		max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
	}

	for (i = 0; i < max_cos; i++)
		REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
}

/******************************************************************************
* Description:
*	Will return the PBF ETS registers to init values.Except
*	credit_upper_bound.
*	That isn't used in this configuration (No WFQ is enabled) and will be
*	configured acording to spec
*.
******************************************************************************/
static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
{
	struct bnx2x *bp = params->bp;
	const u8 port = params->port;
	const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
	u8 i = 0;
	u32 base_weight = 0;
	u8 max_cos = 0;

	/**
	 * mapping between entry  priority to client number 0 - COS0
	 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
	 * TODO_ETS - Should be done by reset value or init tool
	 */
	if (port)
		/*  0x688 (|011|0 10|00 1|000) */
		REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
	else
		/*  (10 1|100 |011|0 10|00 1|000) */
		REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);

	/* TODO_ETS - Should be done by reset value or init tool */
	if (port)
		/* 0x688 (|011|0 10|00 1|000)*/
		REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
	else
	/* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
	REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);

	REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
		   PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);


	REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
		   PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);

	REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
		   PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
	/**
	* In 2 port mode port0 has COS0-5 that can be used for WFQ.
	* In 4 port mode port1 has COS0-2 that can be used for WFQ.
	*/
	if (0 == port) {
		base_weight = PBF_REG_COS0_WEIGHT_P0;
		max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
	} else {
		base_weight = PBF_REG_COS0_WEIGHT_P1;
		max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
	}

	for (i = 0; i < max_cos; i++)
		REG_WR(bp, base_weight + (0x4 * i), 0);

	bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
}
/******************************************************************************
* Description:
*	E3B0 disable will return basicly the values to init values.
*.
******************************************************************************/
static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
				   const struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;

	if (!CHIP_IS_E3B0(bp)) {
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		DP(NETIF_MSG_LINK,
		   "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
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		return -EINVAL;
	}

	bnx2x_ets_e3b0_nig_disabled(params, vars);

	bnx2x_ets_e3b0_pbf_disabled(params);

	return 0;
}

/******************************************************************************
* Description:
*	Disable will return basicly the values to init values.
*.
******************************************************************************/
int bnx2x_ets_disabled(struct link_params *params,
		      struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	int bnx2x_status = 0;

	if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
		bnx2x_ets_e2e3a0_disabled(params);
	else if (CHIP_IS_E3B0(bp))
		bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
	else {
		DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
		return -EINVAL;
	}

	return bnx2x_status;
}

/******************************************************************************
* Description
*	Set the COS mappimg to SP and BW until this point all the COS are not
*	set as SP or BW.
******************************************************************************/
static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
				  const struct bnx2x_ets_params *ets_params,
				  const u8 cos_sp_bitmap,
				  const u8 cos_bw_bitmap)
{
	struct bnx2x *bp = params->bp;
	const u8 port = params->port;
	const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
	const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
	const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
	const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;

	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
	       NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);

	REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
	       PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
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	REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
	       NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
	       nig_cli_subject2wfq_bitmap);

	REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
	       PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
	       pbf_cli_subject2wfq_bitmap);

	return 0;
}

/******************************************************************************
* Description:
*	This function is needed because NIG ARB_CREDIT_WEIGHT_X are
*	not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
******************************************************************************/
static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
				     const u8 cos_entry,
				     const u32 min_w_val_nig,
				     const u32 min_w_val_pbf,
				     const u16 total_bw,
				     const u8 bw,
				     const u8 port)
{
	u32 nig_reg_adress_crd_weight = 0;
	u32 pbf_reg_adress_crd_weight = 0;
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	/* Calculate and set BW for this COS - use 1 instead of 0 for BW */
	const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
	const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
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	switch (cos_entry) {
	case 0:
	    nig_reg_adress_crd_weight =
		 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
		     NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
	     pbf_reg_adress_crd_weight = (port) ?
		 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
	     break;
	case 1:
	     nig_reg_adress_crd_weight = (port) ?
		 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
	     pbf_reg_adress_crd_weight = (port) ?
		 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
	     break;
	case 2:
	     nig_reg_adress_crd_weight = (port) ?
		 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;

		 pbf_reg_adress_crd_weight = (port) ?
		     PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
	     break;
	case 3:
	    if (port)
			return -EINVAL;
	     nig_reg_adress_crd_weight =
		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
	     pbf_reg_adress_crd_weight =
		 PBF_REG_COS3_WEIGHT_P0;
	     break;
	case 4:
	    if (port)
		return -EINVAL;
	     nig_reg_adress_crd_weight =
		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
	     pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
	     break;
	case 5:
	    if (port)
		return -EINVAL;
	     nig_reg_adress_crd_weight =
		 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
	     pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
	     break;
	}

	REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);

	REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);

	return 0;
}
/******************************************************************************
* Description:
*	Calculate the total BW.A value of 0 isn't legal.
*.
******************************************************************************/
static int bnx2x_ets_e3b0_get_total_bw(
	const struct link_params *params,
	const struct bnx2x_ets_params *ets_params,
	u16 *total_bw)
{
	struct bnx2x *bp = params->bp;
	u8 cos_idx = 0;

	*total_bw = 0 ;
	/* Calculate total BW requested */
	for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
		if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
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			*total_bw +=
				ets_params->cos[cos_idx].params.bw_params.bw;
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		}
	}

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	/* Check total BW is valid */
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	if ((100 != *total_bw) || (0 == *total_bw)) {
		if (0 == *total_bw) {
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			DP(NETIF_MSG_LINK,
			   "bnx2x_ets_E3B0_config toatl BW shouldn't be 0\n");
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			return -EINVAL;
		}
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		DP(NETIF_MSG_LINK,
		   "bnx2x_ets_E3B0_config toatl BW should be 100\n");
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		/**
		*   We can handle a case whre the BW isn't 100 this can happen
		*   if the TC are joined.
		*/
	}
	return 0;
}

/******************************************************************************
* Description:
*	Invalidate all the sp_pri_to_cos.
*.
******************************************************************************/
static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
{
	u8 pri = 0;
	for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
		sp_pri_to_cos[pri] = DCBX_INVALID_COS;
}
/******************************************************************************
* Description:
*	Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
*	according to sp_pri_to_cos.
*.
******************************************************************************/
static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
					    u8 *sp_pri_to_cos, const u8 pri,
					    const u8 cos_entry)
{
	struct bnx2x *bp = params->bp;
	const u8 port = params->port;
	const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
		DCBX_E3B0_MAX_NUM_COS_PORT0;

	if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
		DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
908
				   "parameter There can't be two COS's with "
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				   "the same strict pri\n");
		return -EINVAL;
	}

	if (pri > max_num_of_cos) {
914
		DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
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			       "parameter Illegal strict priority\n");
	    return -EINVAL;
	}

	sp_pri_to_cos[pri] = cos_entry;
	return 0;

}

/******************************************************************************
* Description:
*	Returns the correct value according to COS and priority in
*	the sp_pri_cli register.
*.
******************************************************************************/
static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
					 const u8 pri_set,
					 const u8 pri_offset,
					 const u8 entry_size)
{
	u64 pri_cli_nig = 0;
	pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
						    (pri_set + pri_offset));

	return pri_cli_nig;
}
/******************************************************************************
* Description:
*	Returns the correct value according to COS and priority in the
*	sp_pri_cli register for NIG.
*.
******************************************************************************/
static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
{
	/* MCP Dbg0 and dbg1 are always with higher strict pri*/
	const u8 nig_cos_offset = 3;
	const u8 nig_pri_offset = 3;

	return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
		nig_pri_offset, 4);

}
/******************************************************************************
* Description:
*	Returns the correct value according to COS and priority in the
*	sp_pri_cli register for PBF.
*.
******************************************************************************/
static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
{
	const u8 pbf_cos_offset = 0;
	const u8 pbf_pri_offset = 0;

	return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
		pbf_pri_offset, 3);

}

/******************************************************************************
* Description:
*	Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
*	according to sp_pri_to_cos.(which COS has higher priority)
*.
******************************************************************************/
static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
					     u8 *sp_pri_to_cos)
{
	struct bnx2x *bp = params->bp;
	u8 i = 0;
	const u8 port = params->port;
	/* MCP Dbg0 and dbg1 are always with higher strict pri*/
	u64 pri_cli_nig = 0x210;
	u32 pri_cli_pbf = 0x0;
	u8 pri_set = 0;
	u8 pri_bitmask = 0;
	const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
		DCBX_E3B0_MAX_NUM_COS_PORT0;

	u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;

	/* Set all the strict priority first */
	for (i = 0; i < max_num_of_cos; i++) {
		if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
			if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
				DP(NETIF_MSG_LINK,
					   "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
					   "invalid cos entry\n");
				return -EINVAL;
			}

			pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
			    sp_pri_to_cos[i], pri_set);

			pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
			    sp_pri_to_cos[i], pri_set);
			pri_bitmask = 1 << sp_pri_to_cos[i];
			/* COS is used remove it from bitmap.*/
			if (0 == (pri_bitmask & cos_bit_to_set)) {
				DP(NETIF_MSG_LINK,
					"bnx2x_ets_e3b0_sp_set_pri_cli_reg "
					"invalid There can't be two COS's with"
					" the same strict pri\n");
				return -EINVAL;
			}
			cos_bit_to_set &= ~pri_bitmask;
			pri_set++;
		}
	}

	/* Set all the Non strict priority i= COS*/
	for (i = 0; i < max_num_of_cos; i++) {
		pri_bitmask = 1 << i;
		/* Check if COS was already used for SP */
		if (pri_bitmask & cos_bit_to_set) {
			/* COS wasn't used for SP */
			pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
			    i, pri_set);

			pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
			    i, pri_set);
			/* COS is used remove it from bitmap.*/
			cos_bit_to_set &= ~pri_bitmask;
			pri_set++;
		}
	}

	if (pri_set != max_num_of_cos) {
		DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
				   "entries were set\n");
		return -EINVAL;
	}

	if (port) {
		/* Only 6 usable clients*/
		REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
		       (u32)pri_cli_nig);

		REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
	} else {
		/* Only 9 usable clients*/
		const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
		const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);

		REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
		       pri_cli_nig_lsb);
		REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
		       pri_cli_nig_msb);

		REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
	}
	return 0;
}

/******************************************************************************
* Description:
*	Configure the COS to ETS according to BW and SP settings.
******************************************************************************/
int bnx2x_ets_e3b0_config(const struct link_params *params,
			 const struct link_vars *vars,
			 const struct bnx2x_ets_params *ets_params)
{
	struct bnx2x *bp = params->bp;
	int bnx2x_status = 0;
	const u8 port = params->port;
	u16 total_bw = 0;
	const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
	const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
	u8 cos_bw_bitmap = 0;
	u8 cos_sp_bitmap = 0;
	u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
	const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
		DCBX_E3B0_MAX_NUM_COS_PORT0;
	u8 cos_entry = 0;

	if (!CHIP_IS_E3B0(bp)) {
1090 1091
		DP(NETIF_MSG_LINK,
		   "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
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		return -EINVAL;
	}

	if ((ets_params->num_of_cos > max_num_of_cos)) {
		DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
				   "isn't supported\n");
		return -EINVAL;
	}

	/* Prepare sp strict priority parameters*/
	bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);

	/* Prepare BW parameters*/
	bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
						   &total_bw);
	if (0 != bnx2x_status) {
1108 1109
		DP(NETIF_MSG_LINK,
		   "bnx2x_ets_E3B0_config get_total_bw failed\n");
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		return -EINVAL;
	}

	/**
	 *  Upper bound is set according to current link speed (min_w_val
	 *  should be the same for upper bound and COS credit val).
	 */
	bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
	bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);


	for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
		if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
			cos_bw_bitmap |= (1 << cos_entry);
			/**
			 * The function also sets the BW in HW(not the mappin
			 * yet)
			 */
			bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
				bp, cos_entry, min_w_val_nig, min_w_val_pbf,
				total_bw,
				ets_params->cos[cos_entry].params.bw_params.bw,
				 port);
		} else if (bnx2x_cos_state_strict ==
			ets_params->cos[cos_entry].state){
			cos_sp_bitmap |= (1 << cos_entry);

			bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
				params,
				sp_pri_to_cos,
				ets_params->cos[cos_entry].params.sp_params.pri,
				cos_entry);

		} else {
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			DP(NETIF_MSG_LINK,
			   "bnx2x_ets_e3b0_config cos state not valid\n");
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			return -EINVAL;
		}
		if (0 != bnx2x_status) {
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			DP(NETIF_MSG_LINK,
			   "bnx2x_ets_e3b0_config set cos bw failed\n");
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			return bnx2x_status;
		}
	}

	/* Set SP register (which COS has higher priority) */
	bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
							 sp_pri_to_cos);

	if (0 != bnx2x_status) {
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		DP(NETIF_MSG_LINK,
		   "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
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		return bnx2x_status;
	}

	/* Set client mapping of BW and strict */
	bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
					      cos_sp_bitmap,
					      cos_bw_bitmap);

	if (0 != bnx2x_status) {
		DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
		return bnx2x_status;
	}
	return 0;
}
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static void bnx2x_ets_bw_limit_common(const struct link_params *params)
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{
	/* ETS disabled configuration */
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
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	/*
	 * defines which entries (clients) are subjected to WFQ arbitration
	 * COS0 0x8
	 * COS1 0x10
	 */
1186
	REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
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	/*
	 * mapping between the ARB_CREDIT_WEIGHT registers and actual
	 * client numbers (WEIGHT_0 does not actually have to represent
	 * client 0)
	 *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
	 *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
	 */
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	REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);

	REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
	       ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
	REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
	       ETS_BW_LIMIT_CREDIT_UPPER_BOUND);

	/* ETS mode enabled*/
	REG_WR(bp, PBF_REG_ETS_ENABLED, 1);

	/* Defines the number of consecutive slots for the strict priority */
	REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
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	/*
	 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
	 * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
	 * entry, 4 - COS1 entry.
	 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
	 * bit4   bit3	  bit2     bit1	   bit0
	 * MCP and debug are strict
	 */
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	REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);

	/* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
	REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
	       ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
	REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
	       ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
}

void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
			const u32 cos1_bw)
{
	/* ETS disabled configuration*/
	struct bnx2x *bp = params->bp;
	const u32 total_bw = cos0_bw + cos1_bw;
	u32 cos0_credit_weight = 0;
	u32 cos1_credit_weight = 0;

	DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");

	if ((0 == total_bw) ||
	    (0 == cos0_bw) ||
	    (0 == cos1_bw)) {
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		DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
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		return;
	}

	cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
		total_bw;
	cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
		total_bw;

	bnx2x_ets_bw_limit_common(params);

	REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
	REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);

	REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
	REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
}

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int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
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{
	/* ETS disabled configuration*/
	struct bnx2x *bp = params->bp;
	u32 val	= 0;

	DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1262
	/*
1263 1264 1265 1266 1267 1268 1269 1270
	 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
	 * as strict.  Bits 0,1,2 - debug and management entries,
	 * 3 - COS0 entry, 4 - COS1 entry.
	 *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
	 *  bit4   bit3	  bit2      bit1     bit0
	 * MCP and debug are strict
	 */
	REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1271
	/*
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	 * For strict priority entries defines the number of consecutive slots
	 * for the highest priority.
	 */
	REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
	/* ETS mode disable */
	REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
	/* Defines the number of consecutive slots for the strict priority */
	REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);

	/* Defines the number of consecutive slots for the strict priority */
	REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);

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	/*
	 * mapping between entry  priority to client number (0,1,2 -debug and
	 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
	 * 3bits client num.
	 *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
	 * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
	 * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
	 */
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	val = (0 == strict_cos) ? 0x2318 : 0x22E0;
	REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);

	return 0;
}
/******************************************************************/
1298
/*			PFC section				  */
1299 1300
/******************************************************************/

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static void bnx2x_update_pfc_xmac(struct link_params *params,
				  struct link_vars *vars,
				  u8 is_lb)
{
	struct bnx2x *bp = params->bp;
	u32 xmac_base;
	u32 pause_val, pfc0_val, pfc1_val;

	/* XMAC base adrr */
	xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;

	/* Initialize pause and pfc registers */
	pause_val = 0x18000;
	pfc0_val = 0xFFFF8000;
	pfc1_val = 0x2;

	/* No PFC support */
	if (!(params->feature_config_flags &
	      FEATURE_CONFIG_PFC_ENABLED)) {

		/*
		 * RX flow control - Process pause frame in receive direction
		 */
		if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
			pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;

		/*
		 * TX flow control - Send pause packet when buffer is full
		 */
		if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
			pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
	} else {/* PFC support */
		pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
			XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
			XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
			XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
	}

	/* Write pause and PFC registers */
	REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
	REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
	REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);


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	/* Set MAC address for source TX Pause/PFC frames */
	REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
	       ((params->mac_addr[2] << 24) |
		(params->mac_addr[3] << 16) |
		(params->mac_addr[4] << 8) |
		(params->mac_addr[5])));
	REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
	       ((params->mac_addr[0] << 8) |
		(params->mac_addr[1])));
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	udelay(30);
}
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static void bnx2x_emac_get_pfc_stat(struct link_params *params,
				    u32 pfc_frames_sent[2],
				    u32 pfc_frames_received[2])
{
	/* Read pfc statistic */
	struct bnx2x *bp = params->bp;
	u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
	u32 val_xon = 0;
	u32 val_xoff = 0;

	DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");

	/* PFC received frames */
	val_xoff = REG_RD(bp, emac_base +
				EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
	val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
	val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
	val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;

	pfc_frames_received[0] = val_xon + val_xoff;

	/* PFC received sent */
	val_xoff = REG_RD(bp, emac_base +
				EMAC_REG_RX_PFC_STATS_XOFF_SENT);
	val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
	val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
	val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;

	pfc_frames_sent[0] = val_xon + val_xoff;
}

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/* Read pfc statistic*/
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void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
			 u32 pfc_frames_sent[2],
			 u32 pfc_frames_received[2])
{
	/* Read pfc statistic */
	struct bnx2x *bp = params->bp;
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	DP(NETIF_MSG_LINK, "pfc statistic\n");

	if (!vars->link_up)
		return;

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	if (MAC_TYPE_EMAC == vars->mac_type) {
		DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1405 1406 1407 1408 1409 1410 1411
		bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
					pfc_frames_received);
	}
}
/******************************************************************/
/*			MAC/PBF section				  */
/******************************************************************/
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static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
{
	u32 mode, emac_base;
	/**
	 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
	 * (a value of 49==0x31) and make sure that the AUTO poll is off
	 */

	if (CHIP_IS_E2(bp))
		emac_base = GRCBASE_EMAC0;
	else
		emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
	mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
	mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
		  EMAC_MDIO_MODE_CLOCK_CNT);
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	if (USES_WARPCORE(bp))
		mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
	else
		mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1431 1432 1433 1434 1435 1436 1437

	mode |= (EMAC_MDIO_MODE_CLAUSE_45);
	REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);

	udelay(40);
}

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static void bnx2x_emac_init(struct link_params *params,
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			    struct link_vars *vars)
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{
	/* reset and unreset the emac core */
	struct bnx2x *bp = params->bp;
	u8 port = params->port;
	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
	u32 val;
	u16 timeout;

	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
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	       (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
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	udelay(5);
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
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	       (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
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	/* init emac - use read-modify-write */
	/* self clear reset */
	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
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	EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
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	timeout = 200;
1460
	do {
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		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
		DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
		if (!timeout) {
			DP(NETIF_MSG_LINK, "EMAC timeout!\n");
			return;
		}
		timeout--;
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	} while (val & EMAC_MODE_RESET);
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	bnx2x_set_mdio_clk(bp, params->chip_id, port);
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	/* Set mac address */
	val = ((params->mac_addr[0] << 8) |
		params->mac_addr[1]);
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	EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
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	val = ((params->mac_addr[2] << 24) |
	       (params->mac_addr[3] << 16) |
	       (params->mac_addr[4] << 8) |
		params->mac_addr[5]);
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	EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
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}

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static void bnx2x_set_xumac_nig(struct link_params *params,
				u16 tx_pause_en,
				u8 enable)
{
	struct bnx2x *bp = params->bp;

	REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
	       enable);
	REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
	       enable);
	REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
	       NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
}

static void bnx2x_umac_enable(struct link_params *params,
			    struct link_vars *vars, u8 lb)
{
	u32 val;
	u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
	struct bnx2x *bp = params->bp;
	/* Reset UMAC */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
	       (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
	usleep_range(1000, 1000);

	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
	       (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));

	DP(NETIF_MSG_LINK, "enabling UMAC\n");

	/**
	 * This register determines on which events the MAC will assert
	 * error on the i/f to the NIG along w/ EOP.
	 */

	/**
	 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
	 * params->port*0x14,      0xfffff.
	 */
	/* This register opens the gate for the UMAC despite its name */
	REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);

	val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
		UMAC_COMMAND_CONFIG_REG_PAD_EN |
		UMAC_COMMAND_CONFIG_REG_SW_RESET |
		UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
	switch (vars->line_speed) {
	case SPEED_10:
		val |= (0<<2);
		break;
	case SPEED_100:
		val |= (1<<2);
		break;
	case SPEED_1000:
		val |= (2<<2);
		break;
	case SPEED_2500:
		val |= (3<<2);
		break;
	default:
		DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
			       vars->line_speed);
		break;
	}
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	if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
		val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;

	if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
		val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;

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	REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
	udelay(50);

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	/* Set MAC address for source TX Pause/PFC frames (under SW reset) */
	REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
	       ((params->mac_addr[2] << 24) |
		(params->mac_addr[3] << 16) |
		(params->mac_addr[4] << 8) |
		(params->mac_addr[5])));
	REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
	       ((params->mac_addr[0] << 8) |
		(params->mac_addr[1])));

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	/* Enable RX and TX */
	val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
	val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
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		UMAC_COMMAND_CONFIG_REG_RX_ENA;
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	REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
	udelay(50);

	/* Remove SW Reset */
	val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;

	/* Check loopback mode */
	if (lb)
		val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
	REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);

	/*
	 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
	 * length used by the MAC receive logic to check frames.
	 */
	REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
	bnx2x_set_xumac_nig(params,
			    ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
	vars->mac_type = MAC_TYPE_UMAC;

}

static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
{
	u32 port4mode_ovwr_val;
	/* Check 4-port override enabled */
	port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
	if (port4mode_ovwr_val & (1<<0)) {
		/* Return 4-port mode override value */
		return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
	}
	/* Return 4-port mode from input pin */
	return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
}

/* Define the XMAC mode */
static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
{
	u32 is_port4mode = bnx2x_is_4_port_mode(bp);

	/**
	* In 4-port mode, need to set the mode only once, so if XMAC is
	* already out of reset, it means the mode has already been set,
	* and it must not* reset the XMAC again, since it controls both
	* ports of the path
	**/

	if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
	     MISC_REGISTERS_RESET_REG_2_XMAC)) {
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		DP(NETIF_MSG_LINK,
		   "XMAC already out of reset in 4-port mode\n");
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		return;
	}

	/* Hard reset */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
	       MISC_REGISTERS_RESET_REG_2_XMAC);
	usleep_range(1000, 1000);

	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
	       MISC_REGISTERS_RESET_REG_2_XMAC);
	if (is_port4mode) {
		DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");

		/*  Set the number of ports on the system side to up to 2 */
		REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);

		/* Set the number of ports on the Warp Core to 10G */
		REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
	} else {
		/*  Set the number of ports on the system side to 1 */
		REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
		if (max_speed == SPEED_10000) {
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			DP(NETIF_MSG_LINK,
			   "Init XMAC to 10G x 1 port per path\n");
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			/* Set the number of ports on the Warp Core to 10G */
			REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
		} else {
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			DP(NETIF_MSG_LINK,
			   "Init XMAC to 20G x 2 ports per path\n");
1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666
			/* Set the number of ports on the Warp Core to 20G */
			REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
		}
	}
	/* Soft reset */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
	       MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
	usleep_range(1000, 1000);

	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
	       MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);

}

static void bnx2x_xmac_disable(struct link_params *params)
{
	u8 port = params->port;
	struct bnx2x *bp = params->bp;
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	u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
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	if (REG_RD(bp, MISC_REG_RESET_REG_2) &
	    MISC_REGISTERS_RESET_REG_2_XMAC) {
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		/*
		 * Send an indication to change the state in the NIG back to XON
		 * Clearing this bit enables the next set of this bit to get
		 * rising edge
		 */
		pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
		       (pfc_ctrl & ~(1<<1)));
		REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
		       (pfc_ctrl | (1<<1)));
1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
		DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
		REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
		usleep_range(1000, 1000);
		bnx2x_set_xumac_nig(params, 0, 0);
		REG_WR(bp, xmac_base + XMAC_REG_CTRL,
		       XMAC_CTRL_REG_SOFT_RESET);
	}
}

static int bnx2x_xmac_enable(struct link_params *params,
			     struct link_vars *vars, u8 lb)
{
	u32 val, xmac_base;
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "enabling XMAC\n");

	xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;

	bnx2x_xmac_init(bp, vars->line_speed);

	/*
	 * This register determines on which events the MAC will assert
	 * error on the i/f to the NIG along w/ EOP.
	 */

	/*
	 * This register tells the NIG whether to send traffic to UMAC
	 * or XMAC
	 */
	REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);

	/* Set Max packet size */
	REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);

	/* CRC append for Tx packets */
	REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);

	/* update PFC */
	bnx2x_update_pfc_xmac(params, vars, 0);

	/* Enable TX and RX */
	val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;

	/* Check loopback mode */
	if (lb)
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		val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
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	REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
	bnx2x_set_xumac_nig(params,
			    ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);

	vars->mac_type = MAC_TYPE_XMAC;

	return 0;
}
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static int bnx2x_emac_enable(struct link_params *params,
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			     struct link_vars *vars, u8 lb)
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{
	struct bnx2x *bp = params->bp;
	u8 port = params->port;
	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
	u32 val;

	DP(NETIF_MSG_LINK, "enabling EMAC\n");

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	/* Disable BMAC */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
	       (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));

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	/* enable emac and not bmac */
	REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);

	/* ASIC */
	if (vars->phy_flags & PHY_XGXS_FLAG) {
		u32 ser_lane = ((params->lane_config &
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				 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
				PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
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		DP(NETIF_MSG_LINK, "XGXS\n");
		/* select the master lanes (out of 0-3) */
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		REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
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		/* select XGXS */
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		REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
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	} else { /* SerDes */
		DP(NETIF_MSG_LINK, "SerDes\n");
		/* select SerDes */
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		REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
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	}

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	bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
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		      EMAC_RX_MODE_RESET);
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	bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
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		      EMAC_TX_MODE_RESET);
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	if (CHIP_REV_IS_SLOW(bp)) {
		/* config GMII mode */
		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
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		EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
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	} else { /* ASIC */
		/* pause enable/disable */
		bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
			       EMAC_RX_MODE_FLOW_EN);

		bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801
			       (EMAC_TX_MODE_EXT_PAUSE_EN |
				EMAC_TX_MODE_FLOW_EN));
		if (!(params->feature_config_flags &
		      FEATURE_CONFIG_PFC_ENABLED)) {
			if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
				bnx2x_bits_en(bp, emac_base +
					      EMAC_REG_EMAC_RX_MODE,
					      EMAC_RX_MODE_FLOW_EN);

			if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
				bnx2x_bits_en(bp, emac_base +
					      EMAC_REG_EMAC_TX_MODE,
					      (EMAC_TX_MODE_EXT_PAUSE_EN |
					       EMAC_TX_MODE_FLOW_EN));
		} else
			bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
				      EMAC_TX_MODE_FLOW_EN);
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	}

	/* KEEP_VLAN_TAG, promiscuous */
	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
	val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1807

1808 1809 1810 1811 1812 1813 1814 1815
	/*
	 * Setting this bit causes MAC control frames (except for pause
	 * frames) to be passed on for processing. This setting has no
	 * affect on the operation of the pause frames. This bit effects
	 * all packets regardless of RX Parser packet sorting logic.
	 * Turn the PFC off to make sure we are in Xon state before
	 * enabling it.
	 */
1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831
	EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
		DP(NETIF_MSG_LINK, "PFC is enabled\n");
		/* Enable PFC again */
		EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
			EMAC_REG_RX_PFC_MODE_RX_EN |
			EMAC_REG_RX_PFC_MODE_TX_EN |
			EMAC_REG_RX_PFC_MODE_PRIORITIES);

		EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
			((0x0101 <<
			  EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
			 (0x00ff <<
			  EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
		val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
	}
1832
	EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
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	/* Set Loopback */
	val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
	if (lb)
		val |= 0x810;
	else
		val &= ~0x810;
1840
	EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
Y
Yaniv Rosner 已提交
1841

E
Eilon Greenstein 已提交
1842 1843 1844
	/* enable emac */
	REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);

Y
Yaniv Rosner 已提交
1845
	/* enable emac for jumbo packets */
1846
	EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
Y
Yaniv Rosner 已提交
1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860
		(EMAC_RX_MTU_SIZE_JUMBO_ENA |
		 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));

	/* strip CRC */
	REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);

	/* disable the NIG in/out to the bmac */
	REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
	REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
	REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);

	/* enable the NIG in/out to the emac */
	REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
	val = 0;
1861 1862 1863
	if ((params->feature_config_flags &
	      FEATURE_CONFIG_PFC_ENABLED) ||
	    (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
Y
Yaniv Rosner 已提交
1864 1865 1866 1867 1868
		val = 1;

	REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
	REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);

1869
	REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
Y
Yaniv Rosner 已提交
1870 1871 1872 1873 1874

	vars->mac_type = MAC_TYPE_EMAC;
	return 0;
}

1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906
static void bnx2x_update_pfc_bmac1(struct link_params *params,
				   struct link_vars *vars)
{
	u32 wb_data[2];
	struct bnx2x *bp = params->bp;
	u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
		NIG_REG_INGRESS_BMAC0_MEM;

	u32 val = 0x14;
	if ((!(params->feature_config_flags &
	      FEATURE_CONFIG_PFC_ENABLED)) &&
		(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
		/* Enable BigMAC to react on received Pause packets */
		val |= (1<<5);
	wb_data[0] = val;
	wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);

	/* tx control */
	val = 0xc0;
	if (!(params->feature_config_flags &
	      FEATURE_CONFIG_PFC_ENABLED) &&
		(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
		val |= 0x800000;
	wb_data[0] = val;
	wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
}

static void bnx2x_update_pfc_bmac2(struct link_params *params,
				   struct link_vars *vars,
				   u8 is_lb)
D
Dmitry Kravkov 已提交
1907 1908 1909 1910 1911 1912 1913 1914 1915 1916
{
	/*
	 * Set rx control: Strip CRC and enable BigMAC to relay
	 * control packets to the system as well
	 */
	u32 wb_data[2];
	struct bnx2x *bp = params->bp;
	u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
		NIG_REG_INGRESS_BMAC0_MEM;
	u32 val = 0x14;
Y
Yaniv Rosner 已提交
1917

1918 1919 1920
	if ((!(params->feature_config_flags &
	      FEATURE_CONFIG_PFC_ENABLED)) &&
		(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
D
Dmitry Kravkov 已提交
1921 1922 1923 1924
		/* Enable BigMAC to react on received Pause packets */
		val |= (1<<5);
	wb_data[0] = val;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
1925
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
D
Dmitry Kravkov 已提交
1926
	udelay(30);
Y
Yaniv Rosner 已提交
1927

D
Dmitry Kravkov 已提交
1928 1929
	/* Tx control */
	val = 0xc0;
1930 1931 1932
	if (!(params->feature_config_flags &
				FEATURE_CONFIG_PFC_ENABLED) &&
	    (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
D
Dmitry Kravkov 已提交
1933 1934 1935
		val |= 0x800000;
	wb_data[0] = val;
	wb_data[1] = 0;
1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);

	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
		DP(NETIF_MSG_LINK, "PFC is enabled\n");
		/* Enable PFC RX & TX & STATS and set 8 COS  */
		wb_data[0] = 0x0;
		wb_data[0] |= (1<<0);  /* RX */
		wb_data[0] |= (1<<1);  /* TX */
		wb_data[0] |= (1<<2);  /* Force initial Xon */
		wb_data[0] |= (1<<3);  /* 8 cos */
		wb_data[0] |= (1<<5);  /* STATS */
		wb_data[1] = 0;
		REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
			    wb_data, 2);
		/* Clear the force Xon */
		wb_data[0] &= ~(1<<2);
	} else {
		DP(NETIF_MSG_LINK, "PFC is disabled\n");
		/* disable PFC RX & TX & STATS and set 8 COS */
		wb_data[0] = 0x8;
		wb_data[1] = 0;
	}

	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
D
Dmitry Kravkov 已提交
1960

1961 1962 1963 1964 1965 1966
	/*
	 * Set Time (based unit is 512 bit time) between automatic
	 * re-sending of PP packets amd enable automatic re-send of
	 * Per-Priroity Packet as long as pp_gen is asserted and
	 * pp_disable is low.
	 */
D
Dmitry Kravkov 已提交
1967
	val = 0x8000;
1968 1969 1970
	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
		val |= (1<<16); /* enable automatic re-send */

D
Dmitry Kravkov 已提交
1971 1972 1973
	wb_data[0] = val;
	wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
Y
Yaniv Rosner 已提交
1974
		    wb_data, 2);
D
Dmitry Kravkov 已提交
1975 1976 1977 1978 1979 1980 1981

	/* mac control */
	val = 0x3; /* Enable RX and TX */
	if (is_lb) {
		val |= 0x4; /* Local loopback */
		DP(NETIF_MSG_LINK, "enable bmac loopback\n");
	}
1982 1983 1984
	/* When PFC enabled, Pass pause frames towards the NIG. */
	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
		val |= ((1<<6)|(1<<5));
D
Dmitry Kravkov 已提交
1985 1986 1987

	wb_data[0] = val;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
1988
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
D
Dmitry Kravkov 已提交
1989 1990
}

1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159

/* PFC BRB internal port configuration params */
struct bnx2x_pfc_brb_threshold_val {
	u32 pause_xoff;
	u32 pause_xon;
	u32 full_xoff;
	u32 full_xon;
};

struct bnx2x_pfc_brb_e3b0_val {
	u32 full_lb_xoff_th;
	u32 full_lb_xon_threshold;
	u32 lb_guarantied;
	u32 mac_0_class_t_guarantied;
	u32 mac_0_class_t_guarantied_hyst;
	u32 mac_1_class_t_guarantied;
	u32 mac_1_class_t_guarantied_hyst;
};

struct bnx2x_pfc_brb_th_val {
	struct bnx2x_pfc_brb_threshold_val pauseable_th;
	struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
};
static int bnx2x_pfc_brb_get_config_params(
				struct link_params *params,
				struct bnx2x_pfc_brb_th_val *config_val)
{
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
	if (CHIP_IS_E2(bp)) {
		config_val->pauseable_th.pause_xoff =
		    PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
		config_val->pauseable_th.pause_xon =
		    PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
		config_val->pauseable_th.full_xoff =
		    PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
		config_val->pauseable_th.full_xon =
		    PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
		/* non pause able*/
		config_val->non_pauseable_th.pause_xoff =
		    PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
		config_val->non_pauseable_th.pause_xon =
		    PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
		config_val->non_pauseable_th.full_xoff =
		    PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
		config_val->non_pauseable_th.full_xon =
		    PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
	} else if (CHIP_IS_E3A0(bp)) {
		config_val->pauseable_th.pause_xoff =
		    PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
		config_val->pauseable_th.pause_xon =
		    PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
		config_val->pauseable_th.full_xoff =
		    PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
		config_val->pauseable_th.full_xon =
		    PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
		/* non pause able*/
		config_val->non_pauseable_th.pause_xoff =
		    PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
		config_val->non_pauseable_th.pause_xon =
		    PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
		config_val->non_pauseable_th.full_xoff =
		    PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
		config_val->non_pauseable_th.full_xon =
		    PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
	} else if (CHIP_IS_E3B0(bp)) {
		if (params->phy[INT_PHY].flags &
		    FLAGS_4_PORT_MODE) {
			config_val->pauseable_th.pause_xoff =
			    PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
			config_val->pauseable_th.pause_xon =
			    PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
			config_val->pauseable_th.full_xoff =
			    PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
			config_val->pauseable_th.full_xon =
			    PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
			/* non pause able*/
			config_val->non_pauseable_th.pause_xoff =
			    PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
			config_val->non_pauseable_th.pause_xon =
			    PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
			config_val->non_pauseable_th.full_xoff =
			    PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
			config_val->non_pauseable_th.full_xon =
			    PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
	    } else {
		config_val->pauseable_th.pause_xoff =
		    PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
		config_val->pauseable_th.pause_xon =
		    PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
		config_val->pauseable_th.full_xoff =
		    PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
		config_val->pauseable_th.full_xon =
			PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
		/* non pause able*/
		config_val->non_pauseable_th.pause_xoff =
		    PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
		config_val->non_pauseable_th.pause_xon =
		    PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
		config_val->non_pauseable_th.full_xoff =
		    PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
		config_val->non_pauseable_th.full_xon =
		    PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
	    }
	} else
	    return -EINVAL;

	return 0;
}


static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
						 struct bnx2x_pfc_brb_e3b0_val
						 *e3b0_val,
						 u32 cos0_pauseable,
						 u32 cos1_pauseable)
{
	if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
		e3b0_val->full_lb_xoff_th =
		    PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
		e3b0_val->full_lb_xon_threshold =
		    PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
		e3b0_val->lb_guarantied =
		    PFC_E3B0_4P_LB_GUART;
		e3b0_val->mac_0_class_t_guarantied =
		    PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
		e3b0_val->mac_0_class_t_guarantied_hyst =
		    PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
		e3b0_val->mac_1_class_t_guarantied =
		    PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
		e3b0_val->mac_1_class_t_guarantied_hyst =
		    PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
	} else {
		e3b0_val->full_lb_xoff_th =
		    PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
		e3b0_val->full_lb_xon_threshold =
		    PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
		e3b0_val->mac_0_class_t_guarantied_hyst =
		    PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
		e3b0_val->mac_1_class_t_guarantied =
		    PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
		e3b0_val->mac_1_class_t_guarantied_hyst =
		    PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;

		if (cos0_pauseable != cos1_pauseable) {
			/* nonpauseable= Lossy + pauseable = Lossless*/
			e3b0_val->lb_guarantied =
			    PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
			e3b0_val->mac_0_class_t_guarantied =
			    PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
		} else if (cos0_pauseable) {
			/* Lossless +Lossless*/
			e3b0_val->lb_guarantied =
			    PFC_E3B0_2P_PAUSE_LB_GUART;
			e3b0_val->mac_0_class_t_guarantied =
			    PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
		} else {
			/* Lossy +Lossy*/
			e3b0_val->lb_guarantied =
			    PFC_E3B0_2P_NON_PAUSE_LB_GUART;
			e3b0_val->mac_0_class_t_guarantied =
			    PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
		}
	}
}
static int bnx2x_update_pfc_brb(struct link_params *params,
				struct link_vars *vars,
				struct bnx2x_nig_brb_pfc_port_params
				*pfc_params)
2160 2161
{
	struct bnx2x *bp = params->bp;
2162 2163 2164 2165
	struct bnx2x_pfc_brb_th_val config_val = { {0} };
	struct bnx2x_pfc_brb_threshold_val *reg_th_config =
	    &config_val.pauseable_th;
	struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2166 2167
	int set_pfc = params->feature_config_flags &
		FEATURE_CONFIG_PFC_ENABLED;
2168 2169
	int bnx2x_status = 0;
	u8 port = params->port;
2170 2171

	/* default - pause configuration */
2172 2173 2174 2175
	reg_th_config = &config_val.pauseable_th;
	bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
	if (0 != bnx2x_status)
		return bnx2x_status;
2176 2177 2178

	if (set_pfc && pfc_params)
		/* First COS */
2179 2180
		if (!pfc_params->cos0_pauseable)
			reg_th_config = &config_val.non_pauseable_th;
2181 2182 2183 2184
	/*
	 * The number of free blocks below which the pause signal to class 0
	 * of MAC #n is asserted. n=0,1
	 */
2185 2186 2187
	REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
	       BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
	       reg_th_config->pause_xoff);
2188 2189 2190 2191
	/*
	 * The number of free blocks above which the pause signal to class 0
	 * of MAC #n is de-asserted. n=0,1
	 */
2192 2193
	REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
	       BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2194 2195 2196 2197
	/*
	 * The number of free blocks below which the full signal to class 0
	 * of MAC #n is asserted. n=0,1
	 */
2198 2199
	REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
	       BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2200 2201 2202 2203
	/*
	 * The number of free blocks above which the full signal to class 0
	 * of MAC #n is de-asserted. n=0,1
	 */
2204 2205
	REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
	       BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2206 2207 2208

	if (set_pfc && pfc_params) {
		/* Second COS */
2209 2210 2211 2212
		if (pfc_params->cos1_pauseable)
			reg_th_config = &config_val.pauseable_th;
		else
			reg_th_config = &config_val.non_pauseable_th;
2213
		/*
2214 2215
		 * The number of free blocks below which the pause signal to
		 * class 1 of MAC #n is asserted. n=0,1
2216 2217 2218 2219
		**/
		REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
		       BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
		       reg_th_config->pause_xoff);
2220
		/*
2221 2222
		 * The number of free blocks above which the pause signal to
		 * class 1 of MAC #n is de-asserted. n=0,1
2223
		 */
2224 2225 2226
		REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
		       BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
		       reg_th_config->pause_xon);
2227
		/*
2228 2229
		 * The number of free blocks below which the full signal to
		 * class 1 of MAC #n is asserted. n=0,1
2230
		 */
2231 2232 2233
		REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
		       BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
		       reg_th_config->full_xoff);
2234
		/*
2235 2236
		 * The number of free blocks above which the full signal to
		 * class 1 of MAC #n is de-asserted. n=0,1
2237
		 */
2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325
		REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
		       BRB1_REG_FULL_1_XON_THRESHOLD_0,
		       reg_th_config->full_xon);


		if (CHIP_IS_E3B0(bp)) {
			/*Should be done by init tool */
			/*
			* BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
			* reset value
			* 944
			*/

			/**
			 * The hysteresis on the guarantied buffer space for the Lb port
			 * before signaling XON.
			 **/
			REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);

			bnx2x_pfc_brb_get_e3b0_config_params(
			    params,
			    &e3b0_val,
			    pfc_params->cos0_pauseable,
			    pfc_params->cos1_pauseable);
			/**
			 * The number of free blocks below which the full signal to the
			 * LB port is asserted.
			*/
			REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
				   e3b0_val.full_lb_xoff_th);
			/**
			 * The number of free blocks above which the full signal to the
			 * LB port is de-asserted.
			*/
			REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
				   e3b0_val.full_lb_xon_threshold);
			/**
			* The number of blocks guarantied for the MAC #n port. n=0,1
			*/

			/*The number of blocks guarantied for the LB port.*/
			REG_WR(bp, BRB1_REG_LB_GUARANTIED,
			       e3b0_val.lb_guarantied);

			/**
			 * The number of blocks guarantied for the MAC #n port.
			*/
			REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
				   2 * e3b0_val.mac_0_class_t_guarantied);
			REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
				   2 * e3b0_val.mac_1_class_t_guarantied);
			/**
			 * The number of blocks guarantied for class #t in MAC0. t=0,1
			*/
			REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
			       e3b0_val.mac_0_class_t_guarantied);
			REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
			       e3b0_val.mac_0_class_t_guarantied);
			/**
			 * The hysteresis on the guarantied buffer space for class in
			 * MAC0.  t=0,1
			*/
			REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
			       e3b0_val.mac_0_class_t_guarantied_hyst);
			REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
			       e3b0_val.mac_0_class_t_guarantied_hyst);

			/**
			 * The number of blocks guarantied for class #t in MAC1.t=0,1
			*/
			REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
			       e3b0_val.mac_1_class_t_guarantied);
			REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
			       e3b0_val.mac_1_class_t_guarantied);
			/**
			 * The hysteresis on the guarantied buffer space for class #t
			* in MAC1.  t=0,1
			*/
			REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
			       e3b0_val.mac_1_class_t_guarantied_hyst);
			REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
			       e3b0_val.mac_1_class_t_guarantied_hyst);

	    }

	}

	return bnx2x_status;
2326 2327
}

2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375
/******************************************************************************
* Description:
*  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
*  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
******************************************************************************/
int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
					      u8 cos_entry,
					      u32 priority_mask, u8 port)
{
	u32 nig_reg_rx_priority_mask_add = 0;

	switch (cos_entry) {
	case 0:
	     nig_reg_rx_priority_mask_add = (port) ?
		 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
		 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
	     break;
	case 1:
	    nig_reg_rx_priority_mask_add = (port) ?
		NIG_REG_P1_RX_COS1_PRIORITY_MASK :
		NIG_REG_P0_RX_COS1_PRIORITY_MASK;
	    break;
	case 2:
	    nig_reg_rx_priority_mask_add = (port) ?
		NIG_REG_P1_RX_COS2_PRIORITY_MASK :
		NIG_REG_P0_RX_COS2_PRIORITY_MASK;
	    break;
	case 3:
	    if (port)
		return -EINVAL;
	    nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
	    break;
	case 4:
	    if (port)
		return -EINVAL;
	    nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
	    break;
	case 5:
	    if (port)
		return -EINVAL;
	    nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
	    break;
	}

	REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);

	return 0;
}
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Yaniv Rosner 已提交
2376 2377 2378 2379 2380 2381 2382 2383 2384
static void bnx2x_update_mng(struct link_params *params, u32 link_status)
{
	struct bnx2x *bp = params->bp;

	REG_WR(bp, params->shmem_base +
	       offsetof(struct shmem_region,
			port_mb[params->port].link_status), link_status);
}

2385 2386 2387 2388 2389 2390 2391 2392
static void bnx2x_update_pfc_nig(struct link_params *params,
		struct link_vars *vars,
		struct bnx2x_nig_brb_pfc_port_params *nig_params)
{
	u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
	u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
	u32 pkt_priority_to_cos = 0;
	struct bnx2x *bp = params->bp;
2393 2394
	u8 port = params->port;

2395 2396 2397 2398
	int set_pfc = params->feature_config_flags &
		FEATURE_CONFIG_PFC_ENABLED;
	DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");

2399
	/*
2400 2401 2402 2403 2404 2405 2406
	 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
	 * MAC control frames (that are not pause packets)
	 * will be forwarded to the XCM.
	 */
	xcm_mask = REG_RD(bp,
				port ? NIG_REG_LLH1_XCM_MASK :
				NIG_REG_LLH0_XCM_MASK);
2407
	/*
2408 2409 2410 2411 2412 2413 2414
	 * nig params will override non PFC params, since it's possible to
	 * do transition from PFC to SAFC
	 */
	if (set_pfc) {
		pause_enable = 0;
		llfc_out_en = 0;
		llfc_enable = 0;
2415 2416 2417
		if (CHIP_IS_E3(bp))
			ppp_enable = 0;
		else
2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435
		ppp_enable = 1;
		xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
				     NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
		xcm0_out_en = 0;
		p0_hwpfc_enable = 1;
	} else  {
		if (nig_params) {
			llfc_out_en = nig_params->llfc_out_en;
			llfc_enable = nig_params->llfc_enable;
			pause_enable = nig_params->pause_enable;
		} else  /*defaul non PFC mode - PAUSE */
			pause_enable = 1;

		xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
			NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
		xcm0_out_en = 1;
	}

2436 2437 2438
	if (CHIP_IS_E3(bp))
		REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
		       NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460
	REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
	       NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
	REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
	       NIG_REG_LLFC_ENABLE_0, llfc_enable);
	REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
	       NIG_REG_PAUSE_ENABLE_0, pause_enable);

	REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
	       NIG_REG_PPP_ENABLE_0, ppp_enable);

	REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
	       NIG_REG_LLH0_XCM_MASK, xcm_mask);

	REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);

	/* output enable for RX_XCM # IF */
	REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);

	/* HW PFC TX enable */
	REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);

	if (nig_params) {
2461
		u8 i = 0;
2462 2463
		pkt_priority_to_cos = nig_params->pkt_priority_to_cos;

2464 2465 2466
		for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
			bnx2x_pfc_nig_rx_priority_mask(bp, i,
		nig_params->rx_cos_priority_mask[i], port);
2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480

		REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
		       NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
		       nig_params->llfc_high_priority_classes);

		REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
		       NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
		       nig_params->llfc_low_priority_classes);
	}
	REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
	       NIG_REG_P0_PKT_PRIORITY_TO_COS,
	       pkt_priority_to_cos);
}

2481
int bnx2x_update_pfc(struct link_params *params,
2482 2483 2484
		      struct link_vars *vars,
		      struct bnx2x_nig_brb_pfc_port_params *pfc_params)
{
2485
	/*
2486 2487 2488 2489 2490 2491
	 * The PFC and pause are orthogonal to one another, meaning when
	 * PFC is enabled, the pause are disabled, and when PFC is
	 * disabled, pause are set according to the pause result.
	 */
	u32 val;
	struct bnx2x *bp = params->bp;
2492 2493
	int bnx2x_status = 0;
	u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
Y
Yaniv Rosner 已提交
2494 2495 2496 2497 2498 2499 2500 2501

	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
		vars->link_status |= LINK_STATUS_PFC_ENABLED;
	else
		vars->link_status &= ~LINK_STATUS_PFC_ENABLED;

	bnx2x_update_mng(params, vars->link_status);

2502 2503 2504 2505
	/* update NIG params */
	bnx2x_update_pfc_nig(params, vars, pfc_params);

	/* update BRB params */
2506 2507 2508
	bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
	if (0 != bnx2x_status)
		return bnx2x_status;
2509 2510

	if (!vars->link_up)
2511
		return bnx2x_status;
2512 2513

	DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2514 2515 2516 2517 2518
	if (CHIP_IS_E3(bp))
		bnx2x_update_pfc_xmac(params, vars, 0);
	else {
		val = REG_RD(bp, MISC_REG_RESET_REG_2);
		if ((val &
2519
		     (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2520 2521 2522 2523 2524
		    == 0) {
			DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
			bnx2x_emac_enable(params, vars, 0);
			return bnx2x_status;
		}
2525

2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538
		if (CHIP_IS_E2(bp))
			bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
		else
			bnx2x_update_pfc_bmac1(params, vars);

		val = 0;
		if ((params->feature_config_flags &
		     FEATURE_CONFIG_PFC_ENABLED) ||
		    (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
			val = 1;
		REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
	}
	return bnx2x_status;
2539
}
D
Dmitry Kravkov 已提交
2540

2541

Y
Yaniv Rosner 已提交
2542 2543 2544
static int bnx2x_bmac1_enable(struct link_params *params,
			      struct link_vars *vars,
			      u8 is_lb)
Y
Yaniv Rosner 已提交
2545 2546 2547 2548 2549 2550 2551 2552
{
	struct bnx2x *bp = params->bp;
	u8 port = params->port;
	u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
			       NIG_REG_INGRESS_BMAC0_MEM;
	u32 wb_data[2];
	u32 val;

D
Dmitry Kravkov 已提交
2553
	DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
Y
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2554 2555 2556 2557

	/* XGXS control */
	wb_data[0] = 0x3c;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2558 2559
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
		    wb_data, 2);
Y
Yaniv Rosner 已提交
2560 2561 2562 2563 2564 2565 2566 2567

	/* tx MAC SA */
	wb_data[0] = ((params->mac_addr[2] << 24) |
		       (params->mac_addr[3] << 16) |
		       (params->mac_addr[4] << 8) |
			params->mac_addr[5]);
	wb_data[1] = ((params->mac_addr[0] << 8) |
			params->mac_addr[1]);
Y
Yaniv Rosner 已提交
2568
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
Y
Yaniv Rosner 已提交
2569 2570 2571 2572 2573 2574 2575 2576 2577

	/* mac control */
	val = 0x3;
	if (is_lb) {
		val |= 0x4;
		DP(NETIF_MSG_LINK, "enable bmac loopback\n");
	}
	wb_data[0] = val;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2578
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
Y
Yaniv Rosner 已提交
2579 2580 2581 2582

	/* set rx mtu */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2583
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
Y
Yaniv Rosner 已提交
2584

2585
	bnx2x_update_pfc_bmac1(params, vars);
Y
Yaniv Rosner 已提交
2586 2587 2588 2589

	/* set tx mtu */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2590
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
Y
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2591 2592 2593 2594

	/* set cnt max size */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2595
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
Y
Yaniv Rosner 已提交
2596 2597 2598 2599 2600 2601

	/* configure safc */
	wb_data[0] = 0x1000200;
	wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
		    wb_data, 2);
D
Dmitry Kravkov 已提交
2602 2603 2604 2605

	return 0;
}

Y
Yaniv Rosner 已提交
2606 2607 2608
static int bnx2x_bmac2_enable(struct link_params *params,
			      struct link_vars *vars,
			      u8 is_lb)
D
Dmitry Kravkov 已提交
2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619
{
	struct bnx2x *bp = params->bp;
	u8 port = params->port;
	u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
			       NIG_REG_INGRESS_BMAC0_MEM;
	u32 wb_data[2];

	DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");

	wb_data[0] = 0;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2620
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
D
Dmitry Kravkov 已提交
2621 2622 2623 2624 2625
	udelay(30);

	/* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
	wb_data[0] = 0x3c;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2626 2627
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
		    wb_data, 2);
D
Dmitry Kravkov 已提交
2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638

	udelay(30);

	/* tx MAC SA */
	wb_data[0] = ((params->mac_addr[2] << 24) |
		       (params->mac_addr[3] << 16) |
		       (params->mac_addr[4] << 8) |
			params->mac_addr[5]);
	wb_data[1] = ((params->mac_addr[0] << 8) |
			params->mac_addr[1]);
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
Y
Yaniv Rosner 已提交
2639
		    wb_data, 2);
D
Dmitry Kravkov 已提交
2640 2641 2642 2643 2644 2645 2646

	udelay(30);

	/* Configure SAFC */
	wb_data[0] = 0x1000200;
	wb_data[1] = 0;
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
Y
Yaniv Rosner 已提交
2647
		    wb_data, 2);
D
Dmitry Kravkov 已提交
2648 2649 2650 2651 2652
	udelay(30);

	/* set rx mtu */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2653
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
D
Dmitry Kravkov 已提交
2654 2655 2656 2657 2658
	udelay(30);

	/* set tx mtu */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2659
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
D
Dmitry Kravkov 已提交
2660 2661 2662 2663
	udelay(30);
	/* set cnt max size */
	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
	wb_data[1] = 0;
Y
Yaniv Rosner 已提交
2664
	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
D
Dmitry Kravkov 已提交
2665
	udelay(30);
2666
	bnx2x_update_pfc_bmac2(params, vars, is_lb);
D
Dmitry Kravkov 已提交
2667 2668 2669 2670

	return 0;
}

Y
Yaniv Rosner 已提交
2671 2672 2673
static int bnx2x_bmac_enable(struct link_params *params,
			     struct link_vars *vars,
			     u8 is_lb)
D
Dmitry Kravkov 已提交
2674
{
Y
Yaniv Rosner 已提交
2675 2676
	int rc = 0;
	u8 port = params->port;
D
Dmitry Kravkov 已提交
2677 2678 2679 2680
	struct bnx2x *bp = params->bp;
	u32 val;
	/* reset and unreset the BigMac */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
Y
Yaniv Rosner 已提交
2681
	       (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2682
	msleep(1);
D
Dmitry Kravkov 已提交
2683 2684

	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
Y
Yaniv Rosner 已提交
2685
	       (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
D
Dmitry Kravkov 已提交
2686 2687 2688 2689 2690 2691 2692 2693 2694

	/* enable access for bmac registers */
	REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);

	/* Enable BMAC according to BMAC type*/
	if (CHIP_IS_E2(bp))
		rc = bnx2x_bmac2_enable(params, vars, is_lb);
	else
		rc = bnx2x_bmac1_enable(params, vars, is_lb);
Y
Yaniv Rosner 已提交
2695 2696 2697 2698
	REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
	REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
	REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
	val = 0;
2699 2700 2701
	if ((params->feature_config_flags &
	      FEATURE_CONFIG_PFC_ENABLED) ||
	    (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
Y
Yaniv Rosner 已提交
2702 2703 2704 2705 2706 2707 2708 2709 2710
		val = 1;
	REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
	REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
	REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
	REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
	REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
	REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);

	vars->mac_type = MAC_TYPE_BMAC;
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	return rc;
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}

static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
{
	u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
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			NIG_REG_INGRESS_BMAC0_MEM;
Y
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	u32 wb_data[2];
2719
	u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
Y
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	/* Only if the bmac is out of reset */
	if (REG_RD(bp, MISC_REG_RESET_REG_2) &
			(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
	    nig_bmac_enable) {

D
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2726 2727 2728
		if (CHIP_IS_E2(bp)) {
			/* Clear Rx Enable bit in BMAC_CONTROL register */
			REG_RD_DMAE(bp, bmac_addr +
Y
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2729 2730
				    BIGMAC2_REGISTER_BMAC_CONTROL,
				    wb_data, 2);
D
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2731 2732
			wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
			REG_WR_DMAE(bp, bmac_addr +
Y
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2733 2734
				    BIGMAC2_REGISTER_BMAC_CONTROL,
				    wb_data, 2);
D
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2735 2736 2737 2738 2739 2740 2741 2742 2743 2744
		} else {
			/* Clear Rx Enable bit in BMAC_CONTROL register */
			REG_RD_DMAE(bp, bmac_addr +
					BIGMAC_REGISTER_BMAC_CONTROL,
					wb_data, 2);
			wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
			REG_WR_DMAE(bp, bmac_addr +
					BIGMAC_REGISTER_BMAC_CONTROL,
					wb_data, 2);
		}
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		msleep(1);
	}
}

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static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
			    u32 line_speed)
Y
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2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777
{
	struct bnx2x *bp = params->bp;
	u8 port = params->port;
	u32 init_crd, crd;
	u32 count = 1000;

	/* disable port */
	REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);

	/* wait for init credit */
	init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
	crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
	DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);

	while ((init_crd != crd) && count) {
		msleep(5);

		crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
		count--;
	}
	crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
	if (init_crd != crd) {
		DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
			  init_crd, crd);
		return -EINVAL;
	}

2778
	if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
Y
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2779 2780 2781 2782 2783
	    line_speed == SPEED_10 ||
	    line_speed == SPEED_100 ||
	    line_speed == SPEED_1000 ||
	    line_speed == SPEED_2500) {
		REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
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		/* update threshold */
		REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
		/* update init credit */
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		init_crd = 778;		/* (800-18-4) */
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2788 2789 2790 2791

	} else {
		u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
			      ETH_OVREHEAD)/16;
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		REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
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2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819
		/* update threshold */
		REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
		/* update init credit */
		switch (line_speed) {
		case SPEED_10000:
			init_crd = thresh + 553 - 22;
			break;
		default:
			DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
				  line_speed);
			return -EINVAL;
		}
	}
	REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
	DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
		 line_speed, init_crd);

	/* probe the credit changes */
	REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
	msleep(5);
	REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);

	/* enable port */
	REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
	return 0;
}

2820 2821
/**
 * bnx2x_get_emac_base - retrive emac base address
2822
 *
2823 2824 2825
 * @bp:			driver handle
 * @mdc_mdio_access:	access type
 * @port:		port id
2826 2827 2828 2829 2830 2831 2832 2833 2834
 *
 * This function selects the MDC/MDIO access (through emac0 or
 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
 * phy has a default access mode, which could also be overridden
 * by nvram configuration. This parameter, whether this is the
 * default phy configuration, or the nvram overrun
 * configuration, is passed here as mdc_mdio_access and selects
 * the emac_base for the CL45 read/writes operations
 */
2835 2836
static u32 bnx2x_get_emac_base(struct bnx2x *bp,
			       u32 mdc_mdio_access, u8 port)
Y
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{
2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848
	u32 emac_base = 0;
	switch (mdc_mdio_access) {
	case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
		break;
	case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
		if (REG_RD(bp, NIG_REG_PORT_SWAP))
			emac_base = GRCBASE_EMAC1;
		else
			emac_base = GRCBASE_EMAC0;
		break;
	case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
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		if (REG_RD(bp, NIG_REG_PORT_SWAP))
			emac_base = GRCBASE_EMAC0;
		else
			emac_base = GRCBASE_EMAC1;
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		break;
2854 2855 2856 2857
	case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
		emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
		break;
	case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
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		emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
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		break;
	default:
		break;
	}
	return emac_base;

}

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2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943
/******************************************************************/
/*			CL22 access functions			  */
/******************************************************************/
static int bnx2x_cl22_write(struct bnx2x *bp,
				       struct bnx2x_phy *phy,
				       u16 reg, u16 val)
{
	u32 tmp, mode;
	u8 i;
	int rc = 0;
	/* Switch to CL22 */
	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
	       mode & ~EMAC_MDIO_MODE_CLAUSE_45);

	/* address */
	tmp = ((phy->addr << 21) | (reg << 16) | val |
	       EMAC_MDIO_COMM_COMMAND_WRITE_22 |
	       EMAC_MDIO_COMM_START_BUSY);
	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);

	for (i = 0; i < 50; i++) {
		udelay(10);

		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
		if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);
			break;
		}
	}
	if (tmp & EMAC_MDIO_COMM_START_BUSY) {
		DP(NETIF_MSG_LINK, "write phy register failed\n");
		rc = -EFAULT;
	}
	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
	return rc;
}

static int bnx2x_cl22_read(struct bnx2x *bp,
				      struct bnx2x_phy *phy,
				      u16 reg, u16 *ret_val)
{
	u32 val, mode;
	u16 i;
	int rc = 0;

	/* Switch to CL22 */
	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
	       mode & ~EMAC_MDIO_MODE_CLAUSE_45);

	/* address */
	val = ((phy->addr << 21) | (reg << 16) |
	       EMAC_MDIO_COMM_COMMAND_READ_22 |
	       EMAC_MDIO_COMM_START_BUSY);
	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);

	for (i = 0; i < 50; i++) {
		udelay(10);

		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
		if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
			*ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
			udelay(5);
			break;
		}
	}
	if (val & EMAC_MDIO_COMM_START_BUSY) {
		DP(NETIF_MSG_LINK, "read phy register failed\n");

		*ret_val = 0;
		rc = -EFAULT;
	}
	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
	return rc;
}

2944 2945 2946
/******************************************************************/
/*			CL45 access functions			  */
/******************************************************************/
2947 2948
static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
			   u8 devad, u16 reg, u16 *ret_val)
Y
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2949
{
2950 2951
	u32 val;
	u16 i;
Y
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2952
	int rc = 0;
2953 2954 2955
	if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
			      EMAC_MDIO_STATUS_10MB);
Y
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2956
	/* address */
2957
	val = ((phy->addr << 21) | (devad << 16) | reg |
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2958 2959
	       EMAC_MDIO_COMM_COMMAND_ADDRESS |
	       EMAC_MDIO_COMM_START_BUSY);
2960
	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
Y
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2961 2962 2963 2964

	for (i = 0; i < 50; i++) {
		udelay(10);

2965 2966
		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
		if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
Y
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			udelay(5);
			break;
		}
	}
2971 2972
	if (val & EMAC_MDIO_COMM_START_BUSY) {
		DP(NETIF_MSG_LINK, "read phy register failed\n");
2973
		netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2974
		*ret_val = 0;
Y
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		rc = -EFAULT;
	} else {
		/* data */
2978 2979
		val = ((phy->addr << 21) | (devad << 16) |
		       EMAC_MDIO_COMM_COMMAND_READ_45 |
Y
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		       EMAC_MDIO_COMM_START_BUSY);
2981
		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
Y
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2982 2983 2984 2985

		for (i = 0; i < 50; i++) {
			udelay(10);

2986
			val = REG_RD(bp, phy->mdio_ctrl +
Y
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2987
				     EMAC_REG_EMAC_MDIO_COMM);
2988 2989
			if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
				*ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
Y
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2990 2991 2992
				break;
			}
		}
2993 2994
		if (val & EMAC_MDIO_COMM_START_BUSY) {
			DP(NETIF_MSG_LINK, "read phy register failed\n");
2995
			netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2996
			*ret_val = 0;
Y
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2997 2998 2999
			rc = -EFAULT;
		}
	}
3000 3001 3002 3003 3004 3005 3006 3007
	/* Work around for E3 A0 */
	if (phy->flags & FLAGS_MDC_MDIO_WA) {
		phy->flags ^= FLAGS_DUMMY_READ;
		if (phy->flags & FLAGS_DUMMY_READ) {
			u16 temp_val;
			bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
		}
	}
Y
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3008

3009 3010 3011
	if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
			       EMAC_MDIO_STATUS_10MB);
Y
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3012 3013 3014
	return rc;
}

3015 3016
static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
			    u8 devad, u16 reg, u16 val)
Y
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3017
{
3018 3019
	u32 tmp;
	u8 i;
Y
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3020
	int rc = 0;
3021 3022 3023
	if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
			      EMAC_MDIO_STATUS_10MB);
Y
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3024 3025

	/* address */
3026 3027

	tmp = ((phy->addr << 21) | (devad << 16) | reg |
Y
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3028 3029
	       EMAC_MDIO_COMM_COMMAND_ADDRESS |
	       EMAC_MDIO_COMM_START_BUSY);
3030
	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
Y
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3031 3032 3033 3034

	for (i = 0; i < 50; i++) {
		udelay(10);

3035 3036
		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
		if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
Y
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3037 3038 3039 3040
			udelay(5);
			break;
		}
	}
3041 3042
	if (tmp & EMAC_MDIO_COMM_START_BUSY) {
		DP(NETIF_MSG_LINK, "write phy register failed\n");
3043
		netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
Y
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3044 3045 3046 3047
		rc = -EFAULT;

	} else {
		/* data */
3048 3049
		tmp = ((phy->addr << 21) | (devad << 16) | val |
		       EMAC_MDIO_COMM_COMMAND_WRITE_45 |
Y
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3050
		       EMAC_MDIO_COMM_START_BUSY);
3051
		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
Y
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3052 3053 3054 3055

		for (i = 0; i < 50; i++) {
			udelay(10);

3056
			tmp = REG_RD(bp, phy->mdio_ctrl +
Y
Yaniv Rosner 已提交
3057
				     EMAC_REG_EMAC_MDIO_COMM);
3058 3059
			if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
				udelay(5);
Y
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3060 3061 3062
				break;
			}
		}
3063 3064
		if (tmp & EMAC_MDIO_COMM_START_BUSY) {
			DP(NETIF_MSG_LINK, "write phy register failed\n");
3065
			netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
Y
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3066 3067 3068
			rc = -EFAULT;
		}
	}
3069 3070 3071 3072 3073 3074 3075 3076
	/* Work around for E3 A0 */
	if (phy->flags & FLAGS_MDC_MDIO_WA) {
		phy->flags ^= FLAGS_DUMMY_READ;
		if (phy->flags & FLAGS_DUMMY_READ) {
			u16 temp_val;
			bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
		}
	}
3077 3078 3079
	if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
			       EMAC_MDIO_STATUS_10MB);
3080 3081
	return rc;
}
Y
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3082 3083


3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202
/******************************************************************/
/*			BSC access functions from E3	          */
/******************************************************************/
static void bnx2x_bsc_module_sel(struct link_params *params)
{
	int idx;
	u32 board_cfg, sfp_ctrl;
	u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
	struct bnx2x *bp = params->bp;
	u8 port = params->port;
	/* Read I2C output PINs */
	board_cfg = REG_RD(bp, params->shmem_base +
			   offsetof(struct shmem_region,
				    dev_info.shared_hw_config.board));
	i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
	i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
			SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;

	/* Read I2C output value */
	sfp_ctrl = REG_RD(bp, params->shmem_base +
			  offsetof(struct shmem_region,
				 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
	i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
	i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
	DP(NETIF_MSG_LINK, "Setting BSC switch\n");
	for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
		bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
}

static int bnx2x_bsc_read(struct link_params *params,
			  struct bnx2x_phy *phy,
			  u8 sl_devid,
			  u16 sl_addr,
			  u8 lc_addr,
			  u8 xfer_cnt,
			  u32 *data_array)
{
	u32 val, i;
	int rc = 0;
	struct bnx2x *bp = params->bp;

	if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
		DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
		return -EINVAL;
	}

	if (xfer_cnt > 16) {
		DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
					xfer_cnt);
		return -EINVAL;
	}
	bnx2x_bsc_module_sel(params);

	xfer_cnt = 16 - lc_addr;

	/* enable the engine */
	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
	val |= MCPR_IMC_COMMAND_ENABLE;
	REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);

	/* program slave device ID */
	val = (sl_devid << 16) | sl_addr;
	REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);

	/* start xfer with 0 byte to update the address pointer ???*/
	val = (MCPR_IMC_COMMAND_ENABLE) |
	      (MCPR_IMC_COMMAND_WRITE_OP <<
		MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
		(lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
	REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);

	/* poll for completion */
	i = 0;
	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
	while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
		udelay(10);
		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
		if (i++ > 1000) {
			DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
								i);
			rc = -EFAULT;
			break;
		}
	}
	if (rc == -EFAULT)
		return rc;

	/* start xfer with read op */
	val = (MCPR_IMC_COMMAND_ENABLE) |
		(MCPR_IMC_COMMAND_READ_OP <<
		MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
		(lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
		  (xfer_cnt);
	REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);

	/* poll for completion */
	i = 0;
	val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
	while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
		udelay(10);
		val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
		if (i++ > 1000) {
			DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
			rc = -EFAULT;
			break;
		}
	}
	if (rc == -EFAULT)
		return rc;

	for (i = (lc_addr >> 2); i < 4; i++) {
		data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
#ifdef __BIG_ENDIAN
		data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
				((data_array[i] & 0x0000ff00) << 8) |
				((data_array[i] & 0x00ff0000) >> 8) |
				((data_array[i] & 0xff000000) >> 24);
#endif
	}
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3203 3204 3205
	return rc;
}

3206 3207 3208 3209 3210 3211 3212 3213
static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
				     u8 devad, u16 reg, u16 or_val)
{
	u16 val;
	bnx2x_cl45_read(bp, phy, devad, reg, &val);
	bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
}

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Yaniv Rosner 已提交
3214 3215
int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
		   u8 devad, u16 reg, u16 *ret_val)
Y
Yaniv Rosner 已提交
3216 3217
{
	u8 phy_index;
3218
	/*
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3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231
	 * Probe for the phy according to the given phy_addr, and execute
	 * the read request on it
	 */
	for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
		if (params->phy[phy_index].addr == phy_addr) {
			return bnx2x_cl45_read(params->bp,
					       &params->phy[phy_index], devad,
					       reg, ret_val);
		}
	}
	return -EINVAL;
}

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3232 3233
int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
		    u8 devad, u16 reg, u16 val)
Y
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3234 3235
{
	u8 phy_index;
3236
	/*
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3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248
	 * Probe for the phy according to the given phy_addr, and execute
	 * the write request on it
	 */
	for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
		if (params->phy[phy_index].addr == phy_addr) {
			return bnx2x_cl45_write(params->bp,
						&params->phy[phy_index], devad,
						reg, val);
		}
	}
	return -EINVAL;
}
3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301
static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
				  struct link_params *params)
{
	u8 lane = 0;
	struct bnx2x *bp = params->bp;
	u32 path_swap, path_swap_ovr;
	u8 path, port;

	path = BP_PATH(bp);
	port = params->port;

	if (bnx2x_is_4_port_mode(bp)) {
		u32 port_swap, port_swap_ovr;

		/*figure out path swap value */
		path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
		if (path_swap_ovr & 0x1)
			path_swap = (path_swap_ovr & 0x2);
		else
			path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);

		if (path_swap)
			path = path ^ 1;

		/*figure out port swap value */
		port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
		if (port_swap_ovr & 0x1)
			port_swap = (port_swap_ovr & 0x2);
		else
			port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);

		if (port_swap)
			port = port ^ 1;

		lane = (port<<1) + path;
	} else { /* two port mode - no port swap */

		/*figure out path swap value */
		path_swap_ovr =
			REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
		if (path_swap_ovr & 0x1) {
			path_swap = (path_swap_ovr & 0x2);
		} else {
			path_swap =
				REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
		}
		if (path_swap)
			path = path ^ 1;

		lane = path << 1 ;
	}
	return lane;
}
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3302

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3303 3304
static void bnx2x_set_aer_mmd(struct link_params *params,
			      struct bnx2x_phy *phy)
Y
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3305 3306
{
	u32 ser_lane;
D
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	u16 offset, aer_val;
	struct bnx2x *bp = params->bp;
Y
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3309 3310 3311 3312
	ser_lane = ((params->lane_config &
		     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
		     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);

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	offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
		(phy->addr + ser_lane) : 0;

3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327
	if (USES_WARPCORE(bp)) {
		aer_val = bnx2x_get_warpcore_lane(phy, params);
		/*
		 * In Dual-lane mode, two lanes are joined together,
		 * so in order to configure them, the AER broadcast method is
		 * used here.
		 * 0x200 is the broadcast address for lanes 0,1
		 * 0x201 is the broadcast address for lanes 2,3
		 */
		if (phy->flags & FLAGS_WC_DUAL_MODE)
			aer_val = (aer_val >> 1) | 0x200;
	} else if (CHIP_IS_E2(bp))
3328
		aer_val = 0x3800 + offset - 1;
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	else
		aer_val = 0x3800 + offset;
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3331
	DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
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3332
	CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
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			  MDIO_AER_BLOCK_AER_REG, aer_val);
Y
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3334

Y
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3335 3336
}

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3337 3338 3339
/******************************************************************/
/*			Internal phy section			  */
/******************************************************************/
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3340

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3341 3342 3343
static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
{
	u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
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	/* Set Clause 22 */
	REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
	REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
	udelay(500);
	REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
	udelay(500);
	 /* Set Clause 45 */
	REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
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}

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static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
Y
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3356
{
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3357
	u32 val;
Y
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3358

Y
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3359
	DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
Y
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3360

Y
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3361
	val = SERDES_RESET_BITS << (port*16);
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3363 3364 3365 3366
	/* reset and unreset the SerDes/XGXS */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
	udelay(500);
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
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3367

Y
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3368
	bnx2x_set_serdes_access(bp, port);
Y
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3369

Y
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3370 3371
	REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
	       DEFAULT_PHY_DEV_ADDR);
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}

static void bnx2x_xgxs_deassert(struct link_params *params)
{
	struct bnx2x *bp = params->bp;
	u8 port;
	u32 val;
	DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
	port = params->port;

	val = XGXS_RESET_BITS << (port*16);

	/* reset and unreset the SerDes/XGXS */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
	udelay(500);
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);

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3389
	REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
Y
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3390
	REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
Y
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3391
	       params->phy[INT_PHY].def_md_devad);
Y
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3392 3393
}

3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454
static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
				     struct link_params *params, u16 *ieee_fc)
{
	struct bnx2x *bp = params->bp;
	*ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
	/**
	 * resolve pause mode and advertisement Please refer to Table
	 * 28B-3 of the 802.3ab-1999 spec
	 */

	switch (phy->req_flow_ctrl) {
	case BNX2X_FLOW_CTRL_AUTO:
		if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
			*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
		else
			*ieee_fc |=
			MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
		break;

	case BNX2X_FLOW_CTRL_TX:
		*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
		break;

	case BNX2X_FLOW_CTRL_RX:
	case BNX2X_FLOW_CTRL_BOTH:
		*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
		break;

	case BNX2X_FLOW_CTRL_NONE:
	default:
		*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
		break;
	}
	DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
}

static void set_phy_vars(struct link_params *params,
			 struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	u8 actual_phy_idx, phy_index, link_cfg_idx;
	u8 phy_config_swapped = params->multi_phy_config &
			PORT_HW_CFG_PHY_SWAPPED_ENABLED;
	for (phy_index = INT_PHY; phy_index < params->num_phys;
	      phy_index++) {
		link_cfg_idx = LINK_CONFIG_IDX(phy_index);
		actual_phy_idx = phy_index;
		if (phy_config_swapped) {
			if (phy_index == EXT_PHY1)
				actual_phy_idx = EXT_PHY2;
			else if (phy_index == EXT_PHY2)
				actual_phy_idx = EXT_PHY1;
		}
		params->phy[actual_phy_idx].req_flow_ctrl =
			params->req_flow_ctrl[link_cfg_idx];

		params->phy[actual_phy_idx].req_line_speed =
			params->req_line_speed[link_cfg_idx];

		params->phy[actual_phy_idx].speed_cap_mask =
			params->speed_cap_mask[link_cfg_idx];
Y
Yaniv Rosner 已提交
3455

3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543
		params->phy[actual_phy_idx].req_duplex =
			params->req_duplex[link_cfg_idx];

		if (params->req_line_speed[link_cfg_idx] ==
		    SPEED_AUTO_NEG)
			vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;

		DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
			   " speed_cap_mask %x\n",
			   params->phy[actual_phy_idx].req_flow_ctrl,
			   params->phy[actual_phy_idx].req_line_speed,
			   params->phy[actual_phy_idx].speed_cap_mask);
	}
}

static void bnx2x_ext_phy_set_pause(struct link_params *params,
				    struct bnx2x_phy *phy,
				    struct link_vars *vars)
{
	u16 val;
	struct bnx2x *bp = params->bp;
	/* read modify write pause advertizing */
	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);

	val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;

	/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
	bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
	if ((vars->ieee_fc &
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
		val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
	}
	if ((vars->ieee_fc &
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
		val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
	}
	DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
}

static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
{						/*  LD	    LP	 */
	switch (pause_result) {			/* ASYM P ASYM P */
	case 0xb:				/*   1  0   1  1 */
		vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
		break;

	case 0xe:				/*   1  1   1  0 */
		vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
		break;

	case 0x5:				/*   0  1   0  1 */
	case 0x7:				/*   0  1   1  1 */
	case 0xd:				/*   1  1   0  1 */
	case 0xf:				/*   1  1   1  1 */
		vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
		break;

	default:
		break;
	}
	if (pause_result & (1<<0))
		vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
	if (pause_result & (1<<1))
		vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
}

static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
				   struct link_params *params,
				   struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	u16 ld_pause;		/* local */
	u16 lp_pause;		/* link partner */
	u16 pause_result;
	u8 ret = 0;
	/* read twice */

	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;

	if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
		vars->flow_ctrl = phy->req_flow_ctrl;
	else if (phy->req_line_speed != SPEED_AUTO_NEG)
		vars->flow_ctrl = params->req_fc_auto_adv;
	else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
		ret = 1;
3544
		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
Y
Yaniv Rosner 已提交
3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556
			bnx2x_cl22_read(bp, phy,
					0x4, &ld_pause);
			bnx2x_cl22_read(bp, phy,
					0x5, &lp_pause);
		} else {
			bnx2x_cl45_read(bp, phy,
					MDIO_AN_DEVAD,
					MDIO_AN_REG_ADV_PAUSE, &ld_pause);
			bnx2x_cl45_read(bp, phy,
					MDIO_AN_DEVAD,
					MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
		}
3557 3558 3559 3560 3561 3562 3563 3564 3565 3566
		pause_result = (ld_pause &
				MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
		pause_result |= (lp_pause &
				 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
		DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
		   pause_result);
		bnx2x_pause_resolve(vars, pause_result);
	}
	return ret;
}
3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577
/******************************************************************/
/*			Warpcore section			  */
/******************************************************************/
/* The init_internal_warpcore should mirror the xgxs,
 * i.e. reset the lane (if needed), set aer for the
 * init configuration, and set/clear SGMII flag. Internal
 * phy init is done purely in phy_init stage.
 */
static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
					struct link_params *params,
					struct link_vars *vars) {
Y
Yaniv Rosner 已提交
3578
	u16 val16 = 0, lane, bam37 = 0;
3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
	/* Check adding advertisement for 1G KX */
	if (((vars->line_speed == SPEED_AUTO_NEG) &&
	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
	    (vars->line_speed == SPEED_1000)) {
		u16 sd_digital;
		val16 |= (1<<5);

		/* Enable CL37 1G Parallel Detect */
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
				 (sd_digital | 0x1));

		DP(NETIF_MSG_LINK, "Advertize 1G\n");
	}
	if (((vars->line_speed == SPEED_AUTO_NEG) &&
	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
	    (vars->line_speed ==  SPEED_10000)) {
		/* Check adding advertisement for 10G KR */
		val16 |= (1<<7);
		/* Enable 10G Parallel Detect */
		bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
				MDIO_WC_REG_PAR_DET_10G_CTRL, 1);

		DP(NETIF_MSG_LINK, "Advertize 10G\n");
	}

	/* Set Transmit PMD settings */
	lane = bnx2x_get_warpcore_lane(phy, params);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
		      MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
		     ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
		      (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
		      (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
			 0x03f0);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
			 0x03f0);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
			 0x383f);

	/* Advertised speeds */
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
			 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);

Y
Yaniv Rosner 已提交
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	/* Advertised and set FEC (Forward Error Correction) */
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
			 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
			 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
			  MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));

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	/* Enable CL37 BAM */
	if (REG_RD(bp, params->shmem_base +
		   offsetof(struct shmem_region, dev_info.
			    port_hw_config[params->port].default_cfg)) &
	    PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
		DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
	}

3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964
	/* Advertise pause */
	bnx2x_ext_phy_set_pause(params, phy, vars);

	/* Enable Autoneg */
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);

	/* Over 1G - AN local device user page 1 */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_DIGITAL3_UP1, 0x1f);

	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_DIGITAL5_MISC7, &val16);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
}

static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
				      struct link_params *params,
				      struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	u16 val;

	/* Disable Autoneg */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);

	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
			 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);

	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
			 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);

	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_DIGITAL3_UP1, 0x1);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DIGITAL5_MISC7, 0xa);

	/* Disable CL36 PCS Tx */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);

	/* Double Wide Single Data Rate @ pll rate */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);

	/* Leave cl72 training enable, needed for KR */
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
		MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
		0x2);

	/* Leave CL72 enabled */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
			 &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
			 val | 0x3800);

	/* Set speed via PMA/PMD register */
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);

	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
			 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);

	/*Enable encoded forced speed */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);

	/* Turn TX scramble payload only the 64/66 scrambler */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_TX66_CONTROL, 0x9);

	/* Turn RX scramble payload only the 64/66 scrambler */
	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
				 MDIO_WC_REG_RX66_CONTROL, 0xF9);

	/* set and clear loopback to cause a reset to 64/66 decoder */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);

}

static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
				       struct link_params *params,
				       u8 is_xfi)
{
	struct bnx2x *bp = params->bp;
	u16 misc1_val, tap_val, tx_driver_val, lane, val;
	/* Hold rxSeqStart */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));

	/* Hold tx_fifo_reset */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));

	/* Disable CL73 AN */
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);

	/* Disable 100FX Enable and Auto-Detect */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_FX100_CTRL1, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));

	/* Disable 100FX Idle detect */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_FX100_CTRL3, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));

	/* Set Block address to Remote PHY & Clear forced_speed[5] */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_DIGITAL4_MISC3, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));

	/* Turn off auto-detect & fiber mode */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
			 (val & 0xFFEE));

	/* Set filter_force_link, disable_false_link and parallel_detect */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
			 ((val | 0x0006) & 0xFFFE));

	/* Set XFI / SFI */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);

	misc1_val &= ~(0x1f);

	if (is_xfi) {
		misc1_val |= 0x5;
		tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
			   (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
			   (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
		tx_driver_val =
		      ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
		       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
		       (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));

	} else {
		misc1_val |= 0x9;
		tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
			   (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
			   (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
		tx_driver_val =
		      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
		       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
		       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
	}
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);

	/* Set Transmit PMD settings */
	lane = bnx2x_get_warpcore_lane(phy, params);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_TX_FIR_TAP,
			 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
			 tx_driver_val);

	/* Enable fiber mode, enable and invert sig_det */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);

	/* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_DIGITAL4_MISC3, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);

	/* 10G XFI Full Duplex */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);

	/* Release tx_fifo_reset */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);

	/* Release rxSeqStart */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
}

static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
				       struct bnx2x_phy *phy)
{
	DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
}

static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
					 struct bnx2x_phy *phy,
					 u16 lane)
{
	/* Rx0 anaRxControl1G */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);

	/* Rx2 anaRxControl1G */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_SCW0, 0xE070);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_SCW1, 0xC0D0);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_SCW2, 0xA0B0);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_SCW3, 0x8090);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);

	/* Serdes Digital Misc1 */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);

	/* Serdes Digital4 Misc3 */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);

	/* Set Transmit PMD settings */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_TX_FIR_TAP,
			((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
			 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
			 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
			 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
		      MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
		     ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
		      (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
		      (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
}

static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
					   struct link_params *params,
					   u8 fiber_mode)
{
	struct bnx2x *bp = params->bp;
	u16 val16, digctrl_kx1, digctrl_kx2;
	u8 lane;

	lane = bnx2x_get_warpcore_lane(phy, params);

	/* Clear XFI clock comp in non-10G single lane mode. */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_RX66_CONTROL, &val16);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));

	if (phy->req_line_speed == SPEED_AUTO_NEG) {
		/* SGMII Autoneg */
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
				 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
				 val16 | 0x1000);
		DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
	} else {
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
		val16 &= 0xcfbf;
		switch (phy->req_line_speed) {
		case SPEED_10:
			break;
		case SPEED_100:
			val16 |= 0x2000;
			break;
		case SPEED_1000:
			val16 |= 0x0040;
			break;
		default:
3965 3966
			DP(NETIF_MSG_LINK,
			   "Speed not supported: 0x%x\n", phy->req_line_speed);
3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097
			return;
		}

		if (phy->req_duplex == DUPLEX_FULL)
			val16 |= 0x0100;

		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);

		DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
			       phy->req_line_speed);
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
		DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
	}

	/* SGMII Slave mode and disable signal detect */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
	if (fiber_mode)
		digctrl_kx1 = 1;
	else
		digctrl_kx1 &= 0xff4a;

	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
			digctrl_kx1);

	/* Turn off parallel detect */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
			(digctrl_kx2 & ~(1<<2)));

	/* Re-enable parallel detect */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
			(digctrl_kx2 | (1<<2)));

	/* Enable autodet */
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
			(digctrl_kx1 | 0x10));
}

static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
				      struct bnx2x_phy *phy,
				      u8 reset)
{
	u16 val;
	/* Take lane out of reset after configuration is finished */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_DIGITAL5_MISC6, &val);
	if (reset)
		val |= 0xC000;
	else
		val &= 0x3FFF;
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DIGITAL5_MISC6, val);
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DIGITAL5_MISC6, &val);
}


	/* Clear SFI/XFI link settings registers */
static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
				      struct link_params *params,
				      u16 lane)
{
	struct bnx2x *bp = params->bp;
	u16 val16;

	/* Set XFI clock comp as default. */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_RX66_CONTROL, &val16);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));

	bnx2x_warpcore_reset_lane(bp, phy, 1);
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_FX100_CTRL1, 0x014a);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_FX100_CTRL3, 0x0800);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
	lane = bnx2x_get_warpcore_lane(phy, params);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_TX_FIR_TAP, 0x0000);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
	bnx2x_warpcore_reset_lane(bp, phy, 0);
}

static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
						u32 chip_id,
						u32 shmem_base, u8 port,
						u8 *gpio_num, u8 *gpio_port)
{
	u32 cfg_pin;
	*gpio_num = 0;
	*gpio_port = 0;
	if (CHIP_IS_E3(bp)) {
		cfg_pin = (REG_RD(bp, shmem_base +
				offsetof(struct shmem_region,
				dev_info.port_hw_config[port].e3_sfp_ctrl)) &
				PORT_HW_CFG_E3_MOD_ABS_MASK) >>
				PORT_HW_CFG_E3_MOD_ABS_SHIFT;

		/*
		 * Should not happen. This function called upon interrupt
		 * triggered by GPIO ( since EPIO can only generate interrupts
		 * to MCP).
		 * So if this function was called and none of the GPIOs was set,
		 * it means the shit hit the fan.
		 */
		if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
		    (cfg_pin > PIN_CFG_GPIO3_P1)) {
4098 4099 4100
			DP(NETIF_MSG_LINK,
			   "ERROR: Invalid cfg pin %x for module detect indication\n",
			   cfg_pin);
4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227
			return -EINVAL;
		}

		*gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
		*gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
	} else {
		*gpio_num = MISC_REGISTERS_GPIO_3;
		*gpio_port = port;
	}
	DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
	return 0;
}

static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
				       struct link_params *params)
{
	struct bnx2x *bp = params->bp;
	u8 gpio_num, gpio_port;
	u32 gpio_val;
	if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
				      params->shmem_base, params->port,
				      &gpio_num, &gpio_port) != 0)
		return 0;
	gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);

	/* Call the handling function in case module is detected */
	if (gpio_val == 0)
		return 1;
	else
		return 0;
}

static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
				       struct link_params *params,
				       struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	u32 serdes_net_if;
	u8 fiber_mode;
	u16 lane = bnx2x_get_warpcore_lane(phy, params);
	serdes_net_if = (REG_RD(bp, params->shmem_base +
			 offsetof(struct shmem_region, dev_info.
				  port_hw_config[params->port].default_cfg)) &
			 PORT_HW_CFG_NET_SERDES_IF_MASK);
	DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
			   "serdes_net_if = 0x%x\n",
		       vars->line_speed, serdes_net_if);
	bnx2x_set_aer_mmd(params, phy);

	vars->phy_flags |= PHY_XGXS_FLAG;
	if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
	    (phy->req_line_speed &&
	     ((phy->req_line_speed == SPEED_100) ||
	      (phy->req_line_speed == SPEED_10)))) {
		vars->phy_flags |= PHY_SGMII_FLAG;
		DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
		bnx2x_warpcore_clear_regs(phy, params, lane);
		bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
	} else {
		switch (serdes_net_if) {
		case PORT_HW_CFG_NET_SERDES_IF_KR:
			/* Enable KR Auto Neg */
			if (params->loopback_mode == LOOPBACK_NONE)
				bnx2x_warpcore_enable_AN_KR(phy, params, vars);
			else {
				DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
				bnx2x_warpcore_set_10G_KR(phy, params, vars);
			}
			break;

		case PORT_HW_CFG_NET_SERDES_IF_XFI:
			bnx2x_warpcore_clear_regs(phy, params, lane);
			if (vars->line_speed == SPEED_10000) {
				DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
				bnx2x_warpcore_set_10G_XFI(phy, params, 1);
			} else {
				if (SINGLE_MEDIA_DIRECT(params)) {
					DP(NETIF_MSG_LINK, "1G Fiber\n");
					fiber_mode = 1;
				} else {
					DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
					fiber_mode = 0;
				}
				bnx2x_warpcore_set_sgmii_speed(phy,
								params,
								fiber_mode);
			}

			break;

		case PORT_HW_CFG_NET_SERDES_IF_SFI:

			bnx2x_warpcore_clear_regs(phy, params, lane);
			if (vars->line_speed == SPEED_10000) {
				DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
				bnx2x_warpcore_set_10G_XFI(phy, params, 0);
			} else if (vars->line_speed == SPEED_1000) {
				DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
				bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
			}
			/* Issue Module detection */
			if (bnx2x_is_sfp_module_plugged(phy, params))
				bnx2x_sfp_module_detection(phy, params);
			break;

		case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
			if (vars->line_speed != SPEED_20000) {
				DP(NETIF_MSG_LINK, "Speed not supported yet\n");
				return;
			}
			DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
			bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
			/* Issue Module detection */

			bnx2x_sfp_module_detection(phy, params);
			break;

		case PORT_HW_CFG_NET_SERDES_IF_KR2:
			if (vars->line_speed != SPEED_20000) {
				DP(NETIF_MSG_LINK, "Speed not supported yet\n");
				return;
			}
			DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
			bnx2x_warpcore_set_20G_KR2(bp, phy);
			break;

		default:
4228 4229 4230
			DP(NETIF_MSG_LINK,
			   "Unsupported Serdes Net Interface 0x%x\n",
			   serdes_net_if);
4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357
			return;
		}
	}

	/* Take lane out of reset after configuration is finished */
	bnx2x_warpcore_reset_lane(bp, phy, 0);
	DP(NETIF_MSG_LINK, "Exit config init\n");
}

static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
					 struct bnx2x_phy *phy,
					 u8 tx_en)
{
	struct bnx2x *bp = params->bp;
	u32 cfg_pin;
	u8 port = params->port;

	cfg_pin = REG_RD(bp, params->shmem_base +
				offsetof(struct shmem_region,
				dev_info.port_hw_config[port].e3_sfp_ctrl)) &
				PORT_HW_CFG_TX_LASER_MASK;
	/* Set the !tx_en since this pin is DISABLE_TX_LASER */
	DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
	/* For 20G, the expected pin to be used is 3 pins after the current */

	bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
		bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
}

static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
				      struct link_params *params)
{
	struct bnx2x *bp = params->bp;
	u16 val16;
	bnx2x_sfp_e3_set_transmitter(params, phy, 0);
	bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
	bnx2x_set_aer_mmd(params, phy);
	/* Global register */
	bnx2x_warpcore_reset_lane(bp, phy, 1);

	/* Clear loopback settings (if any) */
	/* 10G & 20G */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
			 0xBFFF);

	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);

	/* Update those 1-copy registers */
	CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
			  MDIO_AER_BLOCK_AER_REG, 0);
		/* Enable 1G MDIO (1-copy) */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
			&val16);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
			 val16 & ~0x10);

	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
			 val16 & 0xff00);

}

static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
					struct link_params *params)
{
	struct bnx2x *bp = params->bp;
	u16 val16;
	u32 lane;
	DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
		       params->loopback_mode, phy->req_line_speed);

	if (phy->req_line_speed < SPEED_10000) {
		/* 10/100/1000 */

		/* Update those 1-copy registers */
		CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
				  MDIO_AER_BLOCK_AER_REG, 0);
		/* Enable 1G MDIO (1-copy) */
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
				&val16);
		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
				val16 | 0x10);
		/* Set 1G loopback based on lane (1-copy) */
		lane = bnx2x_get_warpcore_lane(phy, params);
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_XGXSBLK1_LANECTRL2,
				val16 | (1<<lane));

		/* Switch back to 4-copy registers */
		bnx2x_set_aer_mmd(params, phy);
		/* Global loopback, not recommended. */
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
				0x4000);
	} else {
		/* 10G & 20G */
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
				 0x4000);

		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
	}
}


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void bnx2x_link_status_update(struct link_params *params,
Y
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			      struct link_vars *vars)
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4360 4361
{
	struct bnx2x *bp = params->bp;
4362
	u8 link_10g_plus;
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	u8 port = params->port;
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	u32 sync_offset, media_types;
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	/* Update PHY configuration */
	set_phy_vars(params, vars);

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	vars->link_status = REG_RD(bp, params->shmem_base +
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				   offsetof(struct shmem_region,
					    port_mb[port].link_status));
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4371 4372

	vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
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	vars->phy_flags = PHY_XGXS_FLAG;
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	if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
		vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;

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	if (vars->link_up) {
		DP(NETIF_MSG_LINK, "phy link up\n");

		vars->phy_link_up = 1;
		vars->duplex = DUPLEX_FULL;
		switch (vars->link_status &
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4383
			LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
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4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415
			case LINK_10THD:
				vars->duplex = DUPLEX_HALF;
				/* fall thru */
			case LINK_10TFD:
				vars->line_speed = SPEED_10;
				break;

			case LINK_100TXHD:
				vars->duplex = DUPLEX_HALF;
				/* fall thru */
			case LINK_100T4:
			case LINK_100TXFD:
				vars->line_speed = SPEED_100;
				break;

			case LINK_1000THD:
				vars->duplex = DUPLEX_HALF;
				/* fall thru */
			case LINK_1000TFD:
				vars->line_speed = SPEED_1000;
				break;

			case LINK_2500THD:
				vars->duplex = DUPLEX_HALF;
				/* fall thru */
			case LINK_2500TFD:
				vars->line_speed = SPEED_2500;
				break;

			case LINK_10GTFD:
				vars->line_speed = SPEED_10000;
				break;
4416 4417 4418
			case LINK_20GTFD:
				vars->line_speed = SPEED_20000;
				break;
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4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438
			default:
				break;
		}
		vars->flow_ctrl = 0;
		if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
			vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;

		if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
			vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;

		if (!vars->flow_ctrl)
			vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;

		if (vars->line_speed &&
		    ((vars->line_speed == SPEED_10) ||
		     (vars->line_speed == SPEED_100))) {
			vars->phy_flags |= PHY_SGMII_FLAG;
		} else {
			vars->phy_flags &= ~PHY_SGMII_FLAG;
		}
4439 4440 4441 4442
		if (vars->line_speed &&
		    USES_WARPCORE(bp) &&
		    (vars->line_speed == SPEED_1000))
			vars->phy_flags |= PHY_SGMII_FLAG;
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		/* anything 10 and over uses the bmac */
4444 4445 4446 4447 4448 4449
		link_10g_plus = (vars->line_speed >= SPEED_10000);

		if (link_10g_plus) {
			if (USES_WARPCORE(bp))
				vars->mac_type = MAC_TYPE_XMAC;
			else
4450
				vars->mac_type = MAC_TYPE_BMAC;
4451 4452 4453
		} else {
			if (USES_WARPCORE(bp))
				vars->mac_type = MAC_TYPE_UMAC;
4454 4455
			else
				vars->mac_type = MAC_TYPE_EMAC;
4456
		}
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4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467
	} else { /* link down */
		DP(NETIF_MSG_LINK, "phy link down\n");

		vars->phy_link_up = 0;

		vars->line_speed = 0;
		vars->duplex = DUPLEX_FULL;
		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;

		/* indicate no mac active */
		vars->mac_type = MAC_TYPE_NONE;
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		if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
			vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
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4470 4471
	}

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4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488
	/* Sync media type */
	sync_offset = params->shmem_base +
			offsetof(struct shmem_region,
				 dev_info.port_hw_config[port].media_type);
	media_types = REG_RD(bp, sync_offset);

	params->phy[INT_PHY].media_type =
		(media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
		PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
	params->phy[EXT_PHY1].media_type =
		(media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
		PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
	params->phy[EXT_PHY2].media_type =
		(media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
		PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
	DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);

4489 4490 4491 4492 4493 4494 4495
	/* Sync AEU offset */
	sync_offset = params->shmem_base +
			offsetof(struct shmem_region,
				 dev_info.port_hw_config[port].aeu_int_mask);

	vars->aeu_int_mask = REG_RD(bp, sync_offset);

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	/* Sync PFC status */
	if (vars->link_status & LINK_STATUS_PFC_ENABLED)
		params->feature_config_flags |=
					FEATURE_CONFIG_PFC_ENABLED;
	else
		params->feature_config_flags &=
					~FEATURE_CONFIG_PFC_ENABLED;

4504 4505
	DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
		 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
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	DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
		 vars->line_speed, vars->duplex, vars->flow_ctrl);
}


static void bnx2x_set_master_ln(struct link_params *params,
				struct bnx2x_phy *phy)
{
	struct bnx2x *bp = params->bp;
	u16 new_master_ln, ser_lane;
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	ser_lane = ((params->lane_config &
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		     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
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		    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
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4519 4520

	/* set the master_ln for AN */
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	CL22_RD_OVER_CL45(bp, phy,
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			  MDIO_REG_BANK_XGXS_BLOCK2,
			  MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
			  &new_master_ln);
Y
Yaniv Rosner 已提交
4525

Y
Yaniv Rosner 已提交
4526
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4527 4528 4529
			  MDIO_REG_BANK_XGXS_BLOCK2 ,
			  MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
			  (new_master_ln | ser_lane));
Y
Yaniv Rosner 已提交
4530 4531
}

Y
Yaniv Rosner 已提交
4532 4533 4534
static int bnx2x_reset_unicore(struct link_params *params,
			       struct bnx2x_phy *phy,
			       u8 set_serdes)
Y
Yaniv Rosner 已提交
4535 4536 4537 4538
{
	struct bnx2x *bp = params->bp;
	u16 mii_control;
	u16 i;
Y
Yaniv Rosner 已提交
4539
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4540 4541
			  MDIO_REG_BANK_COMBO_IEEE0,
			  MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
Y
Yaniv Rosner 已提交
4542 4543

	/* reset the unicore */
Y
Yaniv Rosner 已提交
4544
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4545 4546 4547 4548
			  MDIO_REG_BANK_COMBO_IEEE0,
			  MDIO_COMBO_IEEE0_MII_CONTROL,
			  (mii_control |
			   MDIO_COMBO_IEEO_MII_CONTROL_RESET));
Y
Yaniv Rosner 已提交
4549 4550 4551 4552 4553 4554 4555 4556
	if (set_serdes)
		bnx2x_set_serdes_access(bp, params->port);

	/* wait for the reset to self clear */
	for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
		udelay(5);

		/* the reset erased the previous bank value */
Y
Yaniv Rosner 已提交
4557
		CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4558 4559 4560
				  MDIO_REG_BANK_COMBO_IEEE0,
				  MDIO_COMBO_IEEE0_MII_CONTROL,
				  &mii_control);
Y
Yaniv Rosner 已提交
4561 4562 4563 4564 4565 4566

		if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
			udelay(5);
			return 0;
		}
	}
Y
Yaniv Rosner 已提交
4567

4568 4569 4570
	netdev_err(bp->dev,  "Warning: PHY was not initialized,"
			      " Port %d\n",
			 params->port);
Y
Yaniv Rosner 已提交
4571 4572 4573 4574 4575
	DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
	return -EINVAL;

}

Y
Yaniv Rosner 已提交
4576 4577
static void bnx2x_set_swap_lanes(struct link_params *params,
				 struct bnx2x_phy *phy)
Y
Yaniv Rosner 已提交
4578 4579
{
	struct bnx2x *bp = params->bp;
4580 4581 4582 4583
	/*
	 *  Each two bits represents a lane number:
	 *  No swap is 0123 => 0x1b no need to enable the swap
	 */
Y
Yaniv Rosner 已提交
4584 4585 4586
	u16 ser_lane, rx_lane_swap, tx_lane_swap;

	ser_lane = ((params->lane_config &
Y
Yaniv Rosner 已提交
4587 4588
		     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
		    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
Y
Yaniv Rosner 已提交
4589
	rx_lane_swap = ((params->lane_config &
Y
Yaniv Rosner 已提交
4590 4591
			 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
			PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
Y
Yaniv Rosner 已提交
4592
	tx_lane_swap = ((params->lane_config &
Y
Yaniv Rosner 已提交
4593 4594
			 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
			PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
Y
Yaniv Rosner 已提交
4595 4596

	if (rx_lane_swap != 0x1b) {
Y
Yaniv Rosner 已提交
4597
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4598 4599 4600 4601 4602
				  MDIO_REG_BANK_XGXS_BLOCK2,
				  MDIO_XGXS_BLOCK2_RX_LN_SWAP,
				  (rx_lane_swap |
				   MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
				   MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
Y
Yaniv Rosner 已提交
4603
	} else {
Y
Yaniv Rosner 已提交
4604
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4605 4606
				  MDIO_REG_BANK_XGXS_BLOCK2,
				  MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
Y
Yaniv Rosner 已提交
4607 4608 4609
	}

	if (tx_lane_swap != 0x1b) {
Y
Yaniv Rosner 已提交
4610
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4611 4612 4613 4614
				  MDIO_REG_BANK_XGXS_BLOCK2,
				  MDIO_XGXS_BLOCK2_TX_LN_SWAP,
				  (tx_lane_swap |
				   MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
Y
Yaniv Rosner 已提交
4615
	} else {
Y
Yaniv Rosner 已提交
4616
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4617 4618
				  MDIO_REG_BANK_XGXS_BLOCK2,
				  MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
Y
Yaniv Rosner 已提交
4619 4620 4621
	}
}

Y
Yaniv Rosner 已提交
4622 4623
static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
					 struct link_params *params)
Y
Yaniv Rosner 已提交
4624 4625 4626
{
	struct bnx2x *bp = params->bp;
	u16 control2;
Y
Yaniv Rosner 已提交
4627
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4628 4629 4630
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
			  &control2);
4631
	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
Y
Yaniv Rosner 已提交
4632 4633 4634
		control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
	else
		control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4635 4636
	DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
		phy->speed_cap_mask, control2);
Y
Yaniv Rosner 已提交
4637
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4638 4639 4640
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
			  control2);
Y
Yaniv Rosner 已提交
4641

Y
Yaniv Rosner 已提交
4642
	if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4643
	     (phy->speed_cap_mask &
Y
Yaniv Rosner 已提交
4644
		    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
Y
Yaniv Rosner 已提交
4645 4646
		DP(NETIF_MSG_LINK, "XGXS\n");

Y
Yaniv Rosner 已提交
4647
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4648 4649 4650
				 MDIO_REG_BANK_10G_PARALLEL_DETECT,
				 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
				 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
Y
Yaniv Rosner 已提交
4651

Y
Yaniv Rosner 已提交
4652
		CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4653 4654 4655
				  MDIO_REG_BANK_10G_PARALLEL_DETECT,
				  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
				  &control2);
Y
Yaniv Rosner 已提交
4656 4657 4658 4659 4660


		control2 |=
		    MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;

Y
Yaniv Rosner 已提交
4661
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4662 4663 4664
				  MDIO_REG_BANK_10G_PARALLEL_DETECT,
				  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
				  control2);
Y
Yaniv Rosner 已提交
4665 4666

		/* Disable parallel detection of HiG */
Y
Yaniv Rosner 已提交
4667
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4668 4669 4670 4671
				  MDIO_REG_BANK_XGXS_BLOCK2,
				  MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
				  MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
				  MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
Y
Yaniv Rosner 已提交
4672 4673 4674
	}
}

Y
Yaniv Rosner 已提交
4675 4676
static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
			      struct link_params *params,
Y
Yaniv Rosner 已提交
4677 4678
			      struct link_vars *vars,
			      u8 enable_cl73)
Y
Yaniv Rosner 已提交
4679 4680 4681 4682 4683
{
	struct bnx2x *bp = params->bp;
	u16 reg_val;

	/* CL37 Autoneg */
Y
Yaniv Rosner 已提交
4684
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4685 4686
			  MDIO_REG_BANK_COMBO_IEEE0,
			  MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
Y
Yaniv Rosner 已提交
4687 4688

	/* CL37 Autoneg Enabled */
Y
Yaniv Rosner 已提交
4689
	if (vars->line_speed == SPEED_AUTO_NEG)
Y
Yaniv Rosner 已提交
4690 4691 4692 4693 4694
		reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
	else /* CL37 Autoneg Disabled */
		reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
			     MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);

Y
Yaniv Rosner 已提交
4695
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4696 4697
			  MDIO_REG_BANK_COMBO_IEEE0,
			  MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
Y
Yaniv Rosner 已提交
4698 4699 4700

	/* Enable/Disable Autodetection */

Y
Yaniv Rosner 已提交
4701
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4702 4703
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4704 4705 4706
	reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
		    MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
	reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
Y
Yaniv Rosner 已提交
4707
	if (vars->line_speed == SPEED_AUTO_NEG)
Y
Yaniv Rosner 已提交
4708 4709 4710 4711
		reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
	else
		reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;

Y
Yaniv Rosner 已提交
4712
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4713 4714
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
Y
Yaniv Rosner 已提交
4715 4716

	/* Enable TetonII and BAM autoneg */
Y
Yaniv Rosner 已提交
4717
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4718 4719
			  MDIO_REG_BANK_BAM_NEXT_PAGE,
			  MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
Y
Yaniv Rosner 已提交
4720
			  &reg_val);
Y
Yaniv Rosner 已提交
4721
	if (vars->line_speed == SPEED_AUTO_NEG) {
Y
Yaniv Rosner 已提交
4722 4723 4724 4725 4726 4727 4728 4729
		/* Enable BAM aneg Mode and TetonII aneg Mode */
		reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
			    MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
	} else {
		/* TetonII and BAM Autoneg Disabled */
		reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
			     MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
	}
Y
Yaniv Rosner 已提交
4730
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4731 4732 4733
			  MDIO_REG_BANK_BAM_NEXT_PAGE,
			  MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
			  reg_val);
Y
Yaniv Rosner 已提交
4734

4735 4736
	if (enable_cl73) {
		/* Enable Cl73 FSM status bits */
Y
Yaniv Rosner 已提交
4737
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4738 4739 4740
				  MDIO_REG_BANK_CL73_USERB0,
				  MDIO_CL73_USERB0_CL73_UCTRL,
				  0xe);
4741 4742

		/* Enable BAM Station Manager*/
Y
Yaniv Rosner 已提交
4743
		CL22_WR_OVER_CL45(bp, phy,
4744 4745 4746 4747 4748 4749
			MDIO_REG_BANK_CL73_USERB0,
			MDIO_CL73_USERB0_CL73_BAM_CTRL1,
			MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
			MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
			MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);

Y
Yaniv Rosner 已提交
4750
		/* Advertise CL73 link speeds */
Y
Yaniv Rosner 已提交
4751
		CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4752 4753 4754
				  MDIO_REG_BANK_CL73_IEEEB1,
				  MDIO_CL73_IEEEB1_AN_ADV2,
				  &reg_val);
4755
		if (phy->speed_cap_mask &
Y
Yaniv Rosner 已提交
4756 4757
		    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
			reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4758
		if (phy->speed_cap_mask &
Y
Yaniv Rosner 已提交
4759 4760
		    PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
			reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4761

Y
Yaniv Rosner 已提交
4762
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4763 4764 4765
				  MDIO_REG_BANK_CL73_IEEEB1,
				  MDIO_CL73_IEEEB1_AN_ADV2,
				  reg_val);
4766 4767 4768 4769 4770 4771

		/* CL73 Autoneg Enabled */
		reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;

	} else /* CL73 Autoneg Disabled */
		reg_val = 0;
Y
Yaniv Rosner 已提交
4772

Y
Yaniv Rosner 已提交
4773
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4774 4775
			  MDIO_REG_BANK_CL73_IEEEB0,
			  MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
Y
Yaniv Rosner 已提交
4776 4777 4778
}

/* program SerDes, forced speed */
Y
Yaniv Rosner 已提交
4779 4780
static void bnx2x_program_serdes(struct bnx2x_phy *phy,
				 struct link_params *params,
Y
Yaniv Rosner 已提交
4781
				 struct link_vars *vars)
Y
Yaniv Rosner 已提交
4782 4783 4784 4785
{
	struct bnx2x *bp = params->bp;
	u16 reg_val;

4786
	/* program duplex, disable autoneg and sgmii*/
Y
Yaniv Rosner 已提交
4787
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4788 4789
			  MDIO_REG_BANK_COMBO_IEEE0,
			  MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
Y
Yaniv Rosner 已提交
4790
	reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4791 4792
		     MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
		     MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4793
	if (phy->req_duplex == DUPLEX_FULL)
Y
Yaniv Rosner 已提交
4794
		reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
Y
Yaniv Rosner 已提交
4795
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4796 4797
			  MDIO_REG_BANK_COMBO_IEEE0,
			  MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
Y
Yaniv Rosner 已提交
4798

4799 4800 4801 4802
	/*
	 * program speed
	 *  - needed only if the speed is greater than 1G (2.5G or 10G)
	 */
Y
Yaniv Rosner 已提交
4803
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4804 4805
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_MISC1, &reg_val);
Y
Yaniv Rosner 已提交
4806 4807 4808 4809 4810 4811 4812 4813 4814 4815
	/* clearing the speed value before setting the right speed */
	DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);

	reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
		     MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);

	if (!((vars->line_speed == SPEED_1000) ||
	      (vars->line_speed == SPEED_100) ||
	      (vars->line_speed == SPEED_10))) {

Y
Yaniv Rosner 已提交
4816 4817
		reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
			    MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
Y
Yaniv Rosner 已提交
4818
		if (vars->line_speed == SPEED_10000)
Y
Yaniv Rosner 已提交
4819 4820
			reg_val |=
				MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
Y
Yaniv Rosner 已提交
4821 4822
	}

Y
Yaniv Rosner 已提交
4823
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4824 4825
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_MISC1, reg_val);
Y
Yaniv Rosner 已提交
4826

Y
Yaniv Rosner 已提交
4827 4828
}

4829 4830
static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
					      struct link_params *params)
Y
Yaniv Rosner 已提交
4831 4832 4833 4834 4835 4836 4837
{
	struct bnx2x *bp = params->bp;
	u16 val = 0;

	/* configure the 48 bits for BAM AN */

	/* set extended capabilities */
4838
	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
Y
Yaniv Rosner 已提交
4839
		val |= MDIO_OVER_1G_UP1_2_5G;
4840
	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
Y
Yaniv Rosner 已提交
4841
		val |= MDIO_OVER_1G_UP1_10G;
Y
Yaniv Rosner 已提交
4842
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4843 4844
			  MDIO_REG_BANK_OVER_1G,
			  MDIO_OVER_1G_UP1, val);
Y
Yaniv Rosner 已提交
4845

Y
Yaniv Rosner 已提交
4846
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4847 4848
			  MDIO_REG_BANK_OVER_1G,
			  MDIO_OVER_1G_UP3, 0x400);
Y
Yaniv Rosner 已提交
4849 4850
}

4851 4852 4853
static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
					      struct link_params *params,
					      u16 ieee_fc)
Y
Yaniv Rosner 已提交
4854 4855
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
4856
	u16 val;
Y
Yaniv Rosner 已提交
4857
	/* for AN, we are always publishing full duplex */
Y
Yaniv Rosner 已提交
4858

Y
Yaniv Rosner 已提交
4859
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4860 4861
			  MDIO_REG_BANK_COMBO_IEEE0,
			  MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
Y
Yaniv Rosner 已提交
4862
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4863 4864
			  MDIO_REG_BANK_CL73_IEEEB1,
			  MDIO_CL73_IEEEB1_AN_ADV1, &val);
Y
Yaniv Rosner 已提交
4865 4866
	val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
	val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
Y
Yaniv Rosner 已提交
4867
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4868 4869
			  MDIO_REG_BANK_CL73_IEEEB1,
			  MDIO_CL73_IEEEB1_AN_ADV1, val);
Y
Yaniv Rosner 已提交
4870 4871
}

Y
Yaniv Rosner 已提交
4872 4873 4874
static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
				  struct link_params *params,
				  u8 enable_cl73)
Y
Yaniv Rosner 已提交
4875 4876
{
	struct bnx2x *bp = params->bp;
E
Eilon Greenstein 已提交
4877
	u16 mii_control;
4878

Y
Yaniv Rosner 已提交
4879
	DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
E
Eilon Greenstein 已提交
4880
	/* Enable and restart BAM/CL37 aneg */
Y
Yaniv Rosner 已提交
4881

4882
	if (enable_cl73) {
Y
Yaniv Rosner 已提交
4883
		CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4884 4885 4886
				  MDIO_REG_BANK_CL73_IEEEB0,
				  MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
				  &mii_control);
4887

Y
Yaniv Rosner 已提交
4888
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4889 4890 4891 4892 4893
				  MDIO_REG_BANK_CL73_IEEEB0,
				  MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
				  (mii_control |
				  MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
				  MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4894 4895
	} else {

Y
Yaniv Rosner 已提交
4896
		CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4897 4898 4899
				  MDIO_REG_BANK_COMBO_IEEE0,
				  MDIO_COMBO_IEEE0_MII_CONTROL,
				  &mii_control);
4900 4901 4902
		DP(NETIF_MSG_LINK,
			 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
			 mii_control);
Y
Yaniv Rosner 已提交
4903
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4904 4905 4906 4907 4908
				  MDIO_REG_BANK_COMBO_IEEE0,
				  MDIO_COMBO_IEEE0_MII_CONTROL,
				  (mii_control |
				   MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
				   MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4909
	}
Y
Yaniv Rosner 已提交
4910 4911
}

Y
Yaniv Rosner 已提交
4912 4913
static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
					   struct link_params *params,
Y
Yaniv Rosner 已提交
4914
					   struct link_vars *vars)
Y
Yaniv Rosner 已提交
4915 4916 4917 4918 4919 4920
{
	struct bnx2x *bp = params->bp;
	u16 control1;

	/* in SGMII mode, the unicore is always slave */

Y
Yaniv Rosner 已提交
4921
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4922 4923 4924
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
			  &control1);
Y
Yaniv Rosner 已提交
4925 4926 4927 4928 4929
	control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
	/* set sgmii mode (and not fiber) */
	control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
		      MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
		      MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
Y
Yaniv Rosner 已提交
4930
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4931 4932 4933
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
			  control1);
Y
Yaniv Rosner 已提交
4934 4935

	/* if forced speed */
Y
Yaniv Rosner 已提交
4936
	if (!(vars->line_speed == SPEED_AUTO_NEG)) {
Y
Yaniv Rosner 已提交
4937 4938 4939
		/* set speed, disable autoneg */
		u16 mii_control;

Y
Yaniv Rosner 已提交
4940
		CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4941 4942 4943
				  MDIO_REG_BANK_COMBO_IEEE0,
				  MDIO_COMBO_IEEE0_MII_CONTROL,
				  &mii_control);
Y
Yaniv Rosner 已提交
4944 4945 4946 4947
		mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
				 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
				 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);

Y
Yaniv Rosner 已提交
4948
		switch (vars->line_speed) {
Y
Yaniv Rosner 已提交
4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961
		case SPEED_100:
			mii_control |=
				MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
			break;
		case SPEED_1000:
			mii_control |=
				MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
			break;
		case SPEED_10:
			/* there is nothing to set for 10M */
			break;
		default:
			/* invalid speed for SGMII */
Y
Yaniv Rosner 已提交
4962 4963
			DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
				  vars->line_speed);
Y
Yaniv Rosner 已提交
4964 4965 4966 4967
			break;
		}

		/* setting the full duplex */
4968
		if (phy->req_duplex == DUPLEX_FULL)
Y
Yaniv Rosner 已提交
4969 4970
			mii_control |=
				MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
Y
Yaniv Rosner 已提交
4971
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4972 4973 4974
				  MDIO_REG_BANK_COMBO_IEEE0,
				  MDIO_COMBO_IEEE0_MII_CONTROL,
				  mii_control);
Y
Yaniv Rosner 已提交
4975 4976 4977

	} else { /* AN mode */
		/* enable and restart AN */
Y
Yaniv Rosner 已提交
4978
		bnx2x_restart_autoneg(phy, params, 0);
Y
Yaniv Rosner 已提交
4979 4980 4981 4982 4983 4984 4985 4986
	}
}


/*
 * link management
 */

Y
Yaniv Rosner 已提交
4987 4988
static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
					     struct link_params *params)
4989 4990 4991
{
	struct bnx2x *bp = params->bp;
	u16 pd_10g, status2_1000x;
4992 4993
	if (phy->req_line_speed != SPEED_AUTO_NEG)
		return 0;
Y
Yaniv Rosner 已提交
4994
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4995 4996 4997
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
			  &status2_1000x);
Y
Yaniv Rosner 已提交
4998
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
4999 5000 5001
			  MDIO_REG_BANK_SERDES_DIGITAL,
			  MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
			  &status2_1000x);
5002 5003 5004 5005 5006 5007
	if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
		DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
			 params->port);
		return 1;
	}

Y
Yaniv Rosner 已提交
5008
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5009 5010 5011
			  MDIO_REG_BANK_10G_PARALLEL_DETECT,
			  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
			  &pd_10g);
5012 5013 5014 5015 5016 5017 5018 5019

	if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
		DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
			 params->port);
		return 1;
	}
	return 0;
}
Y
Yaniv Rosner 已提交
5020

Y
Yaniv Rosner 已提交
5021 5022 5023 5024
static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
				    struct link_params *params,
				    struct link_vars *vars,
				    u32 gp_status)
Y
Yaniv Rosner 已提交
5025 5026
{
	struct bnx2x *bp = params->bp;
5027 5028
	u16 ld_pause;   /* local driver */
	u16 lp_pause;   /* link partner */
Y
Yaniv Rosner 已提交
5029 5030
	u16 pause_result;

5031
	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
Y
Yaniv Rosner 已提交
5032 5033

	/* resolve from gp_status in case of AN complete and not sgmii */
5034 5035 5036 5037 5038 5039
	if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
		vars->flow_ctrl = phy->req_flow_ctrl;
	else if (phy->req_line_speed != SPEED_AUTO_NEG)
		vars->flow_ctrl = params->req_fc_auto_adv;
	else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
		 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
Y
Yaniv Rosner 已提交
5040
		if (bnx2x_direct_parallel_detect_used(phy, params)) {
5041 5042 5043
			vars->flow_ctrl = params->req_fc_auto_adv;
			return;
		}
Y
Yaniv Rosner 已提交
5044 5045 5046 5047 5048 5049
		if ((gp_status &
		    (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
		     MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
		    (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
		     MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {

Y
Yaniv Rosner 已提交
5050
			CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5051 5052 5053
					  MDIO_REG_BANK_CL73_IEEEB1,
					  MDIO_CL73_IEEEB1_AN_ADV1,
					  &ld_pause);
Y
Yaniv Rosner 已提交
5054
			CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5055 5056 5057
					  MDIO_REG_BANK_CL73_IEEEB1,
					  MDIO_CL73_IEEEB1_AN_LP_ADV1,
					  &lp_pause);
Y
Yaniv Rosner 已提交
5058 5059 5060 5061 5062 5063 5064 5065 5066
			pause_result = (ld_pause &
					MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
					>> 8;
			pause_result |= (lp_pause &
					MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
					>> 10;
			DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
				 pause_result);
		} else {
Y
Yaniv Rosner 已提交
5067
			CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5068 5069 5070
					  MDIO_REG_BANK_COMBO_IEEE0,
					  MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
					  &ld_pause);
Y
Yaniv Rosner 已提交
5071
			CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5072 5073 5074
				MDIO_REG_BANK_COMBO_IEEE0,
				MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
				&lp_pause);
Y
Yaniv Rosner 已提交
5075
			pause_result = (ld_pause &
Y
Yaniv Rosner 已提交
5076
				MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
Y
Yaniv Rosner 已提交
5077
			pause_result |= (lp_pause &
Y
Yaniv Rosner 已提交
5078
				MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
Y
Yaniv Rosner 已提交
5079 5080 5081
			DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
				 pause_result);
		}
Y
Yaniv Rosner 已提交
5082 5083 5084 5085 5086
		bnx2x_pause_resolve(vars, pause_result);
	}
	DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
}

Y
Yaniv Rosner 已提交
5087 5088
static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
					 struct link_params *params)
5089 5090
{
	struct bnx2x *bp = params->bp;
5091
	u16 rx_status, ustat_val, cl37_fsm_received;
5092 5093
	DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
	/* Step 1: Make sure signal is detected */
Y
Yaniv Rosner 已提交
5094
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5095 5096 5097
			  MDIO_REG_BANK_RX0,
			  MDIO_RX0_RX_STATUS,
			  &rx_status);
5098 5099 5100 5101
	if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
	    (MDIO_RX0_RX_STATUS_SIGDET)) {
		DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
			     "rx_status(0x80b0) = 0x%x\n", rx_status);
Y
Yaniv Rosner 已提交
5102
		CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5103 5104 5105
				  MDIO_REG_BANK_CL73_IEEEB0,
				  MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
				  MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5106 5107 5108
		return;
	}
	/* Step 2: Check CL73 state machine */
Y
Yaniv Rosner 已提交
5109
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5110 5111 5112
			  MDIO_REG_BANK_CL73_USERB0,
			  MDIO_CL73_USERB0_CL73_USTAT1,
			  &ustat_val);
5113 5114 5115 5116 5117 5118 5119 5120 5121
	if ((ustat_val &
	     (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
	      MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
	    (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
	      MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
		DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
			     "ustat_val(0x8371) = 0x%x\n", ustat_val);
		return;
	}
5122 5123 5124 5125
	/*
	 * Step 3: Check CL37 Message Pages received to indicate LP
	 * supports only CL37
	 */
Y
Yaniv Rosner 已提交
5126
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5127 5128
			  MDIO_REG_BANK_REMOTE_PHY,
			  MDIO_REMOTE_PHY_MISC_RX_STATUS,
5129 5130
			  &cl37_fsm_received);
	if ((cl37_fsm_received &
5131 5132 5133 5134 5135 5136
	     (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
	     MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
	    (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
	      MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
		DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
			     "misc_rx_status(0x8330) = 0x%x\n",
5137
			 cl37_fsm_received);
5138 5139
		return;
	}
5140 5141 5142 5143 5144 5145 5146
	/*
	 * The combined cl37/cl73 fsm state information indicating that
	 * we are connected to a device which does not support cl73, but
	 * does support cl37 BAM. In this case we disable cl73 and
	 * restart cl37 auto-neg
	 */

5147
	/* Disable CL73 */
Y
Yaniv Rosner 已提交
5148
	CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5149 5150 5151
			  MDIO_REG_BANK_CL73_IEEEB0,
			  MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
			  0);
5152
	/* Restart CL37 autoneg */
Y
Yaniv Rosner 已提交
5153
	bnx2x_restart_autoneg(phy, params, 0);
5154 5155
	DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
}
5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169

static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
				  struct link_params *params,
				  struct link_vars *vars,
				  u32 gp_status)
{
	if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
		vars->link_status |=
			LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;

	if (bnx2x_direct_parallel_detect_used(phy, params))
		vars->link_status |=
			LINK_STATUS_PARALLEL_DETECTION_USED;
}
5170 5171 5172 5173 5174 5175
static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
				     struct link_params *params,
				      struct link_vars *vars,
				      u16 is_link_up,
				      u16 speed_mask,
				      u16 is_duplex)
Y
Yaniv Rosner 已提交
5176 5177
{
	struct bnx2x *bp = params->bp;
5178 5179
	if (phy->req_line_speed == SPEED_AUTO_NEG)
		vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5180 5181
	if (is_link_up) {
		DP(NETIF_MSG_LINK, "phy link up\n");
Y
Yaniv Rosner 已提交
5182 5183 5184 5185

		vars->phy_link_up = 1;
		vars->link_status |= LINK_STATUS_LINK_UP;

5186
		switch (speed_mask) {
Y
Yaniv Rosner 已提交
5187
		case GP_STATUS_10M:
5188
			vars->line_speed = SPEED_10;
Y
Yaniv Rosner 已提交
5189 5190 5191 5192 5193 5194 5195
			if (vars->duplex == DUPLEX_FULL)
				vars->link_status |= LINK_10TFD;
			else
				vars->link_status |= LINK_10THD;
			break;

		case GP_STATUS_100M:
5196
			vars->line_speed = SPEED_100;
Y
Yaniv Rosner 已提交
5197 5198 5199 5200 5201 5202 5203 5204
			if (vars->duplex == DUPLEX_FULL)
				vars->link_status |= LINK_100TXFD;
			else
				vars->link_status |= LINK_100TXHD;
			break;

		case GP_STATUS_1G:
		case GP_STATUS_1G_KX:
5205
			vars->line_speed = SPEED_1000;
Y
Yaniv Rosner 已提交
5206 5207 5208 5209 5210 5211 5212
			if (vars->duplex == DUPLEX_FULL)
				vars->link_status |= LINK_1000TFD;
			else
				vars->link_status |= LINK_1000THD;
			break;

		case GP_STATUS_2_5G:
5213
			vars->line_speed = SPEED_2500;
Y
Yaniv Rosner 已提交
5214 5215 5216 5217 5218 5219 5220 5221 5222 5223
			if (vars->duplex == DUPLEX_FULL)
				vars->link_status |= LINK_2500TFD;
			else
				vars->link_status |= LINK_2500THD;
			break;

		case GP_STATUS_5G:
		case GP_STATUS_6G:
			DP(NETIF_MSG_LINK,
				 "link speed unsupported  gp_status 0x%x\n",
5224
				  speed_mask);
Y
Yaniv Rosner 已提交
5225
			return -EINVAL;
5226

Y
Yaniv Rosner 已提交
5227 5228 5229
		case GP_STATUS_10G_KX4:
		case GP_STATUS_10G_HIG:
		case GP_STATUS_10G_CX4:
5230 5231 5232 5233
		case GP_STATUS_10G_KR:
		case GP_STATUS_10G_SFI:
		case GP_STATUS_10G_XFI:
			vars->line_speed = SPEED_10000;
Y
Yaniv Rosner 已提交
5234 5235
			vars->link_status |= LINK_10GTFD;
			break;
5236 5237 5238 5239
		case GP_STATUS_20G_DXGXS:
			vars->line_speed = SPEED_20000;
			vars->link_status |= LINK_20GTFD;
			break;
Y
Yaniv Rosner 已提交
5240 5241 5242
		default:
			DP(NETIF_MSG_LINK,
				  "link speed unsupported gp_status 0x%x\n",
5243
				  speed_mask);
5244
			return -EINVAL;
Y
Yaniv Rosner 已提交
5245 5246 5247 5248 5249
		}
	} else { /* link_down */
		DP(NETIF_MSG_LINK, "phy link down\n");

		vars->phy_link_up = 0;
5250

Y
Yaniv Rosner 已提交
5251
		vars->duplex = DUPLEX_FULL;
5252
		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
Y
Yaniv Rosner 已提交
5253
		vars->mac_type = MAC_TYPE_NONE;
5254 5255 5256 5257 5258 5259 5260 5261 5262 5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275 5276 5277 5278 5279 5280 5281 5282 5283 5284 5285
	}
	DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
		    vars->phy_link_up, vars->line_speed);
	return 0;
}

static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
				      struct link_params *params,
				      struct link_vars *vars)
{

	struct bnx2x *bp = params->bp;

	u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
	int rc = 0;

	/* Read gp_status */
	CL22_RD_OVER_CL45(bp, phy,
			  MDIO_REG_BANK_GP_STATUS,
			  MDIO_GP_STATUS_TOP_AN_STATUS1,
			  &gp_status);
	if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
		duplex = DUPLEX_FULL;
	if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
		link_up = 1;
	speed_mask = gp_status & GP_STATUS_SPEED_MASK;
	DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
		       gp_status, link_up, speed_mask);
	rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
					 duplex);
	if (rc == -EINVAL)
		return rc;
5286

5287 5288 5289 5290 5291 5292 5293 5294
	if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
		if (SINGLE_MEDIA_DIRECT(params)) {
			bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
			if (phy->req_line_speed == SPEED_AUTO_NEG)
				bnx2x_xgxs_an_resolve(phy, params, vars,
						      gp_status);
		}
	} else { /* link_down */
5295 5296
		if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
		    SINGLE_MEDIA_DIRECT(params)) {
5297
			/* Check signal is detected */
5298
			bnx2x_check_fallback_to_cl37(phy, params);
5299
		}
Y
Yaniv Rosner 已提交
5300 5301
	}

Y
Yaniv Rosner 已提交
5302 5303
	DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
		   vars->duplex, vars->flow_ctrl, vars->link_status);
Y
Yaniv Rosner 已提交
5304 5305 5306
	return rc;
}

5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360 5361 5362 5363 5364 5365 5366 5367 5368 5369 5370 5371 5372 5373 5374 5375 5376 5377 5378 5379 5380 5381
static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
				     struct link_params *params,
				     struct link_vars *vars)
{

	struct bnx2x *bp = params->bp;

	u8 lane;
	u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
	int rc = 0;
	lane = bnx2x_get_warpcore_lane(phy, params);
	/* Read gp_status */
	if (phy->req_line_speed > SPEED_10000) {
		u16 temp_link_up;
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				1, &temp_link_up);
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				1, &link_up);
		DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
			       temp_link_up, link_up);
		link_up &= (1<<2);
		if (link_up)
			bnx2x_ext_phy_resolve_fc(phy, params, vars);
	} else {
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
		DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
		/* Check for either KR or generic link up. */
		gp_status1 = ((gp_status1 >> 8) & 0xf) |
			((gp_status1 >> 12) & 0xf);
		link_up = gp_status1 & (1 << lane);
		if (link_up && SINGLE_MEDIA_DIRECT(params)) {
			u16 pd, gp_status4;
			if (phy->req_line_speed == SPEED_AUTO_NEG) {
				/* Check Autoneg complete */
				bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
						MDIO_WC_REG_GP2_STATUS_GP_2_4,
						&gp_status4);
				if (gp_status4 & ((1<<12)<<lane))
					vars->link_status |=
					LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;

				/* Check parallel detect used */
				bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
						MDIO_WC_REG_PAR_DET_10G_STATUS,
						&pd);
				if (pd & (1<<15))
					vars->link_status |=
					LINK_STATUS_PARALLEL_DETECTION_USED;
			}
			bnx2x_ext_phy_resolve_fc(phy, params, vars);
		}
	}

	if (lane < 2) {
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
	} else {
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
	}
	DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);

	if ((lane & 1) == 0)
		gp_speed <<= 8;
	gp_speed &= 0x3f00;


	rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
					 duplex);

	DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
		   vars->duplex, vars->flow_ctrl, vars->link_status);
	return rc;
}
E
Eilon Greenstein 已提交
5382
static void bnx2x_set_gmii_tx_driver(struct link_params *params)
Y
Yaniv Rosner 已提交
5383 5384
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
5385
	struct bnx2x_phy *phy = &params->phy[INT_PHY];
Y
Yaniv Rosner 已提交
5386 5387
	u16 lp_up2;
	u16 tx_driver;
5388
	u16 bank;
Y
Yaniv Rosner 已提交
5389 5390

	/* read precomp */
Y
Yaniv Rosner 已提交
5391
	CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5392 5393
			  MDIO_REG_BANK_OVER_1G,
			  MDIO_OVER_1G_LP_UP2, &lp_up2);
Y
Yaniv Rosner 已提交
5394 5395 5396 5397 5398 5399

	/* bits [10:7] at lp_up2, positioned at [15:12] */
	lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
		   MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
		  MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);

5400 5401 5402 5403 5404
	if (lp_up2 == 0)
		return;

	for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
	      bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
Y
Yaniv Rosner 已提交
5405
		CL22_RD_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5406 5407
				  bank,
				  MDIO_TX0_TX_DRIVER, &tx_driver);
5408 5409 5410 5411 5412 5413

		/* replace tx_driver bits [15:12] */
		if (lp_up2 !=
		    (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
			tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
			tx_driver |= lp_up2;
Y
Yaniv Rosner 已提交
5414
			CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5415 5416
					  bank,
					  MDIO_TX0_TX_DRIVER, tx_driver);
5417
		}
Y
Yaniv Rosner 已提交
5418 5419 5420
	}
}

Y
Yaniv Rosner 已提交
5421 5422
static int bnx2x_emac_program(struct link_params *params,
			      struct link_vars *vars)
Y
Yaniv Rosner 已提交
5423 5424 5425 5426 5427 5428 5429
{
	struct bnx2x *bp = params->bp;
	u8 port = params->port;
	u16 mode = 0;

	DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
	bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
Y
Yaniv Rosner 已提交
5430 5431 5432 5433
		       EMAC_REG_EMAC_MODE,
		       (EMAC_MODE_25G_MODE |
			EMAC_MODE_PORT_MII_10M |
			EMAC_MODE_HALF_DUPLEX));
Y
Yaniv Rosner 已提交
5434
	switch (vars->line_speed) {
Y
Yaniv Rosner 已提交
5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452
	case SPEED_10:
		mode |= EMAC_MODE_PORT_MII_10M;
		break;

	case SPEED_100:
		mode |= EMAC_MODE_PORT_MII;
		break;

	case SPEED_1000:
		mode |= EMAC_MODE_PORT_GMII;
		break;

	case SPEED_2500:
		mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
		break;

	default:
		/* 10G not valid for EMAC */
Y
Yaniv Rosner 已提交
5453 5454
		DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
			   vars->line_speed);
Y
Yaniv Rosner 已提交
5455 5456 5457
		return -EINVAL;
	}

Y
Yaniv Rosner 已提交
5458
	if (vars->duplex == DUPLEX_HALF)
Y
Yaniv Rosner 已提交
5459 5460
		mode |= EMAC_MODE_HALF_DUPLEX;
	bnx2x_bits_en(bp,
Y
Yaniv Rosner 已提交
5461 5462
		      GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
		      mode);
Y
Yaniv Rosner 已提交
5463

5464
	bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
Y
Yaniv Rosner 已提交
5465 5466 5467
	return 0;
}

Y
Yaniv Rosner 已提交
5468 5469
static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
				  struct link_params *params)
Y
Yaniv Rosner 已提交
5470
{
Y
Yaniv Rosner 已提交
5471 5472 5473 5474 5475 5476

	u16 bank, i = 0;
	struct bnx2x *bp = params->bp;

	for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
	      bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
Y
Yaniv Rosner 已提交
5477
			CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5478 5479 5480 5481 5482 5483 5484
					  bank,
					  MDIO_RX0_RX_EQ_BOOST,
					  phy->rx_preemphasis[i]);
	}

	for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
		      bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
Y
Yaniv Rosner 已提交
5485
			CL22_WR_OVER_CL45(bp, phy,
Y
Yaniv Rosner 已提交
5486 5487 5488 5489 5490 5491
					  bank,
					  MDIO_TX0_TX_DRIVER,
					  phy->tx_preemphasis[i]);
	}
}

Y
Yaniv Rosner 已提交
5492 5493 5494
static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
				   struct link_params *params,
				   struct link_vars *vars)
Y
Yaniv Rosner 已提交
5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507
{
	struct bnx2x *bp = params->bp;
	u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
			  (params->loopback_mode == LOOPBACK_XGXS));
	if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
		if (SINGLE_MEDIA_DIRECT(params) &&
		    (params->feature_config_flags &
		     FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
			bnx2x_set_preemphasis(phy, params);

		/* forced speed requested? */
		if (vars->line_speed != SPEED_AUTO_NEG ||
		    (SINGLE_MEDIA_DIRECT(params) &&
Y
Yaniv Rosner 已提交
5508
		     params->loopback_mode == LOOPBACK_EXT)) {
Y
Yaniv Rosner 已提交
5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520
			DP(NETIF_MSG_LINK, "not SGMII, no AN\n");

			/* disable autoneg */
			bnx2x_set_autoneg(phy, params, vars, 0);

			/* program speed and duplex */
			bnx2x_program_serdes(phy, params, vars);

		} else { /* AN_mode */
			DP(NETIF_MSG_LINK, "not SGMII, AN\n");

			/* AN enabled */
5521
			bnx2x_set_brcm_cl37_advertisement(phy, params);
Y
Yaniv Rosner 已提交
5522 5523

			/* program duplex & pause advertisement (for aneg) */
5524 5525
			bnx2x_set_ieee_aneg_advertisement(phy, params,
							  vars->ieee_fc);
Y
Yaniv Rosner 已提交
5526 5527 5528 5529 5530 5531 5532 5533 5534 5535 5536 5537 5538 5539 5540

			/* enable autoneg */
			bnx2x_set_autoneg(phy, params, vars, enable_cl73);

			/* enable and restart AN */
			bnx2x_restart_autoneg(phy, params, enable_cl73);
		}

	} else { /* SGMII mode */
		DP(NETIF_MSG_LINK, "SGMII\n");

		bnx2x_initialize_sgmii_process(phy, params, vars);
	}
}

Y
Yaniv Rosner 已提交
5541 5542 5543
static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
			  struct link_params *params,
			  struct link_vars *vars)
Y
Yaniv Rosner 已提交
5544
{
Y
Yaniv Rosner 已提交
5545
	int rc;
Y
Yaniv Rosner 已提交
5546
	vars->phy_flags |= PHY_XGXS_FLAG;
Y
Yaniv Rosner 已提交
5547 5548 5549 5550 5551 5552 5553
	if ((phy->req_line_speed &&
	     ((phy->req_line_speed == SPEED_100) ||
	      (phy->req_line_speed == SPEED_10))) ||
	    (!phy->req_line_speed &&
	     (phy->speed_cap_mask >=
	      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
	     (phy->speed_cap_mask <
Y
Yaniv Rosner 已提交
5554 5555
	      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
	    (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
Y
Yaniv Rosner 已提交
5556 5557 5558 5559 5560
		vars->phy_flags |= PHY_SGMII_FLAG;
	else
		vars->phy_flags &= ~PHY_SGMII_FLAG;

	bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
Y
Yaniv Rosner 已提交
5561 5562 5563
	bnx2x_set_aer_mmd(params, phy);
	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
		bnx2x_set_master_ln(params, phy);
Y
Yaniv Rosner 已提交
5564 5565 5566 5567 5568 5569

	rc = bnx2x_reset_unicore(params, phy, 0);
	/* reset the SerDes and wait for reset bit return low */
	if (rc != 0)
		return rc;

Y
Yaniv Rosner 已提交
5570
	bnx2x_set_aer_mmd(params, phy);
Y
Yaniv Rosner 已提交
5571
	/* setting the masterLn_def again after the reset */
Y
Yaniv Rosner 已提交
5572 5573 5574 5575
	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
		bnx2x_set_master_ln(params, phy);
		bnx2x_set_swap_lanes(params, phy);
	}
Y
Yaniv Rosner 已提交
5576 5577 5578

	return rc;
}
5579

Y
Yaniv Rosner 已提交
5580
static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5581 5582
				     struct bnx2x_phy *phy,
				     struct link_params *params)
Y
Yaniv Rosner 已提交
5583
{
Y
Yaniv Rosner 已提交
5584
	u16 cnt, ctrl;
L
Lucas De Marchi 已提交
5585
	/* Wait for soft reset to get cleared up to 1 sec */
Y
Yaniv Rosner 已提交
5586
	for (cnt = 0; cnt < 1000; cnt++) {
5587
		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
Y
Yaniv Rosner 已提交
5588 5589 5590 5591 5592 5593
			bnx2x_cl22_read(bp, phy,
				MDIO_PMA_REG_CTRL, &ctrl);
		else
			bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_CTRL, &ctrl);
Y
Yaniv Rosner 已提交
5594 5595 5596 5597
		if (!(ctrl & (1<<15)))
			break;
		msleep(1);
	}
5598 5599 5600 5601 5602

	if (cnt == 1000)
		netdev_err(bp->dev,  "Warning: PHY was not initialized,"
				      " Port %d\n",
			 params->port);
Y
Yaniv Rosner 已提交
5603 5604
	DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
	return cnt;
Y
Yaniv Rosner 已提交
5605 5606
}

Y
Yaniv Rosner 已提交
5607
static void bnx2x_link_int_enable(struct link_params *params)
E
Eilon Greenstein 已提交
5608
{
Y
Yaniv Rosner 已提交
5609 5610 5611
	u8 port = params->port;
	u32 mask;
	struct bnx2x *bp = params->bp;
5612

5613
	/* Setting the status to report on link up for either XGXS or SerDes */
5614 5615 5616 5617 5618
	if (CHIP_IS_E3(bp)) {
		mask = NIG_MASK_XGXS0_LINK_STATUS;
		if (!(SINGLE_MEDIA_DIRECT(params)))
			mask |= NIG_MASK_MI_INT;
	} else if (params->switch_cfg == SWITCH_CFG_10G) {
Y
Yaniv Rosner 已提交
5619 5620 5621 5622 5623 5624 5625 5626 5627 5628 5629 5630 5631 5632 5633 5634 5635 5636 5637 5638 5639 5640 5641 5642 5643 5644 5645 5646 5647 5648 5649 5650 5651 5652
		mask = (NIG_MASK_XGXS0_LINK10G |
			NIG_MASK_XGXS0_LINK_STATUS);
		DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
		if (!(SINGLE_MEDIA_DIRECT(params)) &&
			params->phy[INT_PHY].type !=
				PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
			mask |= NIG_MASK_MI_INT;
			DP(NETIF_MSG_LINK, "enabled external phy int\n");
		}

	} else { /* SerDes */
		mask = NIG_MASK_SERDES0_LINK_STATUS;
		DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
		if (!(SINGLE_MEDIA_DIRECT(params)) &&
			params->phy[INT_PHY].type !=
				PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
			mask |= NIG_MASK_MI_INT;
			DP(NETIF_MSG_LINK, "enabled external phy int\n");
		}
	}
	bnx2x_bits_en(bp,
		      NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
		      mask);

	DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
		 (params->switch_cfg == SWITCH_CFG_10G),
		 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
	DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
		 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
		 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
		 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
	DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
	   REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
	   REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
E
Eilon Greenstein 已提交
5653 5654
}

Y
Yaniv Rosner 已提交
5655 5656
static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
				     u8 exp_mi_int)
E
Eilon Greenstein 已提交
5657
{
Y
Yaniv Rosner 已提交
5658 5659
	u32 latch_status = 0;

5660
	/*
Y
Yaniv Rosner 已提交
5661 5662 5663
	 * Disable the MI INT ( external phy int ) by writing 1 to the
	 * status register. Link down indication is high-active-signal,
	 * so in this case we need to write the status to clear the XOR
Y
Yaniv Rosner 已提交
5664 5665 5666
	 */
	/* Read Latched signals */
	latch_status = REG_RD(bp,
Y
Yaniv Rosner 已提交
5667 5668
				    NIG_REG_LATCH_STATUS_0 + port*8);
	DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
Y
Yaniv Rosner 已提交
5669
	/* Handle only those with latched-signal=up.*/
Y
Yaniv Rosner 已提交
5670 5671 5672 5673 5674 5675 5676 5677 5678 5679 5680
	if (exp_mi_int)
		bnx2x_bits_en(bp,
			      NIG_REG_STATUS_INTERRUPT_PORT0
			      + port*4,
			      NIG_STATUS_EMAC0_MI_INT);
	else
		bnx2x_bits_dis(bp,
			       NIG_REG_STATUS_INTERRUPT_PORT0
			       + port*4,
			       NIG_STATUS_EMAC0_MI_INT);

Y
Yaniv Rosner 已提交
5681
	if (latch_status & 1) {
Y
Yaniv Rosner 已提交
5682

Y
Yaniv Rosner 已提交
5683 5684
		/* For all latched-signal=up : Re-Arm Latch signals */
		REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
Y
Yaniv Rosner 已提交
5685
		       (latch_status & 0xfffe) | (latch_status & 1));
Y
Yaniv Rosner 已提交
5686
	}
Y
Yaniv Rosner 已提交
5687
	/* For all latched-signal=up,Write original_signal to status */
E
Eilon Greenstein 已提交
5688 5689
}

Y
Yaniv Rosner 已提交
5690
static void bnx2x_link_int_ack(struct link_params *params,
5691
			       struct link_vars *vars, u8 is_10g_plus)
5692
{
Y
Yaniv Rosner 已提交
5693
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
5694
	u8 port = params->port;
5695
	u32 mask;
5696 5697 5698 5699
	/*
	 * First reset all status we assume only one line will be
	 * change at a time
	 */
Y
Yaniv Rosner 已提交
5700
	bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
Y
Yaniv Rosner 已提交
5701 5702 5703
		       (NIG_STATUS_XGXS0_LINK10G |
			NIG_STATUS_XGXS0_LINK_STATUS |
			NIG_STATUS_SERDES0_LINK_STATUS));
Y
Yaniv Rosner 已提交
5704
	if (vars->phy_link_up) {
5705 5706 5707 5708 5709 5710 5711 5712 5713 5714 5715 5716
		if (USES_WARPCORE(bp))
			mask = NIG_STATUS_XGXS0_LINK_STATUS;
		else {
			if (is_10g_plus)
				mask = NIG_STATUS_XGXS0_LINK10G;
			else if (params->switch_cfg == SWITCH_CFG_10G) {
				/*
				 * Disable the link interrupt by writing 1 to
				 * the relevant lane in the status register
				 */
				u32 ser_lane =
					((params->lane_config &
Y
Yaniv Rosner 已提交
5717 5718
				    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
				    PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5719 5720 5721 5722
				mask = ((1 << ser_lane) <<
				       NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
			} else
				mask = NIG_STATUS_SERDES0_LINK_STATUS;
Y
Yaniv Rosner 已提交
5723
		}
5724 5725 5726 5727 5728
		DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
			       mask);
		bnx2x_bits_en(bp,
			      NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
			      mask);
Y
Yaniv Rosner 已提交
5729 5730 5731
	}
}

Y
Yaniv Rosner 已提交
5732
static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
Y
Yaniv Rosner 已提交
5733 5734 5735 5736 5737
{
	u8 *str_ptr = str;
	u32 mask = 0xf0000000;
	u8 shift = 8*4;
	u8 digit;
Y
Yaniv Rosner 已提交
5738
	u8 remove_leading_zeros = 1;
Y
Yaniv Rosner 已提交
5739 5740 5741
	if (*len < 10) {
		/* Need more than 10chars for this format */
		*str_ptr = '\0';
Y
Yaniv Rosner 已提交
5742
		(*len)--;
Y
Yaniv Rosner 已提交
5743
		return -EINVAL;
Y
Yaniv Rosner 已提交
5744
	}
Y
Yaniv Rosner 已提交
5745
	while (shift > 0) {
Y
Yaniv Rosner 已提交
5746

Y
Yaniv Rosner 已提交
5747 5748
		shift -= 4;
		digit = ((num & mask) >> shift);
Y
Yaniv Rosner 已提交
5749 5750 5751 5752
		if (digit == 0 && remove_leading_zeros) {
			mask = mask >> 4;
			continue;
		} else if (digit < 0xa)
Y
Yaniv Rosner 已提交
5753 5754 5755
			*str_ptr = digit + '0';
		else
			*str_ptr = digit - 0xa + 'a';
Y
Yaniv Rosner 已提交
5756
		remove_leading_zeros = 0;
Y
Yaniv Rosner 已提交
5757
		str_ptr++;
Y
Yaniv Rosner 已提交
5758
		(*len)--;
Y
Yaniv Rosner 已提交
5759 5760
		mask = mask >> 4;
		if (shift == 4*4) {
Y
Yaniv Rosner 已提交
5761
			*str_ptr = '.';
Y
Yaniv Rosner 已提交
5762
			str_ptr++;
Y
Yaniv Rosner 已提交
5763 5764
			(*len)--;
			remove_leading_zeros = 1;
Y
Yaniv Rosner 已提交
5765 5766
		}
	}
Y
Yaniv Rosner 已提交
5767
	return 0;
Y
Yaniv Rosner 已提交
5768 5769
}

Y
Yaniv Rosner 已提交
5770

Y
Yaniv Rosner 已提交
5771
static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
Y
Yaniv Rosner 已提交
5772
{
Y
Yaniv Rosner 已提交
5773 5774 5775 5776
	str[0] = '\0';
	(*len)--;
	return 0;
}
Y
Yaniv Rosner 已提交
5777

Y
Yaniv Rosner 已提交
5778 5779
int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
				 u8 *version, u16 len)
Y
Yaniv Rosner 已提交
5780 5781 5782
{
	struct bnx2x *bp;
	u32 spirom_ver = 0;
Y
Yaniv Rosner 已提交
5783
	int status = 0;
Y
Yaniv Rosner 已提交
5784
	u8 *ver_p = version;
Y
Yaniv Rosner 已提交
5785
	u16 remain_len = len;
Y
Yaniv Rosner 已提交
5786 5787 5788
	if (version == NULL || params == NULL)
		return -EINVAL;
	bp = params->bp;
Y
Yaniv Rosner 已提交
5789

Y
Yaniv Rosner 已提交
5790 5791 5792
	/* Extract first external phy*/
	version[0] = '\0';
	spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
Y
Yaniv Rosner 已提交
5793

Y
Yaniv Rosner 已提交
5794
	if (params->phy[EXT_PHY1].format_fw_ver) {
Y
Yaniv Rosner 已提交
5795 5796
		status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
							      ver_p,
Y
Yaniv Rosner 已提交
5797 5798 5799 5800 5801
							      &remain_len);
		ver_p += (len - remain_len);
	}
	if ((params->num_phys == MAX_PHYS) &&
	    (params->phy[EXT_PHY2].ver_addr != 0)) {
Y
Yaniv Rosner 已提交
5802
		spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
Y
Yaniv Rosner 已提交
5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814
		if (params->phy[EXT_PHY2].format_fw_ver) {
			*ver_p = '/';
			ver_p++;
			remain_len--;
			status |= params->phy[EXT_PHY2].format_fw_ver(
				spirom_ver,
				ver_p,
				&remain_len);
			ver_p = version + (len - remain_len);
		}
	}
	*ver_p = '\0';
Y
Yaniv Rosner 已提交
5815
	return status;
Y
Yaniv Rosner 已提交
5816
}
Y
Yaniv Rosner 已提交
5817

Y
Yaniv Rosner 已提交
5818 5819
static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
				    struct link_params *params)
E
Eilon Greenstein 已提交
5820
{
Y
Yaniv Rosner 已提交
5821
	u8 port = params->port;
E
Eilon Greenstein 已提交
5822 5823
	struct bnx2x *bp = params->bp;

Y
Yaniv Rosner 已提交
5824
	if (phy->req_line_speed != SPEED_1000) {
5825
		u32 md_devad = 0;
E
Eilon Greenstein 已提交
5826

Y
Yaniv Rosner 已提交
5827
		DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
E
Eilon Greenstein 已提交
5828

5829 5830 5831 5832
		if (!CHIP_IS_E3(bp)) {
			/* change the uni_phy_addr in the nig */
			md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
					       port*0x18));
5833

5834 5835 5836
			REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
			       0x5);
		}
E
Eilon Greenstein 已提交
5837

Y
Yaniv Rosner 已提交
5838
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
5839 5840 5841 5842
				 5,
				 (MDIO_REG_BANK_AER_BLOCK +
				  (MDIO_AER_BLOCK_AER_REG & 0xf)),
				 0x2800);
E
Eilon Greenstein 已提交
5843

Y
Yaniv Rosner 已提交
5844
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
5845 5846 5847 5848
				 5,
				 (MDIO_REG_BANK_CL73_IEEEB0 +
				  (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
				 0x6041);
Y
Yaniv Rosner 已提交
5849 5850
		msleep(200);
		/* set aer mmd back */
Y
Yaniv Rosner 已提交
5851
		bnx2x_set_aer_mmd(params, phy);
E
Eilon Greenstein 已提交
5852

5853 5854 5855 5856 5857
		if (!CHIP_IS_E3(bp)) {
			/* and md_devad */
			REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
			       md_devad);
		}
Y
Yaniv Rosner 已提交
5858 5859 5860 5861 5862 5863 5864 5865 5866 5867 5868 5869 5870
	} else {
		u16 mii_ctrl;
		DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
		bnx2x_cl45_read(bp, phy, 5,
				(MDIO_REG_BANK_COMBO_IEEE0 +
				(MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
				&mii_ctrl);
		bnx2x_cl45_write(bp, phy, 5,
				 (MDIO_REG_BANK_COMBO_IEEE0 +
				 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
				 mii_ctrl |
				 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
	}
E
Eilon Greenstein 已提交
5871 5872
}

Y
Yaniv Rosner 已提交
5873 5874
int bnx2x_set_led(struct link_params *params,
		  struct link_vars *vars, u8 mode, u32 speed)
E
Eilon Greenstein 已提交
5875
{
Y
Yaniv Rosner 已提交
5876 5877
	u8 port = params->port;
	u16 hw_led_mode = params->hw_led_mode;
Y
Yaniv Rosner 已提交
5878 5879
	int rc = 0;
	u8 phy_idx;
Y
Yaniv Rosner 已提交
5880 5881
	u32 tmp;
	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
E
Eilon Greenstein 已提交
5882
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
5883 5884 5885
	DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
	DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
		 speed, hw_led_mode);
5886 5887 5888 5889 5890 5891 5892 5893
	/* In case */
	for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
		if (params->phy[phy_idx].set_link_led) {
			params->phy[phy_idx].set_link_led(
				&params->phy[phy_idx], params, mode);
		}
	}

Y
Yaniv Rosner 已提交
5894
	switch (mode) {
5895
	case LED_MODE_FRONT_PANEL_OFF:
Y
Yaniv Rosner 已提交
5896 5897 5898
	case LED_MODE_OFF:
		REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
		REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
Y
Yaniv Rosner 已提交
5899
		       SHARED_HW_CFG_LED_MAC1);
E
Eilon Greenstein 已提交
5900

Y
Yaniv Rosner 已提交
5901 5902 5903
		tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
		EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
		break;
E
Eilon Greenstein 已提交
5904

Y
Yaniv Rosner 已提交
5905
	case LED_MODE_OPER:
5906
		/*
5907 5908
		 * For all other phys, OPER mode is same as ON, so in case
		 * link is down, do nothing
5909
		 */
5910 5911 5912
		if (!vars->link_up)
			break;
	case LED_MODE_ON:
Y
Yaniv Rosner 已提交
5913 5914 5915 5916
		if (((params->phy[EXT_PHY1].type ==
			  PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
			 (params->phy[EXT_PHY1].type ==
			  PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5917
		    CHIP_IS_E2(bp) && params->num_phys == 2) {
5918 5919 5920
			/*
			 * This is a work-around for E2+8727 Configurations
			 */
5921 5922 5923 5924 5925 5926 5927 5928
			if (mode == LED_MODE_ON ||
				speed == SPEED_10000){
				REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
				REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);

				tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
				EMAC_WR(bp, EMAC_REG_EMAC_LED,
					(tmp | EMAC_LED_OVERRIDE));
Y
Yaniv Rosner 已提交
5929 5930
				/*
				 * return here without enabling traffic
Y
Yaniv Rosner 已提交
5931
				 * LED blink and setting rate in ON mode.
Y
Yaniv Rosner 已提交
5932 5933 5934 5935 5936
				 * In oper mode, enabling LED blink
				 * and setting rate is needed.
				 */
				if (mode == LED_MODE_ON)
					return rc;
5937
			}
Y
Yaniv Rosner 已提交
5938
		} else if (SINGLE_MEDIA_DIRECT(params)) {
5939 5940 5941 5942
			/*
			 * This is a work-around for HW issue found when link
			 * is up in CL73
			 */
Y
Yaniv Rosner 已提交
5943 5944 5945 5946 5947
			if ((!CHIP_IS_E3(bp)) ||
			    (CHIP_IS_E3(bp) &&
			     mode == LED_MODE_ON))
				REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);

Y
Yaniv Rosner 已提交
5948 5949 5950 5951 5952 5953 5954 5955
			if (CHIP_IS_E1x(bp) ||
			    CHIP_IS_E2(bp) ||
			    (mode == LED_MODE_ON))
				REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
			else
				REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
				       hw_led_mode);
		} else
Y
Yaniv Rosner 已提交
5956
			REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
E
Eilon Greenstein 已提交
5957

Y
Yaniv Rosner 已提交
5958
		REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
Y
Yaniv Rosner 已提交
5959
		/* Set blinking rate to ~15.9Hz */
Y
Yaniv Rosner 已提交
5960 5961 5962 5963 5964 5965
		if (CHIP_IS_E3(bp))
			REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
			       LED_BLINK_RATE_VAL_E3);
		else
			REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
			       LED_BLINK_RATE_VAL_E1X_E2);
Y
Yaniv Rosner 已提交
5966
		REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
Y
Yaniv Rosner 已提交
5967
		       port*4, 1);
Y
Yaniv Rosner 已提交
5968
		tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
Y
Yaniv Rosner 已提交
5969
		EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
E
Eilon Greenstein 已提交
5970

Y
Yaniv Rosner 已提交
5971 5972 5973 5974 5975
		if (CHIP_IS_E1(bp) &&
		    ((speed == SPEED_2500) ||
		     (speed == SPEED_1000) ||
		     (speed == SPEED_100) ||
		     (speed == SPEED_10))) {
5976 5977 5978 5979
			/*
			 * On Everest 1 Ax chip versions for speeds less than
			 * 10G LED scheme is different
			 */
Y
Yaniv Rosner 已提交
5980
			REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
Y
Yaniv Rosner 已提交
5981
			       + port*4, 1);
Y
Yaniv Rosner 已提交
5982
			REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
Y
Yaniv Rosner 已提交
5983
			       port*4, 0);
Y
Yaniv Rosner 已提交
5984
			REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
Y
Yaniv Rosner 已提交
5985
			       port*4, 1);
Y
Yaniv Rosner 已提交
5986 5987
		}
		break;
E
Eilon Greenstein 已提交
5988

Y
Yaniv Rosner 已提交
5989 5990 5991 5992 5993
	default:
		rc = -EINVAL;
		DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
			 mode);
		break;
E
Eilon Greenstein 已提交
5994
	}
Y
Yaniv Rosner 已提交
5995
	return rc;
E
Eilon Greenstein 已提交
5996

E
Eilon Greenstein 已提交
5997 5998
}

5999
/*
Y
Yaniv Rosner 已提交
6000 6001 6002
 * This function comes to reflect the actual link state read DIRECTLY from the
 * HW
 */
Y
Yaniv Rosner 已提交
6003 6004
int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
		    u8 is_serdes)
E
Eilon Greenstein 已提交
6005 6006
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
6007
	u16 gp_status = 0, phy_index = 0;
Y
Yaniv Rosner 已提交
6008 6009
	u8 ext_phy_link_up = 0, serdes_phy_type;
	struct link_vars temp_vars;
6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033 6034 6035
	struct bnx2x_phy *int_phy = &params->phy[INT_PHY];

	if (CHIP_IS_E3(bp)) {
		u16 link_up;
		if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
		    > SPEED_10000) {
			/* Check 20G link */
			bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
					1, &link_up);
			bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
					1, &link_up);
			link_up &= (1<<2);
		} else {
			/* Check 10G link and below*/
			u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
			bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
					MDIO_WC_REG_GP2_STATUS_GP_2_1,
					&gp_status);
			gp_status = ((gp_status >> 8) & 0xf) |
				((gp_status >> 12) & 0xf);
			link_up = gp_status & (1 << lane);
		}
		if (!link_up)
			return -ESRCH;
	} else {
		CL22_RD_OVER_CL45(bp, int_phy,
Y
Yaniv Rosner 已提交
6036 6037 6038
			  MDIO_REG_BANK_GP_STATUS,
			  MDIO_GP_STATUS_TOP_AN_STATUS1,
			  &gp_status);
Y
Yaniv Rosner 已提交
6039
	/* link is up only if both local phy and external phy are up */
Y
Yaniv Rosner 已提交
6040 6041
	if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
		return -ESRCH;
6042 6043 6044 6045
	}
	/* In XGXS loopback mode, do not check external PHY */
	if (params->loopback_mode == LOOPBACK_XGXS)
		return 0;
Y
Yaniv Rosner 已提交
6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056

	switch (params->num_phys) {
	case 1:
		/* No external PHY */
		return 0;
	case 2:
		ext_phy_link_up = params->phy[EXT_PHY1].read_status(
			&params->phy[EXT_PHY1],
			params, &temp_vars);
		break;
	case 3: /* Dual Media */
Y
Yaniv Rosner 已提交
6057 6058
		for (phy_index = EXT_PHY1; phy_index < params->num_phys;
		      phy_index++) {
Y
Yaniv Rosner 已提交
6059 6060 6061
			serdes_phy_type = ((params->phy[phy_index].media_type ==
					    ETH_PHY_SFP_FIBER) ||
					   (params->phy[phy_index].media_type ==
Y
Yaniv Rosner 已提交
6062 6063 6064
					    ETH_PHY_XFP_FIBER) ||
					   (params->phy[phy_index].media_type ==
					    ETH_PHY_DA_TWINAX));
Y
Yaniv Rosner 已提交
6065 6066 6067 6068 6069

			if (is_serdes != serdes_phy_type)
				continue;
			if (params->phy[phy_index].read_status) {
				ext_phy_link_up |=
Y
Yaniv Rosner 已提交
6070 6071 6072
					params->phy[phy_index].read_status(
						&params->phy[phy_index],
						params, &temp_vars);
Y
Yaniv Rosner 已提交
6073
			}
Y
Yaniv Rosner 已提交
6074
		}
Y
Yaniv Rosner 已提交
6075
		break;
E
Eilon Greenstein 已提交
6076
	}
Y
Yaniv Rosner 已提交
6077 6078
	if (ext_phy_link_up)
		return 0;
Y
Yaniv Rosner 已提交
6079 6080
	return -ESRCH;
}
E
Eilon Greenstein 已提交
6081

Y
Yaniv Rosner 已提交
6082 6083
static int bnx2x_link_initialize(struct link_params *params,
				 struct link_vars *vars)
Y
Yaniv Rosner 已提交
6084
{
Y
Yaniv Rosner 已提交
6085
	int rc = 0;
Y
Yaniv Rosner 已提交
6086 6087
	u8 phy_index, non_ext_phy;
	struct bnx2x *bp = params->bp;
6088 6089 6090 6091 6092 6093
	/*
	 * In case of external phy existence, the line speed would be the
	 * line speed linked up by the external phy. In case it is direct
	 * only, then the line_speed during initialization will be
	 * equal to the req_line_speed
	 */
Y
Yaniv Rosner 已提交
6094
	vars->line_speed = params->phy[INT_PHY].req_line_speed;
E
Eilon Greenstein 已提交
6095

6096
	/*
Y
Yaniv Rosner 已提交
6097 6098 6099 6100
	 * Initialize the internal phy in case this is a direct board
	 * (no external phys), or this board has external phy which requires
	 * to first.
	 */
6101 6102
	if (!USES_WARPCORE(bp))
		bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
Y
Yaniv Rosner 已提交
6103 6104 6105
	/* init ext phy and enable link state int */
	non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
		       (params->loopback_mode == LOOPBACK_XGXS));
E
Eilon Greenstein 已提交
6106

Y
Yaniv Rosner 已提交
6107 6108 6109 6110
	if (non_ext_phy ||
	    (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
	    (params->loopback_mode == LOOPBACK_EXT_PHY)) {
		struct bnx2x_phy *phy = &params->phy[INT_PHY];
6111 6112 6113
		if (vars->line_speed == SPEED_AUTO_NEG &&
		    (CHIP_IS_E1x(bp) ||
		     CHIP_IS_E2(bp)))
Y
Yaniv Rosner 已提交
6114
			bnx2x_set_parallel_detection(phy, params);
Y
Yaniv Rosner 已提交
6115 6116 6117 6118
			if (params->phy[INT_PHY].config_init)
				params->phy[INT_PHY].config_init(phy,
								 params,
								 vars);
E
Eilon Greenstein 已提交
6119 6120
	}

Y
Yaniv Rosner 已提交
6121
	/* Init external phy*/
Y
Yaniv Rosner 已提交
6122 6123 6124 6125 6126
	if (non_ext_phy) {
		if (params->phy[INT_PHY].supported &
		    SUPPORTED_FIBRE)
			vars->link_status |= LINK_STATUS_SERDES_LINK;
	} else {
Y
Yaniv Rosner 已提交
6127 6128
		for (phy_index = EXT_PHY1; phy_index < params->num_phys;
		      phy_index++) {
6129
			/*
Y
Yaniv Rosner 已提交
6130 6131 6132 6133
			 * No need to initialize second phy in case of first
			 * phy only selection. In case of second phy, we do
			 * need to initialize the first phy, since they are
			 * connected.
6134
			 */
Y
Yaniv Rosner 已提交
6135 6136 6137 6138
			if (params->phy[phy_index].supported &
			    SUPPORTED_FIBRE)
				vars->link_status |= LINK_STATUS_SERDES_LINK;

Y
Yaniv Rosner 已提交
6139 6140 6141
			if (phy_index == EXT_PHY2 &&
			    (bnx2x_phy_selection(params) ==
			     PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6142 6143
				DP(NETIF_MSG_LINK,
				   "Not initializing second phy\n");
Y
Yaniv Rosner 已提交
6144 6145
				continue;
			}
Y
Yaniv Rosner 已提交
6146 6147 6148 6149
			params->phy[phy_index].config_init(
				&params->phy[phy_index],
				params, vars);
		}
Y
Yaniv Rosner 已提交
6150
	}
Y
Yaniv Rosner 已提交
6151 6152 6153 6154 6155 6156 6157
	/* Reset the interrupt indication after phy was initialized */
	bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
		       params->port*4,
		       (NIG_STATUS_XGXS0_LINK10G |
			NIG_STATUS_XGXS0_LINK_STATUS |
			NIG_STATUS_SERDES0_LINK_STATUS |
			NIG_MASK_MI_INT));
Y
Yaniv Rosner 已提交
6158
	bnx2x_update_mng(params, vars->link_status);
Y
Yaniv Rosner 已提交
6159 6160
	return rc;
}
E
Eilon Greenstein 已提交
6161

Y
Yaniv Rosner 已提交
6162 6163 6164 6165
static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
				 struct link_params *params)
{
	/* reset the SerDes/XGXS */
Y
Yaniv Rosner 已提交
6166 6167
	REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
	       (0x1ff << (params->port*16)));
E
Eilon Greenstein 已提交
6168 6169
}

Y
Yaniv Rosner 已提交
6170 6171
static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
					struct link_params *params)
E
Eilon Greenstein 已提交
6172
{
Y
Yaniv Rosner 已提交
6173 6174 6175
	struct bnx2x *bp = params->bp;
	u8 gpio_port;
	/* HW reset */
D
Dmitry Kravkov 已提交
6176 6177 6178 6179
	if (CHIP_IS_E2(bp))
		gpio_port = BP_PATH(bp);
	else
		gpio_port = params->port;
Y
Yaniv Rosner 已提交
6180
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
Y
Yaniv Rosner 已提交
6181 6182
		       MISC_REGISTERS_GPIO_OUTPUT_LOW,
		       gpio_port);
Y
Yaniv Rosner 已提交
6183
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Y
Yaniv Rosner 已提交
6184 6185
		       MISC_REGISTERS_GPIO_OUTPUT_LOW,
		       gpio_port);
Y
Yaniv Rosner 已提交
6186
	DP(NETIF_MSG_LINK, "reset external PHY\n");
E
Eilon Greenstein 已提交
6187
}
E
Eilon Greenstein 已提交
6188

Y
Yaniv Rosner 已提交
6189 6190
static int bnx2x_update_link_down(struct link_params *params,
				  struct link_vars *vars)
E
Eilon Greenstein 已提交
6191 6192
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
6193
	u8 port = params->port;
E
Eilon Greenstein 已提交
6194

Y
Yaniv Rosner 已提交
6195
	DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6196
	bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6197
	vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
Y
Yaniv Rosner 已提交
6198 6199
	/* indicate no mac active */
	vars->mac_type = MAC_TYPE_NONE;
6200

Y
Yaniv Rosner 已提交
6201
	/* update shared memory */
Y
Yaniv Rosner 已提交
6202 6203
	vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
			       LINK_STATUS_LINK_UP |
Y
Yaniv Rosner 已提交
6204
			       LINK_STATUS_PHYSICAL_LINK_FLAG |
Y
Yaniv Rosner 已提交
6205 6206 6207 6208
			       LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
			       LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
			       LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
			       LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
Y
Yaniv Rosner 已提交
6209 6210
	vars->line_speed = 0;
	bnx2x_update_mng(params, vars->link_status);
E
Eilon Greenstein 已提交
6211

Y
Yaniv Rosner 已提交
6212 6213
	/* activate nig drain */
	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
E
Eilon Greenstein 已提交
6214

Y
Yaniv Rosner 已提交
6215
	/* disable emac */
6216 6217
	if (!CHIP_IS_E3(bp))
		REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
Y
Yaniv Rosner 已提交
6218 6219

	msleep(10);
6220 6221 6222 6223 6224 6225
	/* reset BigMac/Xmac */
	if (CHIP_IS_E1x(bp) ||
	    CHIP_IS_E2(bp)) {
		bnx2x_bmac_rx_disable(bp, params->port);
		REG_WR(bp, GRCBASE_MISC +
		       MISC_REGISTERS_RESET_REG_2_CLEAR,
Y
Yaniv Rosner 已提交
6226
	       (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6227 6228 6229 6230
	}
	if (CHIP_IS_E3(bp))
		bnx2x_xmac_disable(params);

E
Eilon Greenstein 已提交
6231 6232
	return 0;
}
Y
Yaniv Rosner 已提交
6233

Y
Yaniv Rosner 已提交
6234 6235 6236
static int bnx2x_update_link_up(struct link_params *params,
				struct link_vars *vars,
				u8 link_10g)
E
Eilon Greenstein 已提交
6237 6238
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
6239
	u8 port = params->port;
Y
Yaniv Rosner 已提交
6240
	int rc = 0;
E
Eilon Greenstein 已提交
6241

Y
Yaniv Rosner 已提交
6242 6243
	vars->link_status |= (LINK_STATUS_LINK_UP |
			      LINK_STATUS_PHYSICAL_LINK_FLAG);
6244
	vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6245

Y
Yaniv Rosner 已提交
6246 6247 6248
	if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
		vars->link_status |=
			LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
E
Eilon Greenstein 已提交
6249

Y
Yaniv Rosner 已提交
6250 6251 6252
	if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
		vars->link_status |=
			LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6253
	if (USES_WARPCORE(bp)) {
6254 6255 6256 6257 6258 6259 6260 6261 6262
		if (link_10g) {
			if (bnx2x_xmac_enable(params, vars, 0) ==
			    -ESRCH) {
				DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
				vars->link_up = 0;
				vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
				vars->link_status &= ~LINK_STATUS_LINK_UP;
			}
		} else
6263
			bnx2x_umac_enable(params, vars, 0);
6264
		bnx2x_set_led(params, vars,
6265 6266 6267 6268 6269
			      LED_MODE_OPER, vars->line_speed);
	}
	if ((CHIP_IS_E1x(bp) ||
	     CHIP_IS_E2(bp))) {
		if (link_10g) {
6270 6271 6272 6273 6274 6275 6276
			if (bnx2x_bmac_enable(params, vars, 0) ==
			    -ESRCH) {
				DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
				vars->link_up = 0;
				vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
				vars->link_status &= ~LINK_STATUS_LINK_UP;
			}
6277

6278 6279 6280 6281 6282 6283 6284 6285 6286 6287 6288 6289 6290
			bnx2x_set_led(params, vars,
				      LED_MODE_OPER, SPEED_10000);
		} else {
			rc = bnx2x_emac_program(params, vars);
			bnx2x_emac_enable(params, vars, 0);

			/* AN complete? */
			if ((vars->link_status &
			     LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
			    && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
			    SINGLE_MEDIA_DIRECT(params))
				bnx2x_set_gmii_tx_driver(params);
		}
Y
Yaniv Rosner 已提交
6291
	}
6292

Y
Yaniv Rosner 已提交
6293
	/* PBF - link up */
6294
	if (CHIP_IS_E1x(bp))
D
Dmitry Kravkov 已提交
6295 6296
		rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
				       vars->line_speed);
E
Eilon Greenstein 已提交
6297

Y
Yaniv Rosner 已提交
6298 6299
	/* disable drain */
	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
E
Eilon Greenstein 已提交
6300

Y
Yaniv Rosner 已提交
6301 6302 6303 6304
	/* update shared memory */
	bnx2x_update_mng(params, vars->link_status);
	msleep(20);
	return rc;
E
Eilon Greenstein 已提交
6305
}
6306
/*
Y
Yaniv Rosner 已提交
6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318
 * The bnx2x_link_update function should be called upon link
 * interrupt.
 * Link is considered up as follows:
 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
 *   to be up
 * - SINGLE_MEDIA - The link between the 577xx and the external
 *   phy (XGXS) need to up as well as the external link of the
 *   phy (PHY_EXT1)
 * - DUAL_MEDIA - The link between the 577xx and the first
 *   external phy needs to be up, and at least one of the 2
 *   external phy link must be up.
 */
Y
Yaniv Rosner 已提交
6319
int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
E
Eilon Greenstein 已提交
6320
{
Y
Yaniv Rosner 已提交
6321 6322 6323
	struct bnx2x *bp = params->bp;
	struct link_vars phy_vars[MAX_PHYS];
	u8 port = params->port;
6324
	u8 link_10g_plus, phy_index;
Y
Yaniv Rosner 已提交
6325 6326
	u8 ext_phy_link_up = 0, cur_link_up;
	int rc = 0;
Y
Yaniv Rosner 已提交
6327 6328 6329
	u8 is_mi_int = 0;
	u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
	u8 active_external_phy = INT_PHY;
6330
	vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
Y
Yaniv Rosner 已提交
6331 6332 6333 6334 6335 6336 6337 6338
	for (phy_index = INT_PHY; phy_index < params->num_phys;
	      phy_index++) {
		phy_vars[phy_index].flow_ctrl = 0;
		phy_vars[phy_index].link_status = 0;
		phy_vars[phy_index].line_speed = 0;
		phy_vars[phy_index].duplex = DUPLEX_FULL;
		phy_vars[phy_index].phy_link_up = 0;
		phy_vars[phy_index].link_up = 0;
6339
		phy_vars[phy_index].fault_detected = 0;
Y
Yaniv Rosner 已提交
6340
	}
E
Eilon Greenstein 已提交
6341

6342 6343 6344
	if (USES_WARPCORE(bp))
		bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);

Y
Yaniv Rosner 已提交
6345 6346 6347
	DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
		 port, (vars->phy_flags & PHY_XGXS_FLAG),
		 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
E
Eilon Greenstein 已提交
6348

Y
Yaniv Rosner 已提交
6349
	is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
Y
Yaniv Rosner 已提交
6350
				port*0x18) > 0);
Y
Yaniv Rosner 已提交
6351 6352 6353
	DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
		 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
		 is_mi_int,
Y
Yaniv Rosner 已提交
6354
		 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
E
Eilon Greenstein 已提交
6355

Y
Yaniv Rosner 已提交
6356 6357 6358
	DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
	  REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
	  REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
E
Eilon Greenstein 已提交
6359

Y
Yaniv Rosner 已提交
6360
	/* disable emac */
6361 6362
	if (!CHIP_IS_E3(bp))
		REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
E
Eilon Greenstein 已提交
6363

6364 6365 6366 6367
	/*
	 * Step 1:
	 * Check external link change only for external phys, and apply
	 * priority selection between them in case the link on both phys
6368
	 * is up. Note that instead of the common vars, a temporary
6369 6370 6371
	 * vars argument is used since each phy may have different link/
	 * speed/duplex result
	 */
Y
Yaniv Rosner 已提交
6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387
	for (phy_index = EXT_PHY1; phy_index < params->num_phys;
	      phy_index++) {
		struct bnx2x_phy *phy = &params->phy[phy_index];
		if (!phy->read_status)
			continue;
		/* Read link status and params of this ext phy */
		cur_link_up = phy->read_status(phy, params,
					       &phy_vars[phy_index]);
		if (cur_link_up) {
			DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
				   phy_index);
		} else {
			DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
				   phy_index);
			continue;
		}
Y
Yaniv Rosner 已提交
6388

Y
Yaniv Rosner 已提交
6389 6390 6391
		if (!ext_phy_link_up) {
			ext_phy_link_up = 1;
			active_external_phy = phy_index;
Y
Yaniv Rosner 已提交
6392 6393 6394 6395
		} else {
			switch (bnx2x_phy_selection(params)) {
			case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
			case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6396
			/*
Y
Yaniv Rosner 已提交
6397 6398 6399
			 * In this option, the first PHY makes sure to pass the
			 * traffic through itself only.
			 * Its not clear how to reset the link on the second phy
6400
			 */
Y
Yaniv Rosner 已提交
6401 6402 6403
				active_external_phy = EXT_PHY1;
				break;
			case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6404
			/*
Y
Yaniv Rosner 已提交
6405 6406
			 * In this option, the first PHY makes sure to pass the
			 * traffic through the second PHY.
6407
			 */
Y
Yaniv Rosner 已提交
6408 6409 6410
				active_external_phy = EXT_PHY2;
				break;
			default:
6411
			/*
Y
Yaniv Rosner 已提交
6412 6413 6414 6415 6416 6417 6418
			 * Link indication on both PHYs with the following cases
			 * is invalid:
			 * - FIRST_PHY means that second phy wasn't initialized,
			 * hence its link is expected to be down
			 * - SECOND_PHY means that first phy should not be able
			 * to link up by itself (using configuration)
			 * - DEFAULT should be overriden during initialiazation
6419
			 */
Y
Yaniv Rosner 已提交
6420 6421 6422 6423 6424 6425
				DP(NETIF_MSG_LINK, "Invalid link indication"
					   "mpc=0x%x. DISABLING LINK !!!\n",
					   params->multi_phy_config);
				ext_phy_link_up = 0;
				break;
			}
E
Eilon Greenstein 已提交
6426 6427
		}
	}
Y
Yaniv Rosner 已提交
6428
	prev_line_speed = vars->line_speed;
6429 6430 6431 6432 6433 6434 6435
	/*
	 * Step 2:
	 * Read the status of the internal phy. In case of
	 * DIRECT_SINGLE_MEDIA board, this link is the external link,
	 * otherwise this is the link between the 577xx and the first
	 * external phy
	 */
Y
Yaniv Rosner 已提交
6436 6437 6438 6439
	if (params->phy[INT_PHY].read_status)
		params->phy[INT_PHY].read_status(
			&params->phy[INT_PHY],
			params, vars);
6440
	/*
Y
Yaniv Rosner 已提交
6441 6442 6443 6444 6445 6446
	 * The INT_PHY flow control reside in the vars. This include the
	 * case where the speed or flow control are not set to AUTO.
	 * Otherwise, the active external phy flow control result is set
	 * to the vars. The ext_phy_line_speed is needed to check if the
	 * speed is different between the internal phy and external phy.
	 * This case may be result of intermediate link speed change.
E
Eilon Greenstein 已提交
6447
	 */
Y
Yaniv Rosner 已提交
6448 6449
	if (active_external_phy > INT_PHY) {
		vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6450
		/*
Y
Yaniv Rosner 已提交
6451 6452
		 * Link speed is taken from the XGXS. AN and FC result from
		 * the external phy.
E
Eilon Greenstein 已提交
6453
		 */
Y
Yaniv Rosner 已提交
6454
		vars->link_status |= phy_vars[active_external_phy].link_status;
Y
Yaniv Rosner 已提交
6455

6456
		/*
Y
Yaniv Rosner 已提交
6457 6458 6459 6460 6461
		 * if active_external_phy is first PHY and link is up - disable
		 * disable TX on second external PHY
		 */
		if (active_external_phy == EXT_PHY1) {
			if (params->phy[EXT_PHY2].phy_specific_func) {
6462 6463
				DP(NETIF_MSG_LINK,
				   "Disabling TX on EXT_PHY2\n");
Y
Yaniv Rosner 已提交
6464 6465 6466 6467 6468 6469
				params->phy[EXT_PHY2].phy_specific_func(
					&params->phy[EXT_PHY2],
					params, DISABLE_TX);
			}
		}

Y
Yaniv Rosner 已提交
6470 6471 6472 6473 6474
		ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
		vars->duplex = phy_vars[active_external_phy].duplex;
		if (params->phy[active_external_phy].supported &
		    SUPPORTED_FIBRE)
			vars->link_status |= LINK_STATUS_SERDES_LINK;
Y
Yaniv Rosner 已提交
6475 6476
		else
			vars->link_status &= ~LINK_STATUS_SERDES_LINK;
Y
Yaniv Rosner 已提交
6477 6478 6479
		DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
			   active_external_phy);
	}
Y
Yaniv Rosner 已提交
6480 6481 6482 6483 6484 6485 6486 6487 6488 6489 6490

	for (phy_index = EXT_PHY1; phy_index < params->num_phys;
	      phy_index++) {
		if (params->phy[phy_index].flags &
		    FLAGS_REARM_LATCH_SIGNAL) {
			bnx2x_rearm_latch_signal(bp, port,
						 phy_index ==
						 active_external_phy);
			break;
		}
	}
Y
Yaniv Rosner 已提交
6491 6492 6493
	DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
		   " ext_phy_line_speed = %d\n", vars->flow_ctrl,
		   vars->link_status, ext_phy_line_speed);
6494
	/*
Y
Yaniv Rosner 已提交
6495 6496 6497 6498
	 * Upon link speed change set the NIG into drain mode. Comes to
	 * deals with possible FIFO glitch due to clk change when speed
	 * is decreased without link down indicator
	 */
E
Eilon Greenstein 已提交
6499

Y
Yaniv Rosner 已提交
6500 6501 6502 6503 6504 6505 6506 6507 6508
	if (vars->phy_link_up) {
		if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
		    (ext_phy_line_speed != vars->line_speed)) {
			DP(NETIF_MSG_LINK, "Internal link speed %d is"
				   " different than the external"
				   " link speed %d\n", vars->line_speed,
				   ext_phy_line_speed);
			vars->phy_link_up = 0;
		} else if (prev_line_speed != vars->line_speed) {
Y
Yaniv Rosner 已提交
6509 6510
			REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
			       0);
Y
Yaniv Rosner 已提交
6511 6512 6513
			msleep(1);
		}
	}
Y
Yaniv Rosner 已提交
6514

Y
Yaniv Rosner 已提交
6515
	/* anything 10 and over uses the bmac */
6516
	link_10g_plus = (vars->line_speed >= SPEED_10000);
E
Eilon Greenstein 已提交
6517

6518
	bnx2x_link_int_ack(params, vars, link_10g_plus);
E
Eilon Greenstein 已提交
6519

6520 6521 6522 6523 6524 6525 6526 6527
	/*
	 * In case external phy link is up, and internal link is down
	 * (not initialized yet probably after link initialization, it
	 * needs to be initialized.
	 * Note that after link down-up as result of cable plug, the xgxs
	 * link would probably become up again without the need
	 * initialize it
	 */
Y
Yaniv Rosner 已提交
6528 6529 6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541
	if (!(SINGLE_MEDIA_DIRECT(params))) {
		DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
			   " init_preceding = %d\n", ext_phy_link_up,
			   vars->phy_link_up,
			   params->phy[EXT_PHY1].flags &
			   FLAGS_INIT_XGXS_FIRST);
		if (!(params->phy[EXT_PHY1].flags &
		      FLAGS_INIT_XGXS_FIRST)
		    && ext_phy_link_up && !vars->phy_link_up) {
			vars->line_speed = ext_phy_line_speed;
			if (vars->line_speed < SPEED_1000)
				vars->phy_flags |= PHY_SGMII_FLAG;
			else
				vars->phy_flags &= ~PHY_SGMII_FLAG;
Y
Yaniv Rosner 已提交
6542 6543 6544 6545

			if (params->phy[INT_PHY].config_init)
				params->phy[INT_PHY].config_init(
					&params->phy[INT_PHY], params,
Y
Yaniv Rosner 已提交
6546
						vars);
E
Eilon Greenstein 已提交
6547
		}
E
Eilon Greenstein 已提交
6548
	}
6549 6550
	/*
	 * Link is up only if both local phy and external phy (in case of
6551
	 * non-direct board) are up and no fault detected on active PHY.
E
Eilon Greenstein 已提交
6552
	 */
Y
Yaniv Rosner 已提交
6553 6554
	vars->link_up = (vars->phy_link_up &&
			 (ext_phy_link_up ||
6555 6556
			  SINGLE_MEDIA_DIRECT(params)) &&
			 (phy_vars[active_external_phy].fault_detected == 0));
Y
Yaniv Rosner 已提交
6557 6558

	if (vars->link_up)
6559
		rc = bnx2x_update_link_up(params, vars, link_10g_plus);
E
Eilon Greenstein 已提交
6560
	else
Y
Yaniv Rosner 已提交
6561
		rc = bnx2x_update_link_down(params, vars);
E
Eilon Greenstein 已提交
6562

E
Eilon Greenstein 已提交
6563
	return rc;
E
Eilon Greenstein 已提交
6564 6565 6566
}


Y
Yaniv Rosner 已提交
6567 6568 6569 6570 6571 6572
/*****************************************************************************/
/*			    External Phy section			     */
/*****************************************************************************/
void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
{
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
Y
Yaniv Rosner 已提交
6573
		       MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
Y
Yaniv Rosner 已提交
6574 6575
	msleep(1);
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
Y
Yaniv Rosner 已提交
6576
		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
Y
Yaniv Rosner 已提交
6577
}
E
Eilon Greenstein 已提交
6578

Y
Yaniv Rosner 已提交
6579 6580 6581 6582 6583
static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
				      u32 spirom_ver, u32 ver_addr)
{
	DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
		 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
E
Eilon Greenstein 已提交
6584

Y
Yaniv Rosner 已提交
6585 6586
	if (ver_addr)
		REG_WR(bp, ver_addr, spirom_ver);
E
Eilon Greenstein 已提交
6587 6588
}

Y
Yaniv Rosner 已提交
6589 6590 6591
static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
				      struct bnx2x_phy *phy,
				      u8 port)
Y
Yaniv Rosner 已提交
6592
{
Y
Yaniv Rosner 已提交
6593 6594 6595
	u16 fw_ver1, fw_ver2;

	bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
6596
			MDIO_PMA_REG_ROM_VER1, &fw_ver1);
Y
Yaniv Rosner 已提交
6597
	bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
6598
			MDIO_PMA_REG_ROM_VER2, &fw_ver2);
Y
Yaniv Rosner 已提交
6599 6600
	bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
				  phy->ver_addr);
Y
Yaniv Rosner 已提交
6601
}
6602

Y
Yaniv Rosner 已提交
6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651 6652 6653 6654 6655
static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
				       struct bnx2x_phy *phy,
				       struct link_vars *vars)
{
	u16 val;
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD,
			MDIO_AN_REG_STATUS, &val);
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD,
			MDIO_AN_REG_STATUS, &val);
	if (val & (1<<5))
		vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
	if ((val & (1<<0)) == 0)
		vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
}

/******************************************************************/
/*		common BCM8073/BCM8727 PHY SECTION		  */
/******************************************************************/
static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
				  struct link_params *params,
				  struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	if (phy->req_line_speed == SPEED_10 ||
	    phy->req_line_speed == SPEED_100) {
		vars->flow_ctrl = phy->req_flow_ctrl;
		return;
	}

	if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
	    (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
		u16 pause_result;
		u16 ld_pause;		/* local */
		u16 lp_pause;		/* link partner */
		bnx2x_cl45_read(bp, phy,
				MDIO_AN_DEVAD,
				MDIO_AN_REG_CL37_FC_LD, &ld_pause);

		bnx2x_cl45_read(bp, phy,
				MDIO_AN_DEVAD,
				MDIO_AN_REG_CL37_FC_LP, &lp_pause);
		pause_result = (ld_pause &
				MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
		pause_result |= (lp_pause &
				 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;

		bnx2x_pause_resolve(vars, pause_result);
		DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
			   pause_result);
	}
}
Y
Yaniv Rosner 已提交
6656 6657 6658
static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
					     struct bnx2x_phy *phy,
					     u8 port)
Y
Yaniv Rosner 已提交
6659
{
6660 6661
	u32 count = 0;
	u16 fw_ver1, fw_msgout;
Y
Yaniv Rosner 已提交
6662
	int rc = 0;
6663

Y
Yaniv Rosner 已提交
6664 6665 6666
	/* Boot port from external ROM  */
	/* EDC grst */
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
6667 6668 6669
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_GEN_CTRL,
			 0x0001);
Y
Yaniv Rosner 已提交
6670 6671 6672

	/* ucode reboot and rst */
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
6673 6674 6675
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_GEN_CTRL,
			 0x008c);
Y
Yaniv Rosner 已提交
6676 6677

	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
6678 6679
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
Y
Yaniv Rosner 已提交
6680 6681 6682

	/* Reset internal microprocessor */
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
6683 6684 6685
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_GEN_CTRL,
			 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
Y
Yaniv Rosner 已提交
6686 6687 6688

	/* Release srst bit */
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
6689 6690 6691
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_GEN_CTRL,
			 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
Y
Yaniv Rosner 已提交
6692

6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718
	/* Delay 100ms per the PHY specifications */
	msleep(100);

	/* 8073 sometimes taking longer to download */
	do {
		count++;
		if (count > 300) {
			DP(NETIF_MSG_LINK,
				 "bnx2x_8073_8727_external_rom_boot port %x:"
				 "Download failed. fw version = 0x%x\n",
				 port, fw_ver1);
			rc = -EINVAL;
			break;
		}

		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_ROM_VER1, &fw_ver1);
		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);

		msleep(1);
	} while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
			((fw_msgout & 0xff) != 0x03 && (phy->type ==
			PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
Y
Yaniv Rosner 已提交
6719 6720 6721

	/* Clear ser_boot_ctl bit */
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
6722 6723
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
Y
Yaniv Rosner 已提交
6724
	bnx2x_save_bcm_spirom_ver(bp, phy, port);
6725 6726 6727 6728 6729 6730 6731

	DP(NETIF_MSG_LINK,
		 "bnx2x_8073_8727_external_rom_boot port %x:"
		 "Download complete. fw version = 0x%x\n",
		 port, fw_ver1);

	return rc;
Y
Yaniv Rosner 已提交
6732 6733 6734 6735 6736
}

/******************************************************************/
/*			BCM8073 PHY SECTION			  */
/******************************************************************/
Y
Yaniv Rosner 已提交
6737
static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
Y
Yaniv Rosner 已提交
6738 6739 6740 6741 6742 6743
{
	/* This is only required for 8073A1, version 102 only */
	u16 val;

	/* Read 8073 HW revision*/
	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
6744 6745
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_8073_CHIP_REV, &val);
Y
Yaniv Rosner 已提交
6746 6747 6748 6749 6750 6751 6752

	if (val != 1) {
		/* No need to workaround in 8073 A1 */
		return 0;
	}

	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
6753 6754
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_ROM_VER2, &val);
Y
Yaniv Rosner 已提交
6755 6756 6757 6758 6759 6760 6761 6762

	/* SNR should be applied only for version 0x102 */
	if (val != 0x102)
		return 0;

	return 1;
}

Y
Yaniv Rosner 已提交
6763
static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
Y
Yaniv Rosner 已提交
6764 6765 6766 6767
{
	u16 val, cnt, cnt1 ;

	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
6768 6769
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_8073_CHIP_REV, &val);
Y
Yaniv Rosner 已提交
6770 6771 6772 6773 6774 6775 6776

	if (val > 0) {
		/* No need to workaround in 8073 A1 */
		return 0;
	}
	/* XAUI workaround in 8073 A0: */

6777 6778 6779 6780
	/*
	 * After loading the boot ROM and restarting Autoneg, poll
	 * Dev1, Reg $C820:
	 */
Y
Yaniv Rosner 已提交
6781 6782 6783

	for (cnt = 0; cnt < 1000; cnt++) {
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
6784 6785 6786
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
				&val);
6787 6788 6789 6790 6791
		  /*
		   * If bit [14] = 0 or bit [13] = 0, continue on with
		   * system initialization (XAUI work-around not required, as
		   * these bits indicate 2.5G or 1G link up).
		   */
Y
Yaniv Rosner 已提交
6792 6793 6794 6795
		if (!(val & (1<<14)) || !(val & (1<<13))) {
			DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
			return 0;
		} else if (!(val & (1<<15))) {
6796 6797 6798 6799 6800 6801 6802
			DP(NETIF_MSG_LINK, "bit 15 went off\n");
			/*
			 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
			 * MSB (bit15) goes to 1 (indicating that the XAUI
			 * workaround has completed), then continue on with
			 * system initialization.
			 */
Y
Yaniv Rosner 已提交
6803 6804 6805 6806 6807 6808 6809 6810 6811 6812 6813 6814 6815 6816 6817 6818 6819 6820 6821 6822 6823 6824 6825 6826 6827 6828 6829 6830 6831 6832 6833 6834
			for (cnt1 = 0; cnt1 < 1000; cnt1++) {
				bnx2x_cl45_read(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_8073_XAUI_WA, &val);
				if (val & (1<<15)) {
					DP(NETIF_MSG_LINK,
					  "XAUI workaround has completed\n");
					return 0;
				 }
				 msleep(3);
			}
			break;
		}
		msleep(3);
	}
	DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
	return -EINVAL;
}

static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
{
	/* Force KR or KX */
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
	bnx2x_cl45_write(bp, phy,
			 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
}

Y
Yaniv Rosner 已提交
6835
static void bnx2x_8073_set_pause_cl37(struct link_params *params,
Y
Yaniv Rosner 已提交
6836 6837
				      struct bnx2x_phy *phy,
				      struct link_vars *vars)
Y
Yaniv Rosner 已提交
6838
{
Y
Yaniv Rosner 已提交
6839
	u16 cl37_val;
Y
Yaniv Rosner 已提交
6840 6841
	struct bnx2x *bp = params->bp;
	bnx2x_cl45_read(bp, phy,
6842
			MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
Y
Yaniv Rosner 已提交
6843 6844 6845

	cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
	/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
Y
Yaniv Rosner 已提交
6846
	bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
Y
Yaniv Rosner 已提交
6847 6848 6849 6850 6851 6852 6853 6854 6855 6856 6857 6858 6859 6860 6861 6862 6863 6864
	if ((vars->ieee_fc &
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
		cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
	}
	if ((vars->ieee_fc &
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
		cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
	}
	if ((vars->ieee_fc &
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
	    MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
		cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
	}
	DP(NETIF_MSG_LINK,
		 "Ext phy AN advertize cl37 0x%x\n", cl37_val);

Y
Yaniv Rosner 已提交
6865
	bnx2x_cl45_write(bp, phy,
6866
			 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
Y
Yaniv Rosner 已提交
6867
	msleep(500);
Y
Yaniv Rosner 已提交
6868 6869
}

Y
Yaniv Rosner 已提交
6870 6871 6872
static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
				  struct link_params *params,
				  struct link_vars *vars)
Y
Yaniv Rosner 已提交
6873
{
Y
Yaniv Rosner 已提交
6874
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
6875 6876 6877
	u16 val = 0, tmp1;
	u8 gpio_port;
	DP(NETIF_MSG_LINK, "Init 8073\n");
Y
Yaniv Rosner 已提交
6878

D
Dmitry Kravkov 已提交
6879 6880 6881 6882
	if (CHIP_IS_E2(bp))
		gpio_port = BP_PATH(bp);
	else
		gpio_port = params->port;
Y
Yaniv Rosner 已提交
6883 6884
	/* Restore normal power mode*/
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Y
Yaniv Rosner 已提交
6885
		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
Y
Yaniv Rosner 已提交
6886

Y
Yaniv Rosner 已提交
6887
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
Y
Yaniv Rosner 已提交
6888
		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
Y
Yaniv Rosner 已提交
6889

Y
Yaniv Rosner 已提交
6890 6891
	/* enable LASI */
	bnx2x_cl45_write(bp, phy,
6892
			 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
Y
Yaniv Rosner 已提交
6893
	bnx2x_cl45_write(bp, phy,
6894
			 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
6895

Y
Yaniv Rosner 已提交
6896
	bnx2x_8073_set_pause_cl37(params, phy, vars);
6897

Y
Yaniv Rosner 已提交
6898
	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
6899
			MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6900

Y
Yaniv Rosner 已提交
6901
	bnx2x_cl45_read(bp, phy,
6902
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6903

Y
Yaniv Rosner 已提交
6904
	DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6905

6906 6907 6908 6909 6910 6911 6912 6913 6914 6915 6916 6917 6918 6919 6920
	/* Swap polarity if required - Must be done only in non-1G mode */
	if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
		/* Configure the 8073 to swap _P and _N of the KR lines */
		DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
		/* 10G Rx/Tx and 1G Tx signal polarity swap */
		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
				 (val | (3<<9)));
	}


Y
Yaniv Rosner 已提交
6921
	/* Enable CL37 BAM */
6922 6923 6924 6925
	if (REG_RD(bp, params->shmem_base +
			 offsetof(struct shmem_region, dev_info.
				  port_hw_config[params->port].default_cfg)) &
	    PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6926

6927 6928 6929 6930 6931 6932 6933 6934
		bnx2x_cl45_read(bp, phy,
				MDIO_AN_DEVAD,
				MDIO_AN_REG_8073_BAM, &val);
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD,
				 MDIO_AN_REG_8073_BAM, val | 1);
		DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
	}
Y
Yaniv Rosner 已提交
6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947
	if (params->loopback_mode == LOOPBACK_EXT) {
		bnx2x_807x_force_10G(bp, phy);
		DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
		return 0;
	} else {
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
	}
	if (phy->req_line_speed != SPEED_AUTO_NEG) {
		if (phy->req_line_speed == SPEED_10000) {
			val = (1<<7);
		} else if (phy->req_line_speed ==  SPEED_2500) {
			val = (1<<5);
6948 6949
			/*
			 * Note that 2.5G works only when used with 1G
L
Lucas De Marchi 已提交
6950
			 * advertisement
6951
			 */
Y
Yaniv Rosner 已提交
6952 6953 6954 6955 6956 6957 6958
		} else
			val = (1<<5);
	} else {
		val = 0;
		if (phy->speed_cap_mask &
			PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
			val |= (1<<7);
6959

L
Lucas De Marchi 已提交
6960
		/* Note that 2.5G works only when used with 1G advertisement */
Y
Yaniv Rosner 已提交
6961 6962 6963 6964 6965 6966
		if (phy->speed_cap_mask &
			(PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
			 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
			val |= (1<<5);
		DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
	}
6967

Y
Yaniv Rosner 已提交
6968 6969
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6970

Y
Yaniv Rosner 已提交
6971 6972 6973 6974 6975 6976 6977 6978 6979 6980 6981 6982 6983 6984 6985 6986 6987
	if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
	     (phy->req_line_speed == SPEED_AUTO_NEG)) ||
	    (phy->req_line_speed == SPEED_2500)) {
		u16 phy_ver;
		/* Allow 2.5G for A1 and above */
		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
				&phy_ver);
		DP(NETIF_MSG_LINK, "Add 2.5G\n");
		if (phy_ver > 0)
			tmp1 |= 1;
		else
			tmp1 &= 0xfffe;
	} else {
		DP(NETIF_MSG_LINK, "Disable 2.5G\n");
		tmp1 &= 0xfffe;
	}
6988

Y
Yaniv Rosner 已提交
6989 6990
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
	/* Add support for CL37 (passive mode) II */
6991

Y
Yaniv Rosner 已提交
6992 6993 6994 6995
	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
			 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
				  0x20 : 0x40)));
6996

Y
Yaniv Rosner 已提交
6997 6998
	/* Add support for CL37 (passive mode) III */
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6999

7000 7001 7002 7003 7004
	/*
	 * The SNR will improve about 2db by changing BW and FEE main
	 * tap. Rest commands are executed after link is up
	 * Change FFE main cursor to 5 in EDC register
	 */
Y
Yaniv Rosner 已提交
7005 7006 7007 7008
	if (bnx2x_8073_is_snr_needed(bp, phy))
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
				 0xFB0C);
7009

Y
Yaniv Rosner 已提交
7010 7011 7012 7013
	/* Enable FEC (Forware Error Correction) Request in the AN */
	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
	tmp1 |= (1<<15);
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7014

Y
Yaniv Rosner 已提交
7015
	bnx2x_ext_phy_set_pause(params, phy, vars);
7016

Y
Yaniv Rosner 已提交
7017 7018 7019 7020 7021 7022
	/* Restart autoneg */
	msleep(500);
	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
	DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
		   ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
	return 0;
Y
Yaniv Rosner 已提交
7023
}
Y
Yaniv Rosner 已提交
7024

Y
Yaniv Rosner 已提交
7025
static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
Y
Yaniv Rosner 已提交
7026 7027 7028 7029
				 struct link_params *params,
				 struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
7030 7031 7032 7033
	u8 link_up = 0;
	u16 val1, val2;
	u16 link_status = 0;
	u16 an1000_status = 0;
E
Eilon Greenstein 已提交
7034

Y
Yaniv Rosner 已提交
7035
	bnx2x_cl45_read(bp, phy,
7036
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
Y
Yaniv Rosner 已提交
7037

Y
Yaniv Rosner 已提交
7038
	DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
Y
Yaniv Rosner 已提交
7039

Y
Yaniv Rosner 已提交
7040 7041 7042 7043 7044 7045 7046 7047 7048 7049 7050 7051
	/* clear the interrupt LASI status register */
	bnx2x_cl45_read(bp, phy,
			MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
	bnx2x_cl45_read(bp, phy,
			MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
	DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
	/* Clear MSG-OUT */
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);

	/* Check the LASI */
	bnx2x_cl45_read(bp, phy,
7052
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
Y
Yaniv Rosner 已提交
7053 7054 7055 7056 7057 7058 7059 7060 7061 7062 7063 7064 7065 7066 7067 7068 7069 7070 7071

	DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);

	/* Check the link status */
	bnx2x_cl45_read(bp, phy,
			MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
	DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);

	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
	link_up = ((val1 & 4) == 4);
	DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);

	if (link_up &&
	     ((phy->req_line_speed != SPEED_10000))) {
		if (bnx2x_8073_xaui_wa(bp, phy) != 0)
			return 0;
7072
	}
Y
Yaniv Rosner 已提交
7073 7074 7075 7076
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7077

Y
Yaniv Rosner 已提交
7078 7079 7080 7081 7082 7083 7084
	/* Check the link status on 1.1.2 */
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
	DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
		   "an_link_status=0x%x\n", val2, val1, an1000_status);
7085

Y
Yaniv Rosner 已提交
7086 7087
	link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
	if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7088 7089 7090 7091 7092
		/*
		 * The SNR will improve about 2dbby changing the BW and FEE main
		 * tap. The 1st write to change FFE main tap is set before
		 * restart AN. Change PLL Bandwidth in EDC register
		 */
7093
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7094 7095
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
				 0x26BC);
7096

Y
Yaniv Rosner 已提交
7097
		/* Change CDR Bandwidth in EDC register */
7098
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7099 7100 7101 7102 7103 7104
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
				 0x0333);
	}
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
			&link_status);
7105

Y
Yaniv Rosner 已提交
7106 7107 7108 7109 7110 7111 7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125
	/* Bits 0..2 --> speed detected, bits 13..15--> link is down */
	if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
		link_up = 1;
		vars->line_speed = SPEED_10000;
		DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
			   params->port);
	} else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
		link_up = 1;
		vars->line_speed = SPEED_2500;
		DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
			   params->port);
	} else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
		link_up = 1;
		vars->line_speed = SPEED_1000;
		DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
			   params->port);
	} else {
		link_up = 0;
		DP(NETIF_MSG_LINK, "port %x: External link is down\n",
			   params->port);
7126
	}
Y
Yaniv Rosner 已提交
7127 7128

	if (link_up) {
7129 7130 7131 7132 7133 7134 7135
		/* Swap polarity if required */
		if (params->lane_config &
		    PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
			/* Configure the 8073 to swap P and N of the KR lines */
			bnx2x_cl45_read(bp, phy,
					MDIO_XS_DEVAD,
					MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7136 7137 7138 7139
			/*
			 * Set bit 3 to invert Rx in 1G mode and clear this bit
			 * when it`s in 10G mode.
			 */
7140 7141 7142 7143 7144 7145 7146 7147 7148 7149 7150 7151
			if (vars->line_speed == SPEED_1000) {
				DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
					      "the 8073\n");
				val1 |= (1<<3);
			} else
				val1 &= ~(1<<3);

			bnx2x_cl45_write(bp, phy,
					 MDIO_XS_DEVAD,
					 MDIO_XS_REG_8073_RX_CTRL_PCIE,
					 val1);
		}
Y
Yaniv Rosner 已提交
7152 7153
		bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
		bnx2x_8073_resolve_fc(phy, params, vars);
7154
		vars->duplex = DUPLEX_FULL;
Y
Yaniv Rosner 已提交
7155 7156
	}
	return link_up;
Y
Yaniv Rosner 已提交
7157 7158
}

Y
Yaniv Rosner 已提交
7159 7160 7161 7162 7163
static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
				  struct link_params *params)
{
	struct bnx2x *bp = params->bp;
	u8 gpio_port;
D
Dmitry Kravkov 已提交
7164 7165 7166 7167
	if (CHIP_IS_E2(bp))
		gpio_port = BP_PATH(bp);
	else
		gpio_port = params->port;
Y
Yaniv Rosner 已提交
7168 7169 7170
	DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
	   gpio_port);
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Y
Yaniv Rosner 已提交
7171 7172
		       MISC_REGISTERS_GPIO_OUTPUT_LOW,
		       gpio_port);
Y
Yaniv Rosner 已提交
7173 7174 7175 7176 7177
}

/******************************************************************/
/*			BCM8705 PHY SECTION			  */
/******************************************************************/
Y
Yaniv Rosner 已提交
7178 7179 7180
static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
				  struct link_params *params,
				  struct link_vars *vars)
Y
Yaniv Rosner 已提交
7181 7182
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
7183
	DP(NETIF_MSG_LINK, "init 8705\n");
Y
Yaniv Rosner 已提交
7184 7185
	/* Restore normal power mode*/
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Y
Yaniv Rosner 已提交
7186
		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
Y
Yaniv Rosner 已提交
7187 7188 7189
	/* HW reset */
	bnx2x_ext_phy_hw_reset(bp, params->port);
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7190
	bnx2x_wait_reset_complete(bp, phy, params);
Y
Yaniv Rosner 已提交
7191

Y
Yaniv Rosner 已提交
7192 7193 7194 7195 7196 7197 7198 7199 7200 7201 7202 7203
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
	bnx2x_cl45_write(bp, phy,
			 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
	/* BCM8705 doesn't have microcode, hence the 0 */
	bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
	return 0;
}
E
Eilon Greenstein 已提交
7204

Y
Yaniv Rosner 已提交
7205 7206 7207 7208 7209 7210 7211 7212 7213 7214 7215
static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
				 struct link_params *params,
				 struct link_vars *vars)
{
	u8 link_up = 0;
	u16 val1, rx_sd;
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "read status 8705\n");
	bnx2x_cl45_read(bp, phy,
		      MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
	DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7216

Y
Yaniv Rosner 已提交
7217 7218 7219
	bnx2x_cl45_read(bp, phy,
		      MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
	DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7220

Y
Yaniv Rosner 已提交
7221 7222
	bnx2x_cl45_read(bp, phy,
		      MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7223

Y
Yaniv Rosner 已提交
7224 7225 7226 7227
	bnx2x_cl45_read(bp, phy,
		      MDIO_PMA_DEVAD, 0xc809, &val1);
	bnx2x_cl45_read(bp, phy,
		      MDIO_PMA_DEVAD, 0xc809, &val1);
7228

Y
Yaniv Rosner 已提交
7229 7230 7231 7232 7233
	DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
	link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
	if (link_up) {
		vars->line_speed = SPEED_10000;
		bnx2x_ext_phy_resolve_fc(phy, params, vars);
7234
	}
Y
Yaniv Rosner 已提交
7235 7236
	return link_up;
}
7237

Y
Yaniv Rosner 已提交
7238 7239 7240
/******************************************************************/
/*			SFP+ module Section			  */
/******************************************************************/
7241 7242 7243 7244 7245 7246 7247 7248 7249 7250 7251 7252 7253 7254 7255 7256 7257 7258 7259 7260 7261 7262 7263 7264
static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
					   struct bnx2x_phy *phy,
					   u8 pmd_dis)
{
	struct bnx2x *bp = params->bp;
	/*
	 * Disable transmitter only for bootcodes which can enable it afterwards
	 * (for D3 link)
	 */
	if (pmd_dis) {
		if (params->feature_config_flags &
		     FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
			DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
		else {
			DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
			return;
		}
	} else
		DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
}

7265 7266 7267 7268 7269 7270 7271 7272 7273 7274 7275 7276 7277
static u8 bnx2x_get_gpio_port(struct link_params *params)
{
	u8 gpio_port;
	u32 swap_val, swap_override;
	struct bnx2x *bp = params->bp;
	if (CHIP_IS_E2(bp))
		gpio_port = BP_PATH(bp);
	else
		gpio_port = params->port;
	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
	return gpio_port ^ (swap_val && swap_override);
}
7278 7279 7280 7281

static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
					   struct bnx2x_phy *phy,
					   u8 tx_en)
Y
Yaniv Rosner 已提交
7282 7283
{
	u16 val;
7284 7285 7286
	u8 port = params->port;
	struct bnx2x *bp = params->bp;
	u32 tx_en_mode;
7287

Y
Yaniv Rosner 已提交
7288
	/* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7289 7290 7291 7292 7293 7294 7295 7296
	tx_en_mode = REG_RD(bp, params->shmem_base +
			    offsetof(struct shmem_region,
				     dev_info.port_hw_config[port].sfp_ctrl)) &
		PORT_HW_CFG_TX_LASER_MASK;
	DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
			   "mode = %x\n", tx_en, port, tx_en_mode);
	switch (tx_en_mode) {
	case PORT_HW_CFG_TX_LASER_MDIO:
7297

7298 7299 7300 7301
		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_PHY_IDENTIFIER,
				&val);
Y
Yaniv Rosner 已提交
7302

7303 7304 7305 7306 7307 7308 7309 7310 7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328 7329 7330 7331 7332 7333
		if (tx_en)
			val &= ~(1<<15);
		else
			val |= (1<<15);

		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_PHY_IDENTIFIER,
				 val);
	break;
	case PORT_HW_CFG_TX_LASER_GPIO0:
	case PORT_HW_CFG_TX_LASER_GPIO1:
	case PORT_HW_CFG_TX_LASER_GPIO2:
	case PORT_HW_CFG_TX_LASER_GPIO3:
	{
		u16 gpio_pin;
		u8 gpio_port, gpio_mode;
		if (tx_en)
			gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
		else
			gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;

		gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
		gpio_port = bnx2x_get_gpio_port(params);
		bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
		break;
	}
	default:
		DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
		break;
	}
Y
Yaniv Rosner 已提交
7334 7335
}

7336 7337 7338 7339 7340 7341 7342 7343 7344 7345 7346 7347
static void bnx2x_sfp_set_transmitter(struct link_params *params,
				      struct bnx2x_phy *phy,
				      u8 tx_en)
{
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
	if (CHIP_IS_E3(bp))
		bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
	else
		bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
}

Y
Yaniv Rosner 已提交
7348 7349 7350
static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
					     struct link_params *params,
					     u16 addr, u8 byte_cnt, u8 *o_buf)
Y
Yaniv Rosner 已提交
7351 7352
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
7353 7354 7355
	u16 val = 0;
	u16 i;
	if (byte_cnt > 16) {
7356 7357
		DP(NETIF_MSG_LINK,
		   "Reading from eeprom is limited to 0xf\n");
Y
Yaniv Rosner 已提交
7358 7359 7360
		return -EINVAL;
	}
	/* Set the read command byte count */
7361
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7362
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
Y
Yaniv Rosner 已提交
7363
			 (byte_cnt | 0xa000));
Y
Yaniv Rosner 已提交
7364

Y
Yaniv Rosner 已提交
7365 7366 7367
	/* Set the read command address */
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
Y
Yaniv Rosner 已提交
7368
			 addr);
Y
Yaniv Rosner 已提交
7369

Y
Yaniv Rosner 已提交
7370
	/* Activate read command */
7371
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7372
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
Y
Yaniv Rosner 已提交
7373
			 0x2c0f);
Y
Yaniv Rosner 已提交
7374

Y
Yaniv Rosner 已提交
7375 7376 7377
	/* Wait up to 500us for command complete status */
	for (i = 0; i < 100; i++) {
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7378 7379
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
Y
Yaniv Rosner 已提交
7380 7381 7382 7383
		if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
			break;
		udelay(5);
7384 7385
	}

Y
Yaniv Rosner 已提交
7386 7387 7388 7389 7390 7391
	if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
		DP(NETIF_MSG_LINK,
			 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
			 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
		return -EINVAL;
7392
	}
Y
Yaniv Rosner 已提交
7393

Y
Yaniv Rosner 已提交
7394 7395
	/* Read the buffer */
	for (i = 0; i < byte_cnt; i++) {
7396
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7397 7398
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
Y
Yaniv Rosner 已提交
7399
		o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7400
	}
Y
Yaniv Rosner 已提交
7401

Y
Yaniv Rosner 已提交
7402 7403
	for (i = 0; i < 100; i++) {
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7404 7405
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
Y
Yaniv Rosner 已提交
7406 7407
		if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7408
			return 0;
Y
Yaniv Rosner 已提交
7409 7410 7411
		msleep(1);
	}
	return -EINVAL;
Y
Yaniv Rosner 已提交
7412
}
E
Eilon Greenstein 已提交
7413

7414 7415 7416 7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427
static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
						 struct link_params *params,
						 u16 addr, u8 byte_cnt,
						 u8 *o_buf)
{
	int rc = 0;
	u8 i, j = 0, cnt = 0;
	u32 data_array[4];
	u16 addr32;
	struct bnx2x *bp = params->bp;
	/*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
					" addr %d, cnt %d\n",
					addr, byte_cnt);*/
	if (byte_cnt > 16) {
7428 7429
		DP(NETIF_MSG_LINK,
		   "Reading from eeprom is limited to 16 bytes\n");
7430 7431 7432 7433 7434 7435 7436 7437 7438 7439 7440 7441 7442 7443 7444 7445 7446 7447 7448 7449
		return -EINVAL;
	}

	/* 4 byte aligned address */
	addr32 = addr & (~0x3);
	do {
		rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
				    data_array);
	} while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));

	if (rc == 0) {
		for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
			o_buf[j] = *((u8 *)data_array + i);
			j++;
		}
	}

	return rc;
}

Y
Yaniv Rosner 已提交
7450 7451 7452
static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
					     struct link_params *params,
					     u16 addr, u8 byte_cnt, u8 *o_buf)
Y
Yaniv Rosner 已提交
7453 7454
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
7455
	u16 val, i;
Y
Yaniv Rosner 已提交
7456

Y
Yaniv Rosner 已提交
7457
	if (byte_cnt > 16) {
7458 7459
		DP(NETIF_MSG_LINK,
		   "Reading from eeprom is limited to 0xf\n");
Y
Yaniv Rosner 已提交
7460 7461
		return -EINVAL;
	}
E
Eilon Greenstein 已提交
7462

Y
Yaniv Rosner 已提交
7463 7464
	/* Need to read from 1.8000 to clear it */
	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7465 7466 7467
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
			&val);
E
Eilon Greenstein 已提交
7468

Y
Yaniv Rosner 已提交
7469
	/* Set the read command byte count */
7470
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7471 7472 7473
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
			 ((byte_cnt < 2) ? 2 : byte_cnt));
Y
Yaniv Rosner 已提交
7474

Y
Yaniv Rosner 已提交
7475
	/* Set the read command address */
7476
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7477 7478 7479
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
			 addr);
Y
Yaniv Rosner 已提交
7480
	/* Set the destination address */
7481
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7482 7483 7484
			 MDIO_PMA_DEVAD,
			 0x8004,
			 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7485

Y
Yaniv Rosner 已提交
7486
	/* Activate read command */
7487
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7488 7489 7490
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
			 0x8002);
7491 7492 7493 7494
	/*
	 * Wait appropriate time for two-wire command to finish before
	 * polling the status register
	 */
Y
Yaniv Rosner 已提交
7495
	msleep(1);
E
Eilon Greenstein 已提交
7496

Y
Yaniv Rosner 已提交
7497 7498
	/* Wait up to 500us for command complete status */
	for (i = 0; i < 100; i++) {
7499
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7500 7501
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
Y
Yaniv Rosner 已提交
7502 7503 7504 7505
		if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
			break;
		udelay(5);
7506
	}
E
Eilon Greenstein 已提交
7507

Y
Yaniv Rosner 已提交
7508 7509 7510 7511 7512
	if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
		DP(NETIF_MSG_LINK,
			 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
			 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7513
		return -EFAULT;
Y
Yaniv Rosner 已提交
7514
	}
7515

Y
Yaniv Rosner 已提交
7516 7517 7518
	/* Read the buffer */
	for (i = 0; i < byte_cnt; i++) {
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7519 7520
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
Y
Yaniv Rosner 已提交
7521 7522
		o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
	}
E
Eilon Greenstein 已提交
7523

Y
Yaniv Rosner 已提交
7524 7525
	for (i = 0; i < 100; i++) {
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7526 7527
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
Y
Yaniv Rosner 已提交
7528 7529
		if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
		    MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7530
			return 0;
Y
Yaniv Rosner 已提交
7531
		msleep(1);
7532 7533
	}

Y
Yaniv Rosner 已提交
7534
	return -EINVAL;
Y
Yaniv Rosner 已提交
7535 7536
}

Y
Yaniv Rosner 已提交
7537 7538 7539
int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
				 struct link_params *params, u16 addr,
				 u8 byte_cnt, u8 *o_buf)
Y
Yaniv Rosner 已提交
7540
{
Y
Yaniv Rosner 已提交
7541
	int rc = -EINVAL;
Y
Yaniv Rosner 已提交
7542 7543 7544 7545 7546 7547 7548 7549 7550 7551
	switch (phy->type) {
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
		rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
						       byte_cnt, o_buf);
	break;
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
		rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
						       byte_cnt, o_buf);
	break;
7552 7553 7554 7555
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
		rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
							   byte_cnt, o_buf);
	break;
Y
Yaniv Rosner 已提交
7556 7557
	}
	return rc;
Y
Yaniv Rosner 已提交
7558 7559
}

Y
Yaniv Rosner 已提交
7560 7561 7562
static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
			      struct link_params *params,
			      u16 *edc_mode)
Y
Yaniv Rosner 已提交
7563 7564
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
7565
	u32 sync_offset = 0, phy_idx, media_types;
Y
Yaniv Rosner 已提交
7566 7567
	u8 val, check_limiting_mode = 0;
	*edc_mode = EDC_MODE_LIMITING;
7568

Y
Yaniv Rosner 已提交
7569
	phy->media_type = ETH_PHY_UNSPECIFIED;
Y
Yaniv Rosner 已提交
7570 7571 7572 7573 7574 7575 7576 7577 7578
	/* First check for copper cable */
	if (bnx2x_read_sfp_module_eeprom(phy,
					 params,
					 SFP_EEPROM_CON_TYPE_ADDR,
					 1,
					 &val) != 0) {
		DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
		return -EINVAL;
	}
7579

Y
Yaniv Rosner 已提交
7580 7581 7582 7583
	switch (val) {
	case SFP_EEPROM_CON_TYPE_VAL_COPPER:
	{
		u8 copper_module_type;
Y
Yaniv Rosner 已提交
7584
		phy->media_type = ETH_PHY_DA_TWINAX;
7585 7586 7587 7588
		/*
		 * Check if its active cable (includes SFP+ module)
		 * of passive cable
		 */
Y
Yaniv Rosner 已提交
7589 7590 7591 7592
		if (bnx2x_read_sfp_module_eeprom(phy,
					       params,
					       SFP_EEPROM_FC_TX_TECH_ADDR,
					       1,
7593
					       &copper_module_type) != 0) {
Y
Yaniv Rosner 已提交
7594 7595 7596 7597 7598
			DP(NETIF_MSG_LINK,
				"Failed to read copper-cable-type"
				" from SFP+ EEPROM\n");
			return -EINVAL;
		}
Y
Yaniv Rosner 已提交
7599

Y
Yaniv Rosner 已提交
7600 7601 7602 7603 7604 7605
		if (copper_module_type &
		    SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
			DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
			check_limiting_mode = 1;
		} else if (copper_module_type &
			SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7606 7607
				DP(NETIF_MSG_LINK,
				   "Passive Copper cable detected\n");
Y
Yaniv Rosner 已提交
7608 7609 7610
				*edc_mode =
				      EDC_MODE_PASSIVE_DAC;
		} else {
7611 7612 7613
			DP(NETIF_MSG_LINK,
			   "Unknown copper-cable-type 0x%x !!!\n",
			   copper_module_type);
Y
Yaniv Rosner 已提交
7614 7615 7616
			return -EINVAL;
		}
		break;
7617
	}
Y
Yaniv Rosner 已提交
7618
	case SFP_EEPROM_CON_TYPE_VAL_LC:
Y
Yaniv Rosner 已提交
7619
		phy->media_type = ETH_PHY_SFP_FIBER;
Y
Yaniv Rosner 已提交
7620 7621 7622 7623 7624 7625 7626
		DP(NETIF_MSG_LINK, "Optic module detected\n");
		check_limiting_mode = 1;
		break;
	default:
		DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
			 val);
		return -EINVAL;
7627
	}
Y
Yaniv Rosner 已提交
7628 7629 7630 7631 7632 7633 7634 7635 7636 7637 7638 7639 7640 7641 7642 7643
	sync_offset = params->shmem_base +
		offsetof(struct shmem_region,
			 dev_info.port_hw_config[params->port].media_type);
	media_types = REG_RD(bp, sync_offset);
	/* Update media type for non-PMF sync */
	for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
		if (&(params->phy[phy_idx]) == phy) {
			media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
				(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
			media_types |= ((phy->media_type &
					PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
				(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
			break;
		}
	}
	REG_WR(bp, sync_offset, media_types);
Y
Yaniv Rosner 已提交
7644 7645 7646 7647 7648 7649 7650
	if (check_limiting_mode) {
		u8 options[SFP_EEPROM_OPTIONS_SIZE];
		if (bnx2x_read_sfp_module_eeprom(phy,
						 params,
						 SFP_EEPROM_OPTIONS_ADDR,
						 SFP_EEPROM_OPTIONS_SIZE,
						 options) != 0) {
7651 7652
			DP(NETIF_MSG_LINK,
			   "Failed to read Option field from module EEPROM\n");
Y
Yaniv Rosner 已提交
7653 7654 7655 7656 7657 7658
			return -EINVAL;
		}
		if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
			*edc_mode = EDC_MODE_LINEAR;
		else
			*edc_mode = EDC_MODE_LIMITING;
7659
	}
Y
Yaniv Rosner 已提交
7660
	DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7661
	return 0;
Y
Yaniv Rosner 已提交
7662
}
7663 7664 7665 7666
/*
 * This function read the relevant field from the module (SFP+), and verify it
 * is compliant with this board
 */
Y
Yaniv Rosner 已提交
7667 7668
static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
				   struct link_params *params)
Y
Yaniv Rosner 已提交
7669 7670
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
7671 7672
	u32 val, cmd;
	u32 fw_resp, fw_cmd_param;
Y
Yaniv Rosner 已提交
7673 7674
	char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
	char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
Y
Yaniv Rosner 已提交
7675
	phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
Y
Yaniv Rosner 已提交
7676 7677 7678 7679 7680 7681 7682 7683
	val = REG_RD(bp, params->shmem_base +
			 offsetof(struct shmem_region, dev_info.
				  port_feature_config[params->port].config));
	if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
	    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
		DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
		return 0;
	}
Y
Yaniv Rosner 已提交
7684

Y
Yaniv Rosner 已提交
7685 7686 7687 7688 7689 7690 7691 7692
	if (params->feature_config_flags &
	    FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
		/* Use specific phy request */
		cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
	} else if (params->feature_config_flags &
		   FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
		/* Use first phy request only in case of non-dual media*/
		if (DUAL_MEDIA(params)) {
7693 7694
			DP(NETIF_MSG_LINK,
			   "FW does not support OPT MDL verification\n");
Y
Yaniv Rosner 已提交
7695 7696 7697 7698 7699
			return -EINVAL;
		}
		cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
	} else {
		/* No support in OPT MDL detection */
7700 7701
		DP(NETIF_MSG_LINK,
		   "FW does not support OPT MDL verification\n");
Y
Yaniv Rosner 已提交
7702 7703
		return -EINVAL;
	}
7704

Y
Yaniv Rosner 已提交
7705 7706
	fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
	fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
Y
Yaniv Rosner 已提交
7707 7708 7709 7710
	if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
		DP(NETIF_MSG_LINK, "Approved module\n");
		return 0;
	}
Y
Yaniv Rosner 已提交
7711

Y
Yaniv Rosner 已提交
7712 7713 7714
	/* format the warning message */
	if (bnx2x_read_sfp_module_eeprom(phy,
					 params,
Y
Yaniv Rosner 已提交
7715 7716 7717
					 SFP_EEPROM_VENDOR_NAME_ADDR,
					 SFP_EEPROM_VENDOR_NAME_SIZE,
					 (u8 *)vendor_name))
Y
Yaniv Rosner 已提交
7718 7719 7720 7721 7722
		vendor_name[0] = '\0';
	else
		vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
	if (bnx2x_read_sfp_module_eeprom(phy,
					 params,
Y
Yaniv Rosner 已提交
7723 7724 7725
					 SFP_EEPROM_PART_NO_ADDR,
					 SFP_EEPROM_PART_NO_SIZE,
					 (u8 *)vendor_pn))
Y
Yaniv Rosner 已提交
7726 7727 7728 7729
		vendor_pn[0] = '\0';
	else
		vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';

7730 7731 7732
	netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
			      " Port %d from %s part number %s\n",
			 params->port, vendor_name, vendor_pn);
Y
Yaniv Rosner 已提交
7733
	phy->flags |= FLAGS_SFP_NOT_APPROVED;
Y
Yaniv Rosner 已提交
7734
	return -EINVAL;
Y
Yaniv Rosner 已提交
7735
}
7736

Y
Yaniv Rosner 已提交
7737 7738
static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
						 struct link_params *params)
7739

E
Eilon Greenstein 已提交
7740
{
Y
Yaniv Rosner 已提交
7741
	u8 val;
E
Eilon Greenstein 已提交
7742
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
7743
	u16 timeout;
7744 7745 7746 7747 7748
	/*
	 * Initialization time after hot-plug may take up to 300ms for
	 * some phys type ( e.g. JDSU )
	 */

Y
Yaniv Rosner 已提交
7749 7750 7751
	for (timeout = 0; timeout < 60; timeout++) {
		if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
		    == 0) {
7752 7753 7754
			DP(NETIF_MSG_LINK,
			   "SFP+ module initialization took %d ms\n",
			   timeout * 5);
Y
Yaniv Rosner 已提交
7755 7756 7757 7758 7759 7760
			return 0;
		}
		msleep(5);
	}
	return -EINVAL;
}
E
Eilon Greenstein 已提交
7761

Y
Yaniv Rosner 已提交
7762 7763 7764 7765 7766 7767
static void bnx2x_8727_power_module(struct bnx2x *bp,
				    struct bnx2x_phy *phy,
				    u8 is_power_up) {
	/* Make sure GPIOs are not using for LED mode */
	u16 val;
	/*
7768
	 * In the GPIO register, bit 4 is use to determine if the GPIOs are
Y
Yaniv Rosner 已提交
7769 7770
	 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
	 * output
7771 7772
	 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
	 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
Y
Yaniv Rosner 已提交
7773 7774
	 * where the 1st bit is the over-current(only input), and 2nd bit is
	 * for power( only output )
7775
	 *
Y
Yaniv Rosner 已提交
7776 7777 7778 7779 7780
	 * In case of NOC feature is disabled and power is up, set GPIO control
	 *  as input to enable listening of over-current indication
	 */
	if (phy->flags & FLAGS_NOC)
		return;
7781
	if (is_power_up)
Y
Yaniv Rosner 已提交
7782 7783 7784 7785 7786 7787
		val = (1<<4);
	else
		/*
		 * Set GPIO control to OUTPUT, and set the power bit
		 * to according to the is_power_up
		 */
7788
		val = (1<<1);
E
Eilon Greenstein 已提交
7789

Y
Yaniv Rosner 已提交
7790 7791 7792 7793 7794
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_8727_GPIO_CTRL,
			 val);
}
E
Eilon Greenstein 已提交
7795

Y
Yaniv Rosner 已提交
7796 7797 7798
static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
					struct bnx2x_phy *phy,
					u16 edc_mode)
Y
Yaniv Rosner 已提交
7799 7800
{
	u16 cur_limiting_mode;
E
Eilon Greenstein 已提交
7801

Y
Yaniv Rosner 已提交
7802
	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7803 7804 7805
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_ROM_VER2,
			&cur_limiting_mode);
Y
Yaniv Rosner 已提交
7806 7807 7808 7809
	DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
		 cur_limiting_mode);

	if (edc_mode == EDC_MODE_LIMITING) {
Y
Yaniv Rosner 已提交
7810
		DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
Y
Yaniv Rosner 已提交
7811
		bnx2x_cl45_write(bp, phy,
7812
				 MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
7813 7814 7815
				 MDIO_PMA_REG_ROM_VER2,
				 EDC_MODE_LIMITING);
	} else { /* LRM mode ( default )*/
E
Eilon Greenstein 已提交
7816

Y
Yaniv Rosner 已提交
7817
		DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
E
Eilon Greenstein 已提交
7818

7819 7820 7821 7822
		/*
		 * Changing to LRM mode takes quite few seconds. So do it only
		 * if current mode is limiting (default is LRM)
		 */
Y
Yaniv Rosner 已提交
7823 7824
		if (cur_limiting_mode != EDC_MODE_LIMITING)
			return 0;
E
Eilon Greenstein 已提交
7825

Y
Yaniv Rosner 已提交
7826
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7827 7828 7829
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_LRM_MODE,
				 0);
Y
Yaniv Rosner 已提交
7830
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7831 7832 7833
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_ROM_VER2,
				 0x128);
Y
Yaniv Rosner 已提交
7834
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7835 7836 7837
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_MISC_CTRL0,
				 0x4008);
Y
Yaniv Rosner 已提交
7838
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7839 7840 7841
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_LRM_MODE,
				 0xaaaa);
E
Eilon Greenstein 已提交
7842
	}
Y
Yaniv Rosner 已提交
7843
	return 0;
E
Eilon Greenstein 已提交
7844 7845
}

Y
Yaniv Rosner 已提交
7846 7847 7848
static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
					struct bnx2x_phy *phy,
					u16 edc_mode)
Y
Yaniv Rosner 已提交
7849
{
Y
Yaniv Rosner 已提交
7850 7851
	u16 phy_identifier;
	u16 rom_ver2_val;
7852
	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7853 7854 7855
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_PHY_IDENTIFIER,
			&phy_identifier);
Y
Yaniv Rosner 已提交
7856

Y
Yaniv Rosner 已提交
7857
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7858 7859 7860
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_PHY_IDENTIFIER,
			 (phy_identifier & ~(1<<9)));
Y
Yaniv Rosner 已提交
7861

7862
	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
7863 7864 7865
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_ROM_VER2,
			&rom_ver2_val);
Y
Yaniv Rosner 已提交
7866 7867
	/* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7868 7869 7870
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_ROM_VER2,
			 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
E
Eilon Greenstein 已提交
7871

Y
Yaniv Rosner 已提交
7872
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
7873 7874 7875
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_PHY_IDENTIFIER,
			 (phy_identifier | (1<<9)));
E
Eilon Greenstein 已提交
7876

Y
Yaniv Rosner 已提交
7877
	return 0;
Y
Yaniv Rosner 已提交
7878
}
Y
Yaniv Rosner 已提交
7879

Y
Yaniv Rosner 已提交
7880 7881 7882 7883 7884 7885 7886 7887
static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
				     struct link_params *params,
				     u32 action)
{
	struct bnx2x *bp = params->bp;

	switch (action) {
	case DISABLE_TX:
7888
		bnx2x_sfp_set_transmitter(params, phy, 0);
Y
Yaniv Rosner 已提交
7889 7890 7891
		break;
	case ENABLE_TX:
		if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7892
			bnx2x_sfp_set_transmitter(params, phy, 1);
Y
Yaniv Rosner 已提交
7893 7894 7895 7896 7897 7898 7899 7900
		break;
	default:
		DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
		   action);
		return;
	}
}

7901
static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7902 7903 7904 7905 7906 7907 7908 7909 7910 7911 7912 7913 7914 7915 7916 7917 7918 7919 7920 7921 7922 7923 7924 7925 7926 7927 7928 7929 7930 7931 7932
					   u8 gpio_mode)
{
	struct bnx2x *bp = params->bp;

	u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
			    offsetof(struct shmem_region,
			dev_info.port_hw_config[params->port].sfp_ctrl)) &
		PORT_HW_CFG_FAULT_MODULE_LED_MASK;
	switch (fault_led_gpio) {
	case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
		return;
	case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
	case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
	case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
	case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
	{
		u8 gpio_port = bnx2x_get_gpio_port(params);
		u16 gpio_pin = fault_led_gpio -
			PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
		DP(NETIF_MSG_LINK, "Set fault module-detected led "
				   "pin %x port %x mode %x\n",
			       gpio_pin, gpio_port, gpio_mode);
		bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
	}
	break;
	default:
		DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
			       fault_led_gpio);
	}
}

7933 7934 7935 7936 7937 7938 7939 7940 7941 7942 7943 7944 7945 7946 7947 7948 7949 7950 7951 7952 7953 7954 7955 7956 7957 7958 7959 7960 7961 7962 7963 7964 7965 7966 7967 7968 7969 7970 7971 7972 7973 7974 7975
static void bnx2x_set_e3_module_fault_led(struct link_params *params,
					  u8 gpio_mode)
{
	u32 pin_cfg;
	u8 port = params->port;
	struct bnx2x *bp = params->bp;
	pin_cfg = (REG_RD(bp, params->shmem_base +
			 offsetof(struct shmem_region,
				  dev_info.port_hw_config[port].e3_sfp_ctrl)) &
		PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
		PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
	DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
		       gpio_mode, pin_cfg);
	bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
}

static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
					   u8 gpio_mode)
{
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
	if (CHIP_IS_E3(bp)) {
		/*
		 * Low ==> if SFP+ module is supported otherwise
		 * High ==> if SFP+ module is not on the approved vendor list
		 */
		bnx2x_set_e3_module_fault_led(params, gpio_mode);
	} else
		bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
}

static void bnx2x_warpcore_power_module(struct link_params *params,
					struct bnx2x_phy *phy,
					u8 power)
{
	u32 pin_cfg;
	struct bnx2x *bp = params->bp;

	pin_cfg = (REG_RD(bp, params->shmem_base +
			  offsetof(struct shmem_region,
			dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
			PORT_HW_CFG_E3_PWR_DIS_MASK) >>
			PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7976 7977 7978

	if (pin_cfg == PIN_CFG_NA)
		return;
7979 7980 7981 7982 7983 7984 7985 7986 7987
	DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
		       power, pin_cfg);
	/*
	 * Low ==> corresponding SFP+ module is powered
	 * high ==> the SFP+ module is powered down
	 */
	bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
}

7988 7989 7990 7991 7992 7993
static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
				    struct link_params *params)
{
	bnx2x_warpcore_power_module(params, phy, 0);
}

Y
Yaniv Rosner 已提交
7994 7995 7996 7997 7998 7999 8000 8001 8002 8003 8004 8005
static void bnx2x_power_sfp_module(struct link_params *params,
				   struct bnx2x_phy *phy,
				   u8 power)
{
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);

	switch (phy->type) {
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
		bnx2x_8727_power_module(params->bp, phy, power);
		break;
8006 8007 8008 8009 8010 8011 8012 8013 8014 8015 8016 8017 8018 8019 8020 8021 8022 8023 8024 8025 8026 8027 8028 8029 8030 8031 8032 8033 8034
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
		bnx2x_warpcore_power_module(params, phy, power);
		break;
	default:
		break;
	}
}
static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
					     struct bnx2x_phy *phy,
					     u16 edc_mode)
{
	u16 val = 0;
	u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
	struct bnx2x *bp = params->bp;

	u8 lane = bnx2x_get_warpcore_lane(phy, params);
	/* This is a global register which controls all lanes */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
	val &= ~(0xf << (lane << 2));

	switch (edc_mode) {
	case EDC_MODE_LINEAR:
	case EDC_MODE_LIMITING:
		mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
		break;
	case EDC_MODE_PASSIVE_DAC:
		mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
		break;
Y
Yaniv Rosner 已提交
8035 8036 8037
	default:
		break;
	}
8038 8039 8040 8041 8042 8043 8044 8045

	val |= (mode << (lane << 2));
	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
			 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
	/* A must read */
	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
			MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);

8046 8047 8048
	/* Restart microcode to re-read the new mode */
	bnx2x_warpcore_reset_lane(bp, phy, 1);
	bnx2x_warpcore_reset_lane(bp, phy, 0);
8049

Y
Yaniv Rosner 已提交
8050 8051 8052 8053 8054 8055 8056 8057 8058 8059 8060 8061 8062 8063
}

static void bnx2x_set_limiting_mode(struct link_params *params,
				    struct bnx2x_phy *phy,
				    u16 edc_mode)
{
	switch (phy->type) {
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
		bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
		break;
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
		bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
		break;
8064 8065 8066
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
		bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
		break;
Y
Yaniv Rosner 已提交
8067 8068 8069
	}
}

Y
Yaniv Rosner 已提交
8070 8071
int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
			       struct link_params *params)
Y
Yaniv Rosner 已提交
8072 8073
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
8074
	u16 edc_mode;
Y
Yaniv Rosner 已提交
8075
	int rc = 0;
Y
Yaniv Rosner 已提交
8076

Y
Yaniv Rosner 已提交
8077 8078 8079
	u32 val = REG_RD(bp, params->shmem_base +
			     offsetof(struct shmem_region, dev_info.
				     port_feature_config[params->port].config));
8080

Y
Yaniv Rosner 已提交
8081 8082
	DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
		 params->port);
Y
Yaniv Rosner 已提交
8083 8084
	/* Power up module */
	bnx2x_power_sfp_module(params, phy, 1);
Y
Yaniv Rosner 已提交
8085 8086 8087
	if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
		DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
		return -EINVAL;
Y
Yaniv Rosner 已提交
8088
	} else if (bnx2x_verify_sfp_module(phy, params) != 0) {
Y
Yaniv Rosner 已提交
8089 8090 8091 8092
		/* check SFP+ module compatibility */
		DP(NETIF_MSG_LINK, "Module verification failed!!\n");
		rc = -EINVAL;
		/* Turn on fault module-detected led */
8093 8094 8095
		bnx2x_set_sfp_module_fault_led(params,
					       MISC_REGISTERS_GPIO_HIGH);

Y
Yaniv Rosner 已提交
8096 8097 8098
		/* Check if need to power down the SFP+ module */
		if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
		     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
Y
Yaniv Rosner 已提交
8099
			DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
Y
Yaniv Rosner 已提交
8100
			bnx2x_power_sfp_module(params, phy, 0);
Y
Yaniv Rosner 已提交
8101 8102 8103 8104
			return rc;
		}
	} else {
		/* Turn off fault module-detected led */
8105
		bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8106
	}
Y
Yaniv Rosner 已提交
8107

8108 8109 8110 8111
	/*
	 * Check and set limiting mode / LRM mode on 8726. On 8727 it
	 * is done automatically
	 */
Y
Yaniv Rosner 已提交
8112 8113
	bnx2x_set_limiting_mode(params, phy, edc_mode);

Y
Yaniv Rosner 已提交
8114 8115 8116 8117 8118 8119 8120
	/*
	 * Enable transmit for this module if the module is approved, or
	 * if unapproved modules should also enable the Tx laser
	 */
	if (rc == 0 ||
	    (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
	    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8121
		bnx2x_sfp_set_transmitter(params, phy, 1);
Y
Yaniv Rosner 已提交
8122
	else
8123
		bnx2x_sfp_set_transmitter(params, phy, 0);
Y
Yaniv Rosner 已提交
8124

Y
Yaniv Rosner 已提交
8125 8126 8127 8128
	return rc;
}

void bnx2x_handle_module_detect_int(struct link_params *params)
Y
Yaniv Rosner 已提交
8129 8130
{
	struct bnx2x *bp = params->bp;
8131
	struct bnx2x_phy *phy;
Y
Yaniv Rosner 已提交
8132
	u32 gpio_val;
8133 8134 8135 8136 8137 8138 8139 8140 8141 8142 8143 8144
	u8 gpio_num, gpio_port;
	if (CHIP_IS_E3(bp))
		phy = &params->phy[INT_PHY];
	else
		phy = &params->phy[EXT_PHY1];

	if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
				      params->port, &gpio_num, &gpio_port) ==
	    -EINVAL) {
		DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
		return;
	}
E
Eilon Greenstein 已提交
8145

Y
Yaniv Rosner 已提交
8146
	/* Set valid module led off */
8147
	bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
E
Eilon Greenstein 已提交
8148

8149
	/* Get current gpio val reflecting module plugged in / out*/
8150
	gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8151

Y
Yaniv Rosner 已提交
8152 8153
	/* Call the handling function in case module is detected */
	if (gpio_val == 0) {
Y
Yaniv Rosner 已提交
8154
		bnx2x_power_sfp_module(params, phy, 1);
8155
		bnx2x_set_gpio_int(bp, gpio_num,
Y
Yaniv Rosner 已提交
8156
				   MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8157
				   gpio_port);
Y
Yaniv Rosner 已提交
8158 8159 8160 8161 8162 8163
		if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
			bnx2x_sfp_module_detection(phy, params);
		else
			DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
	} else {
		u32 val = REG_RD(bp, params->shmem_base +
Y
Yaniv Rosner 已提交
8164 8165 8166
				 offsetof(struct shmem_region, dev_info.
					  port_feature_config[params->port].
					  config));
8167
		bnx2x_set_gpio_int(bp, gpio_num,
Y
Yaniv Rosner 已提交
8168
				   MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8169
				   gpio_port);
8170 8171 8172 8173
		/*
		 * Module was plugged out.
		 * Disable transmit for this module
		 */
Y
Yaniv Rosner 已提交
8174
		phy->media_type = ETH_PHY_NOT_PRESENT;
Y
Yaniv Rosner 已提交
8175 8176 8177
		if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
		     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
		    CHIP_IS_E3(bp))
8178
			bnx2x_sfp_set_transmitter(params, phy, 0);
8179
	}
Y
Yaniv Rosner 已提交
8180
}
8181

8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 8202 8203 8204
/******************************************************************/
/*		Used by 8706 and 8727                             */
/******************************************************************/
static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
				 struct bnx2x_phy *phy,
				 u16 alarm_status_offset,
				 u16 alarm_ctrl_offset)
{
	u16 alarm_status, val;
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, alarm_status_offset,
			&alarm_status);
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, alarm_status_offset,
			&alarm_status);
	/* Mask or enable the fault event. */
	bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
	if (alarm_status & (1<<0))
		val &= ~(1<<0);
	else
		val |= (1<<0);
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
}
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8205 8206 8207 8208 8209 8210 8211 8212 8213 8214 8215 8216
/******************************************************************/
/*		common BCM8706/BCM8726 PHY SECTION		  */
/******************************************************************/
static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
				      struct link_params *params,
				      struct link_vars *vars)
{
	u8 link_up = 0;
	u16 val1, val2, rx_sd, pcs_status;
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
	/* Clear RX Alarm*/
8217
	bnx2x_cl45_read(bp, phy,
8218
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8219

8220 8221
	bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
			     MDIO_PMA_LASI_TXCTRL);
8222

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8223 8224
	/* clear LASI indication*/
	bnx2x_cl45_read(bp, phy,
8225
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
Y
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8226
	bnx2x_cl45_read(bp, phy,
8227
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
Y
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8228
	DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8229 8230

	bnx2x_cl45_read(bp, phy,
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8231 8232 8233 8234 8235 8236 8237
			MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
	bnx2x_cl45_read(bp, phy,
			MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8238

Y
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8239 8240
	DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
			" link_status 0x%x\n", rx_sd, pcs_status, val2);
8241 8242 8243
	/*
	 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
	 * are set, or if the autoneg bit 1 is set
Y
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8244 8245 8246 8247 8248 8249 8250
	 */
	link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
	if (link_up) {
		if (val2 & (1<<1))
			vars->line_speed = SPEED_1000;
		else
			vars->line_speed = SPEED_10000;
8251
		bnx2x_ext_phy_resolve_fc(phy, params, vars);
8252
		vars->duplex = DUPLEX_FULL;
Y
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8253
	}
8254 8255 8256 8257

	/* Capture 10G link fault. Read twice to clear stale value. */
	if (vars->line_speed == SPEED_10000) {
		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8258
			    MDIO_PMA_LASI_TXSTAT, &val1);
8259
		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8260
			    MDIO_PMA_LASI_TXSTAT, &val1);
8261 8262 8263 8264
		if (val1 & (1<<0))
			vars->fault_detected = 1;
	}

8265
	return link_up;
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8266
}
8267

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8268 8269 8270 8271
/******************************************************************/
/*			BCM8706 PHY SECTION			  */
/******************************************************************/
static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
Y
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8272 8273 8274
				 struct link_params *params,
				 struct link_vars *vars)
{
8275 8276
	u32 tx_en_mode;
	u16 cnt, val, tmp1;
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8277
	struct bnx2x *bp = params->bp;
8278

Y
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8279
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Y
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8280
		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
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8281 8282 8283
	/* HW reset */
	bnx2x_ext_phy_hw_reset(bp, params->port);
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8284
	bnx2x_wait_reset_complete(bp, phy, params);
Y
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8285

Y
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8286 8287 8288 8289 8290 8291 8292 8293 8294 8295 8296 8297 8298 8299 8300 8301 8302 8303 8304 8305 8306 8307 8308 8309 8310 8311 8312 8313 8314 8315
	/* Wait until fw is loaded */
	for (cnt = 0; cnt < 100; cnt++) {
		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
		if (val)
			break;
		msleep(10);
	}
	DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
	if ((params->feature_config_flags &
	     FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
		u8 i;
		u16 reg;
		for (i = 0; i < 4; i++) {
			reg = MDIO_XS_8706_REG_BANK_RX0 +
				i*(MDIO_XS_8706_REG_BANK_RX1 -
				   MDIO_XS_8706_REG_BANK_RX0);
			bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
			/* Clear first 3 bits of the control */
			val &= ~0x7;
			/* Set control bits according to configuration */
			val |= (phy->rx_preemphasis[i] & 0x7);
			DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
				   " reg 0x%x <-- val 0x%x\n", reg, val);
			bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
		}
	}
	/* Force speed */
	if (phy->req_line_speed == SPEED_10000) {
		DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
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8316

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8317 8318 8319 8320
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
		bnx2x_cl45_write(bp, phy,
8321
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8322 8323 8324
				 0);
		/* Arm LASI for link and Tx fault. */
		bnx2x_cl45_write(bp, phy,
8325
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
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8326
	} else {
L
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8327
		/* Force 1Gbps using autoneg with 1G advertisement */
Y
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8328

Y
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8329 8330 8331 8332
		/* Allow CL37 through CL73 */
		DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
Y
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8333

L
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8334
		/* Enable Full-Duplex advertisement on CL37 */
Y
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8335 8336 8337 8338 8339 8340 8341 8342
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
		/* Enable CL37 AN */
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
		/* 1G support */
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
Y
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8343

Y
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8344 8345 8346 8347
		/* Enable clause 73 AN */
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
		bnx2x_cl45_write(bp, phy,
8348
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
Y
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8349 8350
				 0x0400);
		bnx2x_cl45_write(bp, phy,
8351
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
Y
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8352 8353 8354
				 0x0004);
	}
	bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8355 8356 8357 8358 8359 8360 8361 8362 8363 8364 8365 8366 8367 8368 8369 8370 8371 8372 8373 8374

	/*
	 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
	 * power mode, if TX Laser is disabled
	 */

	tx_en_mode = REG_RD(bp, params->shmem_base +
			    offsetof(struct shmem_region,
				dev_info.port_hw_config[params->port].sfp_ctrl))
			& PORT_HW_CFG_TX_LASER_MASK;

	if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
		DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
		bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
		tmp1 |= 0x1;
		bnx2x_cl45_write(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
	}

Y
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8375 8376
	return 0;
}
Y
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8377

Y
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8378 8379 8380
static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
				  struct link_params *params,
				  struct link_vars *vars)
Y
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8381 8382 8383
{
	return bnx2x_8706_8726_read_status(phy, params, vars);
}
Y
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8384

Y
Yaniv Rosner 已提交
8385 8386 8387 8388 8389 8390 8391 8392 8393 8394
/******************************************************************/
/*			BCM8726 PHY SECTION			  */
/******************************************************************/
static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
				       struct link_params *params)
{
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
}
8395

Y
Yaniv Rosner 已提交
8396 8397 8398 8399 8400 8401
static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
					 struct link_params *params)
{
	struct bnx2x *bp = params->bp;
	/* Need to wait 100ms after reset */
	msleep(100);
8402

Y
Yaniv Rosner 已提交
8403 8404 8405
	/* Micro controller re-boot */
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8406

Y
Yaniv Rosner 已提交
8407 8408
	/* Set soft reset */
	bnx2x_cl45_write(bp, phy,
Y
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8409 8410 8411
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_GEN_CTRL,
			 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8412

Y
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8413
	bnx2x_cl45_write(bp, phy,
Y
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8414 8415
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
Y
Yaniv Rosner 已提交
8416

Y
Yaniv Rosner 已提交
8417
	bnx2x_cl45_write(bp, phy,
Y
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8418 8419 8420
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_GEN_CTRL,
			 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
Y
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8421 8422 8423 8424 8425 8426

	/* wait for 150ms for microcode load */
	msleep(150);

	/* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
	bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
8427 8428
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
Y
Yaniv Rosner 已提交
8429 8430 8431

	msleep(200);
	bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
Y
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8432 8433
}

Y
Yaniv Rosner 已提交
8434
static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
Y
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8435 8436 8437 8438
				 struct link_params *params,
				 struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
Y
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8439 8440
	u16 val1;
	u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8441 8442
	if (link_up) {
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
8443 8444 8445 8446 8447 8448 8449
				MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
				&val1);
		if (val1 & (1<<15)) {
			DP(NETIF_MSG_LINK, "Tx is disabled\n");
			link_up = 0;
			vars->line_speed = 0;
		}
8450 8451
	}
	return link_up;
Y
Yaniv Rosner 已提交
8452 8453
}

Y
Yaniv Rosner 已提交
8454

Y
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8455 8456 8457
static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
				  struct link_params *params,
				  struct link_vars *vars)
Y
Yaniv Rosner 已提交
8458 8459
{
	struct bnx2x *bp = params->bp;
Y
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8460
	DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8461

Y
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8462
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8463
	bnx2x_wait_reset_complete(bp, phy, params);
8464

Y
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8465
	bnx2x_8726_external_rom_boot(phy, params);
8466

8467 8468 8469 8470 8471 8472
	/*
	 * Need to call module detected on initialization since the module
	 * detection triggered by actual module insertion might occur before
	 * driver is loaded, and when driver is loaded, it reset all
	 * registers, including the transmitter
	 */
Y
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8473
	bnx2x_sfp_module_detection(phy, params);
8474

Y
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8475 8476 8477 8478 8479 8480 8481
	if (phy->req_line_speed == SPEED_1000) {
		DP(NETIF_MSG_LINK, "Setting 1G force\n");
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
		bnx2x_cl45_write(bp, phy,
8482
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
Y
Yaniv Rosner 已提交
8483
		bnx2x_cl45_write(bp, phy,
8484
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
Y
Yaniv Rosner 已提交
8485 8486 8487 8488 8489 8490 8491 8492 8493 8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504
				 0x400);
	} else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
		   (phy->speed_cap_mask &
		      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
		   ((phy->speed_cap_mask &
		      PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
		    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
		DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
		/* Set Flow control */
		bnx2x_ext_phy_set_pause(params, phy, vars);
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
		bnx2x_cl45_write(bp, phy,
				MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8505 8506 8507 8508
		/*
		 * Enable RX-ALARM control to receive interrupt for 1G speed
		 * change
		 */
Y
Yaniv Rosner 已提交
8509
		bnx2x_cl45_write(bp, phy,
8510
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
Y
Yaniv Rosner 已提交
8511
		bnx2x_cl45_write(bp, phy,
8512
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
Y
Yaniv Rosner 已提交
8513
				 0x400);
8514

Y
Yaniv Rosner 已提交
8515 8516
	} else { /* Default 10G. Set only LASI control */
		bnx2x_cl45_write(bp, phy,
8517
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8518 8519
	}

Y
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8520 8521 8522
	/* Set TX PreEmphasis if needed */
	if ((params->feature_config_flags &
	     FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8523 8524
		DP(NETIF_MSG_LINK,
		   "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
Y
Yaniv Rosner 已提交
8525 8526 8527 8528 8529 8530
			 phy->tx_preemphasis[0],
			 phy->tx_preemphasis[1]);
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_8726_TX_CTRL1,
				 phy->tx_preemphasis[0]);
8531

Y
Yaniv Rosner 已提交
8532 8533 8534 8535 8536
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_8726_TX_CTRL2,
				 phy->tx_preemphasis[1]);
	}
8537

Y
Yaniv Rosner 已提交
8538
	return 0;
8539

Y
Yaniv Rosner 已提交
8540 8541
}

Y
Yaniv Rosner 已提交
8542 8543
static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
				  struct link_params *params)
8544
{
Y
Yaniv Rosner 已提交
8545 8546 8547 8548 8549 8550 8551 8552 8553 8554 8555
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
	/* Set serial boot control for external load */
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_GEN_CTRL, 0x0001);
}

/******************************************************************/
/*			BCM8727 PHY SECTION			  */
/******************************************************************/
8556 8557 8558 8559 8560 8561 8562 8563 8564 8565 8566 8567 8568 8569 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 8590 8591 8592 8593 8594 8595 8596 8597 8598 8599 8600 8601 8602

static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
				    struct link_params *params, u8 mode)
{
	struct bnx2x *bp = params->bp;
	u16 led_mode_bitmask = 0;
	u16 gpio_pins_bitmask = 0;
	u16 val;
	/* Only NOC flavor requires to set the LED specifically */
	if (!(phy->flags & FLAGS_NOC))
		return;
	switch (mode) {
	case LED_MODE_FRONT_PANEL_OFF:
	case LED_MODE_OFF:
		led_mode_bitmask = 0;
		gpio_pins_bitmask = 0x03;
		break;
	case LED_MODE_ON:
		led_mode_bitmask = 0;
		gpio_pins_bitmask = 0x02;
		break;
	case LED_MODE_OPER:
		led_mode_bitmask = 0x60;
		gpio_pins_bitmask = 0x11;
		break;
	}
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_8727_PCS_OPT_CTRL,
			&val);
	val &= 0xff8f;
	val |= led_mode_bitmask;
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
			 val);
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_8727_GPIO_CTRL,
			&val);
	val &= 0xffe0;
	val |= gpio_pins_bitmask;
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_8727_GPIO_CTRL,
			 val);
}
Y
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8603 8604 8605 8606
static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
				struct link_params *params) {
	u32 swap_val, swap_override;
	u8 port;
8607
	/*
Y
Yaniv Rosner 已提交
8608 8609
	 * The PHY reset is controlled by GPIO 1. Fake the port number
	 * to cancel the swap done in set_gpio()
8610
	 */
Y
Yaniv Rosner 已提交
8611 8612 8613 8614 8615
	struct bnx2x *bp = params->bp;
	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
	port = (swap_val && swap_override) ^ 1;
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
Y
Yaniv Rosner 已提交
8616
		       MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8617
}
Y
Yaniv Rosner 已提交
8618

Y
Yaniv Rosner 已提交
8619 8620 8621
static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
				  struct link_params *params,
				  struct link_vars *vars)
Y
Yaniv Rosner 已提交
8622
{
8623 8624
	u32 tx_en_mode;
	u16 tmp1, val, mod_abs, tmp2;
Y
Yaniv Rosner 已提交
8625 8626
	u16 rx_alarm_ctrl_val;
	u16 lasi_ctrl_val;
Y
Yaniv Rosner 已提交
8627
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
8628
	/* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
Y
Yaniv Rosner 已提交
8629

8630
	bnx2x_wait_reset_complete(bp, phy, params);
Y
Yaniv Rosner 已提交
8631
	rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8632 8633
	/* Should be 0x6 to enable XS on Tx side. */
	lasi_ctrl_val = 0x0006;
Y
Yaniv Rosner 已提交
8634

Y
Yaniv Rosner 已提交
8635 8636 8637
	DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
	/* enable LASI */
	bnx2x_cl45_write(bp, phy,
8638
			 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
Y
Yaniv Rosner 已提交
8639
			 rx_alarm_ctrl_val);
8640
	bnx2x_cl45_write(bp, phy,
8641
			 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8642
			 0);
Y
Yaniv Rosner 已提交
8643
	bnx2x_cl45_write(bp, phy,
8644
			 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
Y
Yaniv Rosner 已提交
8645

8646 8647 8648 8649
	/*
	 * Initially configure MOD_ABS to interrupt when module is
	 * presence( bit 8)
	 */
Y
Yaniv Rosner 已提交
8650 8651
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8652 8653 8654 8655 8656
	/*
	 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
	 * When the EDC is off it locks onto a reference clock and avoids
	 * becoming 'lost'
	 */
8657 8658 8659
	mod_abs &= ~(1<<8);
	if (!(phy->flags & FLAGS_NOC))
		mod_abs &= ~(1<<9);
Y
Yaniv Rosner 已提交
8660 8661
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
Y
Yaniv Rosner 已提交
8662 8663


8664 8665 8666
	/* Enable/Disable PHY transmitter output */
	bnx2x_set_disable_pmd_transmit(params, phy, 0);

Y
Yaniv Rosner 已提交
8667 8668 8669 8670
	/* Make MOD_ABS give interrupt on change */
	bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
			&val);
	val |= (1<<12);
8671 8672
	if (phy->flags & FLAGS_NOC)
		val |= (3<<5);
Y
Yaniv Rosner 已提交
8673

8674
	/*
8675 8676 8677 8678 8679
	 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
	 * status which reflect SFP+ module over-current
	 */
	if (!(phy->flags & FLAGS_NOC))
		val &= 0xff8f; /* Reset bits 4-6 */
Y
Yaniv Rosner 已提交
8680 8681
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
Y
Yaniv Rosner 已提交
8682

Y
Yaniv Rosner 已提交
8683 8684 8685 8686 8687 8688
	bnx2x_8727_power_module(bp, phy, 1);

	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);

	bnx2x_cl45_read(bp, phy,
8689
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
Y
Yaniv Rosner 已提交
8690 8691 8692 8693 8694 8695 8696 8697 8698 8699 8700

	/* Set option 1G speed */
	if (phy->req_line_speed == SPEED_1000) {
		DP(NETIF_MSG_LINK, "Setting 1G force\n");
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
		DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8701
		/*
Y
Yaniv Rosner 已提交
8702 8703 8704 8705 8706 8707 8708 8709 8710 8711 8712 8713
		 * Power down the XAUI until link is up in case of dual-media
		 * and 1G
		 */
		if (DUAL_MEDIA(params)) {
			bnx2x_cl45_read(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_8727_PCS_GP, &val);
			val |= (3<<10);
			bnx2x_cl45_write(bp, phy,
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8727_PCS_GP, val);
		}
Y
Yaniv Rosner 已提交
8714 8715 8716 8717 8718 8719 8720 8721 8722 8723 8724 8725 8726
	} else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
		   ((phy->speed_cap_mask &
		     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
		   ((phy->speed_cap_mask &
		      PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
		   PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {

		DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
	} else {
8727
		/*
Y
Yaniv Rosner 已提交
8728 8729 8730 8731 8732 8733 8734 8735 8736 8737 8738 8739 8740
		 * Since the 8727 has only single reset pin, need to set the 10G
		 * registers although it is default
		 */
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
				 0x0020);
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
				 0x0008);
Y
Yaniv Rosner 已提交
8741 8742
	}

8743 8744
	/*
	 * Set 2-wire transfer rate of SFP+ module EEPROM
Y
Yaniv Rosner 已提交
8745 8746 8747 8748 8749 8750
	 * to 100Khz since some DACs(direct attached cables) do
	 * not work at 400Khz.
	 */
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
			 0xa001);
Y
Yaniv Rosner 已提交
8751

Y
Yaniv Rosner 已提交
8752 8753 8754 8755 8756 8757 8758 8759 8760
	/* Set TX PreEmphasis if needed */
	if ((params->feature_config_flags &
	     FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
		DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
			   phy->tx_preemphasis[0],
			   phy->tx_preemphasis[1]);
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
				 phy->tx_preemphasis[0]);
Y
Yaniv Rosner 已提交
8761

Y
Yaniv Rosner 已提交
8762 8763 8764 8765
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
				 phy->tx_preemphasis[1]);
	}
Y
Yaniv Rosner 已提交
8766

8767 8768 8769 8770 8771 8772 8773 8774 8775 8776 8777 8778 8779 8780 8781 8782 8783 8784 8785 8786
	/*
	 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
	 * power mode, if TX Laser is disabled
	 */
	tx_en_mode = REG_RD(bp, params->shmem_base +
			    offsetof(struct shmem_region,
				dev_info.port_hw_config[params->port].sfp_ctrl))
			& PORT_HW_CFG_TX_LASER_MASK;

	if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {

		DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
		bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
		tmp2 |= 0x1000;
		tmp2 &= 0xFFEF;
		bnx2x_cl45_write(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
	}

Y
Yaniv Rosner 已提交
8787
	return 0;
Y
Yaniv Rosner 已提交
8788 8789
}

Y
Yaniv Rosner 已提交
8790 8791
static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
				      struct link_params *params)
Y
Yaniv Rosner 已提交
8792 8793
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
8794 8795 8796 8797 8798 8799
	u16 mod_abs, rx_alarm_status;
	u32 val = REG_RD(bp, params->shmem_base +
			     offsetof(struct shmem_region, dev_info.
				      port_feature_config[params->port].
				      config));
	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
8800 8801
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
Y
Yaniv Rosner 已提交
8802
	if (mod_abs & (1<<8)) {
Y
Yaniv Rosner 已提交
8803

Y
Yaniv Rosner 已提交
8804
		/* Module is absent */
8805 8806
		DP(NETIF_MSG_LINK,
		   "MOD_ABS indication show module is absent\n");
Y
Yaniv Rosner 已提交
8807
		phy->media_type = ETH_PHY_NOT_PRESENT;
8808 8809 8810 8811 8812 8813 8814 8815
		/*
		 * 1. Set mod_abs to detect next module
		 *    presence event
		 * 2. Set EDC off by setting OPTXLOS signal input to low
		 *    (bit 9).
		 *    When the EDC is off it locks onto a reference clock and
		 *    avoids becoming 'lost'.
		 */
8816 8817 8818
		mod_abs &= ~(1<<8);
		if (!(phy->flags & FLAGS_NOC))
			mod_abs &= ~(1<<9);
Y
Yaniv Rosner 已提交
8819
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
8820 8821
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
Y
Yaniv Rosner 已提交
8822

8823 8824 8825 8826
		/*
		 * Clear RX alarm since it stays up as long as
		 * the mod_abs wasn't changed
		 */
Y
Yaniv Rosner 已提交
8827
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
8828
				MDIO_PMA_DEVAD,
8829
				MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
Y
Yaniv Rosner 已提交
8830

Y
Yaniv Rosner 已提交
8831 8832
	} else {
		/* Module is present */
8833 8834
		DP(NETIF_MSG_LINK,
		   "MOD_ABS indication show module is present\n");
8835 8836 8837 8838 8839 8840 8841 8842
		/*
		 * First disable transmitter, and if the module is ok, the
		 * module_detection will enable it
		 * 1. Set mod_abs to detect next module absent event ( bit 8)
		 * 2. Restore the default polarity of the OPRXLOS signal and
		 * this signal will then correctly indicate the presence or
		 * absence of the Rx signal. (bit 9)
		 */
8843 8844 8845
		mod_abs |= (1<<8);
		if (!(phy->flags & FLAGS_NOC))
			mod_abs |= (1<<9);
Y
Yaniv Rosner 已提交
8846
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
8847 8848
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
Y
Yaniv Rosner 已提交
8849

8850 8851 8852 8853 8854 8855
		/*
		 * Clear RX alarm since it stays up as long as the mod_abs
		 * wasn't changed. This is need to be done before calling the
		 * module detection, otherwise it will clear* the link update
		 * alarm
		 */
Y
Yaniv Rosner 已提交
8856 8857
		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD,
8858
				MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
Y
Yaniv Rosner 已提交
8859 8860


Y
Yaniv Rosner 已提交
8861 8862
		if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
		    PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8863
			bnx2x_sfp_set_transmitter(params, phy, 0);
Y
Yaniv Rosner 已提交
8864 8865 8866 8867 8868

		if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
			bnx2x_sfp_module_detection(phy, params);
		else
			DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
Y
Yaniv Rosner 已提交
8869
	}
Y
Yaniv Rosner 已提交
8870 8871

	DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8872 8873
		   rx_alarm_status);
	/* No need to check link status in case of module plugged in/out */
Y
Yaniv Rosner 已提交
8874 8875
}

Y
Yaniv Rosner 已提交
8876 8877 8878 8879
static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
				 struct link_params *params,
				 struct link_vars *vars)

Y
Yaniv Rosner 已提交
8880 8881
{
	struct bnx2x *bp = params->bp;
8882
	u8 link_up = 0, oc_port = params->port;
Y
Yaniv Rosner 已提交
8883
	u16 link_status = 0;
Y
Yaniv Rosner 已提交
8884 8885 8886 8887
	u16 rx_alarm_status, lasi_ctrl, val1;

	/* If PHY is not initialized, do not check link status */
	bnx2x_cl45_read(bp, phy,
8888
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
Y
Yaniv Rosner 已提交
8889 8890 8891 8892
			&lasi_ctrl);
	if (!lasi_ctrl)
		return 0;

8893
	/* Check the LASI on Rx */
Y
Yaniv Rosner 已提交
8894
	bnx2x_cl45_read(bp, phy,
8895
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
Y
Yaniv Rosner 已提交
8896 8897 8898 8899
			&rx_alarm_status);
	vars->line_speed = 0;
	DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);

8900 8901
	bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
			     MDIO_PMA_LASI_TXCTRL);
8902

Y
Yaniv Rosner 已提交
8903
	bnx2x_cl45_read(bp, phy,
8904
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
Y
Yaniv Rosner 已提交
8905 8906 8907 8908 8909 8910 8911

	DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);

	/* Clear MSG-OUT */
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);

8912
	/*
Y
Yaniv Rosner 已提交
8913 8914 8915 8916 8917 8918 8919 8920 8921 8922
	 * If a module is present and there is need to check
	 * for over current
	 */
	if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
		/* Check over-current using 8727 GPIO0 input*/
		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
				&val1);

		if ((val1 & (1<<8)) == 0) {
8923 8924
			if (!CHIP_IS_E1x(bp))
				oc_port = BP_PATH(bp) + (params->port << 1);
8925 8926 8927
			DP(NETIF_MSG_LINK,
			   "8727 Power fault has been detected on port %d\n",
			   oc_port);
Y
Yaniv Rosner 已提交
8928 8929 8930 8931 8932 8933 8934
			netdev_err(bp->dev, "Error:  Power fault on Port %d has"
					    " been detected and the power to "
					    "that SFP+ module has been removed"
					    " to prevent failure of the card."
					    " Please remove the SFP+ module and"
					    " restart the system to clear this"
					    " error.\n",
8935
			 oc_port);
8936
			/* Disable all RX_ALARMs except for mod_abs */
Y
Yaniv Rosner 已提交
8937 8938
			bnx2x_cl45_write(bp, phy,
					 MDIO_PMA_DEVAD,
8939
					 MDIO_PMA_LASI_RXCTRL, (1<<5));
Y
Yaniv Rosner 已提交
8940 8941 8942 8943 8944 8945 8946 8947 8948 8949 8950 8951

			bnx2x_cl45_read(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
			/* Wait for module_absent_event */
			val1 |= (1<<8);
			bnx2x_cl45_write(bp, phy,
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
			/* Clear RX alarm */
			bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD,
8952
				MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
Y
Yaniv Rosner 已提交
8953 8954 8955 8956 8957 8958 8959 8960 8961
			return 0;
		}
	} /* Over current check */

	/* When module absent bit is set, check module */
	if (rx_alarm_status & (1<<5)) {
		bnx2x_8727_handle_mod_abs(phy, params);
		/* Enable all mod_abs and link detection bits */
		bnx2x_cl45_write(bp, phy,
8962
				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
Y
Yaniv Rosner 已提交
8963 8964
				 ((1<<5) | (1<<2)));
	}
Y
Yaniv Rosner 已提交
8965 8966
	DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
	bnx2x_8727_specific_func(phy, params, ENABLE_TX);
Y
Yaniv Rosner 已提交
8967 8968 8969 8970 8971 8972 8973 8974 8975 8976 8977 8978
	/* If transmitter is disabled, ignore false link up indication */
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
	if (val1 & (1<<15)) {
		DP(NETIF_MSG_LINK, "Tx is disabled\n");
		return 0;
	}

	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);

8979 8980 8981 8982
	/*
	 * Bits 0..2 --> speed detected,
	 * Bits 13..15--> link is down
	 */
Y
Yaniv Rosner 已提交
8983 8984 8985
	if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
		link_up = 1;
		vars->line_speed = SPEED_10000;
8986 8987
		DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
			   params->port);
Y
Yaniv Rosner 已提交
8988 8989 8990 8991 8992 8993 8994 8995 8996 8997
	} else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
		link_up = 1;
		vars->line_speed = SPEED_1000;
		DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
			   params->port);
	} else {
		link_up = 0;
		DP(NETIF_MSG_LINK, "port %x: External link is down\n",
			   params->port);
	}
8998 8999 9000 9001

	/* Capture 10G link fault. */
	if (vars->line_speed == SPEED_10000) {
		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9002
			    MDIO_PMA_LASI_TXSTAT, &val1);
9003 9004

		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9005
			    MDIO_PMA_LASI_TXSTAT, &val1);
9006 9007 9008 9009 9010 9011

		if (val1 & (1<<0)) {
			vars->fault_detected = 1;
		}
	}

9012
	if (link_up) {
Y
Yaniv Rosner 已提交
9013
		bnx2x_ext_phy_resolve_fc(phy, params, vars);
9014 9015 9016
		vars->duplex = DUPLEX_FULL;
		DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
	}
Y
Yaniv Rosner 已提交
9017 9018 9019 9020 9021 9022

	if ((DUAL_MEDIA(params)) &&
	    (phy->req_line_speed == SPEED_1000)) {
		bnx2x_cl45_read(bp, phy,
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_8727_PCS_GP, &val1);
9023
		/*
Y
Yaniv Rosner 已提交
9024 9025 9026 9027 9028 9029 9030 9031 9032 9033 9034
		 * In case of dual-media board and 1G, power up the XAUI side,
		 * otherwise power it down. For 10G it is done automatically
		 */
		if (link_up)
			val1 &= ~(3<<10);
		else
			val1 |= (3<<10);
		bnx2x_cl45_write(bp, phy,
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_8727_PCS_GP, val1);
	}
Y
Yaniv Rosner 已提交
9035
	return link_up;
Y
Yaniv Rosner 已提交
9036
}
Y
Yaniv Rosner 已提交
9037

Y
Yaniv Rosner 已提交
9038 9039
static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
				  struct link_params *params)
Y
Yaniv Rosner 已提交
9040 9041
{
	struct bnx2x *bp = params->bp;
9042 9043 9044 9045

	/* Enable/Disable PHY transmitter output */
	bnx2x_set_disable_pmd_transmit(params, phy, 1);

Y
Yaniv Rosner 已提交
9046
	/* Disable Transmitter */
9047
	bnx2x_sfp_set_transmitter(params, phy, 0);
Y
Yaniv Rosner 已提交
9048
	/* Clear LASI */
9049
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
Y
Yaniv Rosner 已提交
9050

Y
Yaniv Rosner 已提交
9051
}
9052

Y
Yaniv Rosner 已提交
9053 9054 9055 9056 9057
/******************************************************************/
/*		BCM8481/BCM84823/BCM84833 PHY SECTION	          */
/******************************************************************/
static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
					   struct link_params *params)
Y
Yaniv Rosner 已提交
9058
{
Y
Yaniv Rosner 已提交
9059 9060
	u16 val, fw_ver1, fw_ver2, cnt;
	u8 port;
Y
Yaniv Rosner 已提交
9061
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
9062

Y
Yaniv Rosner 已提交
9063
	port = params->port;
9064

Y
Yaniv Rosner 已提交
9065 9066
	/* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
	/* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
Y
Yaniv Rosner 已提交
9067 9068 9069 9070 9071
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
Y
Yaniv Rosner 已提交
9072

Y
Yaniv Rosner 已提交
9073
	for (cnt = 0; cnt < 100; cnt++) {
Y
Yaniv Rosner 已提交
9074
		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
Y
Yaniv Rosner 已提交
9075 9076 9077 9078 9079 9080
		if (val & 1)
			break;
		udelay(5);
	}
	if (cnt == 100) {
		DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
Y
Yaniv Rosner 已提交
9081
		bnx2x_save_spirom_version(bp, port, 0,
Y
Yaniv Rosner 已提交
9082 9083 9084
					  phy->ver_addr);
		return;
	}
Y
Yaniv Rosner 已提交
9085 9086


Y
Yaniv Rosner 已提交
9087
	/* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
Y
Yaniv Rosner 已提交
9088 9089 9090
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
Y
Yaniv Rosner 已提交
9091
	for (cnt = 0; cnt < 100; cnt++) {
Y
Yaniv Rosner 已提交
9092
		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
Y
Yaniv Rosner 已提交
9093 9094 9095 9096 9097 9098
		if (val & 1)
			break;
		udelay(5);
	}
	if (cnt == 100) {
		DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
Y
Yaniv Rosner 已提交
9099
		bnx2x_save_spirom_version(bp, port, 0,
Y
Yaniv Rosner 已提交
9100 9101
					  phy->ver_addr);
		return;
Y
Yaniv Rosner 已提交
9102 9103
	}

Y
Yaniv Rosner 已提交
9104
	/* lower 16 bits of the register SPI_FW_STATUS */
Y
Yaniv Rosner 已提交
9105
	bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
Y
Yaniv Rosner 已提交
9106
	/* upper 16 bits of register SPI_FW_STATUS */
Y
Yaniv Rosner 已提交
9107
	bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
Y
Yaniv Rosner 已提交
9108

Y
Yaniv Rosner 已提交
9109
	bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
Y
Yaniv Rosner 已提交
9110 9111
				  phy->ver_addr);
}
Y
Yaniv Rosner 已提交
9112

Y
Yaniv Rosner 已提交
9113 9114
static void bnx2x_848xx_set_led(struct bnx2x *bp,
				struct bnx2x_phy *phy)
Y
Yaniv Rosner 已提交
9115
{
Y
Yaniv Rosner 已提交
9116
	u16 val;
Y
Yaniv Rosner 已提交
9117

Y
Yaniv Rosner 已提交
9118 9119 9120
	/* PHYC_CTL_LED_CTL */
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
9121
			MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
Y
Yaniv Rosner 已提交
9122 9123
	val &= 0xFE00;
	val |= 0x0092;
9124

Y
Yaniv Rosner 已提交
9125 9126
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
9127
			 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
Y
Yaniv Rosner 已提交
9128

Y
Yaniv Rosner 已提交
9129 9130
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
9131
			 MDIO_PMA_REG_8481_LED1_MASK,
Y
Yaniv Rosner 已提交
9132
			 0x80);
Y
Yaniv Rosner 已提交
9133

Y
Yaniv Rosner 已提交
9134 9135
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
9136
			 MDIO_PMA_REG_8481_LED2_MASK,
Y
Yaniv Rosner 已提交
9137
			 0x18);
Y
Yaniv Rosner 已提交
9138

Y
Yaniv Rosner 已提交
9139
	/* Select activity source by Tx and Rx, as suggested by PHY AE */
Y
Yaniv Rosner 已提交
9140 9141
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
9142
			 MDIO_PMA_REG_8481_LED3_MASK,
Y
Yaniv Rosner 已提交
9143 9144 9145 9146 9147
			 0x0006);

	/* Select the closest activity blink rate to that in 10/100/1000 */
	bnx2x_cl45_write(bp, phy,
			MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
9148
			MDIO_PMA_REG_8481_LED3_BLINK,
Y
Yaniv Rosner 已提交
9149 9150 9151 9152
			0);

	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
9153
			MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
Y
Yaniv Rosner 已提交
9154 9155 9156 9157
	val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/

	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
Y
Yaniv Rosner 已提交
9158
			 MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
Y
Yaniv Rosner 已提交
9159

Y
Yaniv Rosner 已提交
9160 9161 9162 9163
	/* 'Interrupt Mask' */
	bnx2x_cl45_write(bp, phy,
			 MDIO_AN_DEVAD,
			 0xFFFB, 0xFFFD);
Y
Yaniv Rosner 已提交
9164 9165
}

Y
Yaniv Rosner 已提交
9166 9167 9168
static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
				       struct link_params *params,
				       struct link_vars *vars)
Y
Yaniv Rosner 已提交
9169
{
9170
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
9171
	u16 autoneg_val, an_1000_val, an_10_100_val;
Y
Yaniv Rosner 已提交
9172 9173 9174 9175 9176 9177 9178
	u16 tmp_req_line_speed;

	tmp_req_line_speed = phy->req_line_speed;
	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
		if (phy->req_line_speed == SPEED_10000)
			phy->req_line_speed = SPEED_AUTO_NEG;

9179 9180 9181 9182 9183
	/*
	 * This phy uses the NIG latch mechanism since link indication
	 * arrives through its LED4 and not via its LASI signal, so we
	 * get steady signal instead of clear on read
	 */
Y
Yaniv Rosner 已提交
9184 9185
	bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
		      1 << NIG_LATCH_BC_ENABLE_MI_INT);
Y
Yaniv Rosner 已提交
9186

Y
Yaniv Rosner 已提交
9187 9188
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
Y
Yaniv Rosner 已提交
9189

Y
Yaniv Rosner 已提交
9190
	bnx2x_848xx_set_led(bp, phy);
Y
Yaniv Rosner 已提交
9191

Y
Yaniv Rosner 已提交
9192 9193 9194 9195
	/* set 1000 speed advertisement */
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
			&an_1000_val);
9196

Y
Yaniv Rosner 已提交
9197 9198 9199 9200 9201 9202 9203 9204 9205 9206 9207
	bnx2x_ext_phy_set_pause(params, phy, vars);
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD,
			MDIO_AN_REG_8481_LEGACY_AN_ADV,
			&an_10_100_val);
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
			&autoneg_val);
	/* Disable forced speed */
	autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
	an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
Y
Yaniv Rosner 已提交
9208

Y
Yaniv Rosner 已提交
9209 9210 9211 9212 9213 9214 9215 9216 9217 9218 9219
	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
	     (phy->speed_cap_mask &
	     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
	    (phy->req_line_speed == SPEED_1000)) {
		an_1000_val |= (1<<8);
		autoneg_val |= (1<<9 | 1<<12);
		if (phy->req_duplex == DUPLEX_FULL)
			an_1000_val |= (1<<9);
		DP(NETIF_MSG_LINK, "Advertising 1G\n");
	} else
		an_1000_val &= ~((1<<8) | (1<<9));
Y
Yaniv Rosner 已提交
9220

Y
Yaniv Rosner 已提交
9221 9222 9223
	bnx2x_cl45_write(bp, phy,
			 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
			 an_1000_val);
Y
Yaniv Rosner 已提交
9224

9225
	/* set 100 speed advertisement */
Y
Yaniv Rosner 已提交
9226 9227
	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
	     (phy->speed_cap_mask &
9228 9229 9230 9231 9232
	      (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
	       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
	     (phy->supported &
	      (SUPPORTED_100baseT_Half |
	       SUPPORTED_100baseT_Full)))) {
Y
Yaniv Rosner 已提交
9233 9234 9235
		an_10_100_val |= (1<<7);
		/* Enable autoneg and restart autoneg for legacy speeds */
		autoneg_val |= (1<<9 | 1<<12);
Y
Yaniv Rosner 已提交
9236

Y
Yaniv Rosner 已提交
9237 9238 9239 9240 9241 9242
		if (phy->req_duplex == DUPLEX_FULL)
			an_10_100_val |= (1<<8);
		DP(NETIF_MSG_LINK, "Advertising 100M\n");
	}
	/* set 10 speed advertisement */
	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9243 9244 9245 9246 9247 9248
	     (phy->speed_cap_mask &
	      (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
	       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
	     (phy->supported &
	      (SUPPORTED_10baseT_Half |
	       SUPPORTED_10baseT_Full)))) {
Y
Yaniv Rosner 已提交
9249 9250 9251 9252 9253 9254
		an_10_100_val |= (1<<5);
		autoneg_val |= (1<<9 | 1<<12);
		if (phy->req_duplex == DUPLEX_FULL)
			an_10_100_val |= (1<<6);
		DP(NETIF_MSG_LINK, "Advertising 10M\n");
	}
Y
Yaniv Rosner 已提交
9255

Y
Yaniv Rosner 已提交
9256
	/* Only 10/100 are allowed to work in FORCE mode */
9257 9258 9259 9260
	if ((phy->req_line_speed == SPEED_100) &&
	    (phy->supported &
	     (SUPPORTED_100baseT_Half |
	      SUPPORTED_100baseT_Full))) {
Y
Yaniv Rosner 已提交
9261 9262 9263 9264 9265 9266 9267
		autoneg_val |= (1<<13);
		/* Enabled AUTO-MDIX when autoneg is disabled */
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
				 (1<<15 | 1<<9 | 7<<0));
		DP(NETIF_MSG_LINK, "Setting 100M force\n");
	}
9268 9269 9270 9271
	if ((phy->req_line_speed == SPEED_10) &&
	    (phy->supported &
	     (SUPPORTED_10baseT_Half |
	      SUPPORTED_10baseT_Full))) {
Y
Yaniv Rosner 已提交
9272 9273 9274 9275 9276 9277
		/* Enabled AUTO-MDIX when autoneg is disabled */
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
				 (1<<15 | 1<<9 | 7<<0));
		DP(NETIF_MSG_LINK, "Setting 10M force\n");
	}
Y
Yaniv Rosner 已提交
9278

Y
Yaniv Rosner 已提交
9279 9280 9281
	bnx2x_cl45_write(bp, phy,
			 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
			 an_10_100_val);
Y
Yaniv Rosner 已提交
9282

Y
Yaniv Rosner 已提交
9283 9284
	if (phy->req_duplex == DUPLEX_FULL)
		autoneg_val |= (1<<8);
Y
Yaniv Rosner 已提交
9285

Y
Yaniv Rosner 已提交
9286 9287 9288 9289 9290 9291 9292
	/*
	 * Always write this if this is not 84833.
	 * For 84833, write it only when it's a forced speed.
	 */
	if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
		((autoneg_val & (1<<12)) == 0))
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
9293 9294
			 MDIO_AN_DEVAD,
			 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
Y
Yaniv Rosner 已提交
9295

Y
Yaniv Rosner 已提交
9296 9297 9298 9299
	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
	    (phy->speed_cap_mask &
	     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
		(phy->req_line_speed == SPEED_10000)) {
9300 9301
			DP(NETIF_MSG_LINK, "Advertising 10G\n");
			/* Restart autoneg for 10G*/
Y
Yaniv Rosner 已提交
9302

9303
			bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
9304 9305
				 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
				 0x3200);
Y
Yaniv Rosner 已提交
9306
	} else
Y
Yaniv Rosner 已提交
9307 9308 9309 9310
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD,
				 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
				 1);
Y
Yaniv Rosner 已提交
9311

Y
Yaniv Rosner 已提交
9312 9313 9314
	/* Save spirom version */
	bnx2x_save_848xx_spirom_version(phy, params);

Y
Yaniv Rosner 已提交
9315 9316
	phy->req_line_speed = tmp_req_line_speed;

Y
Yaniv Rosner 已提交
9317
	return 0;
Y
Yaniv Rosner 已提交
9318 9319
}

Y
Yaniv Rosner 已提交
9320 9321 9322
static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
				  struct link_params *params,
				  struct link_vars *vars)
Y
Yaniv Rosner 已提交
9323 9324
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
9325 9326
	/* Restore normal power mode*/
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Y
Yaniv Rosner 已提交
9327
		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
Y
Yaniv Rosner 已提交
9328

Y
Yaniv Rosner 已提交
9329 9330
	/* HW reset */
	bnx2x_ext_phy_hw_reset(bp, params->port);
9331
	bnx2x_wait_reset_complete(bp, phy, params);
9332

Y
Yaniv Rosner 已提交
9333 9334 9335
	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
	return bnx2x_848xx_cmn_config_init(phy, params, vars);
}
Y
Yaniv Rosner 已提交
9336

Y
Yaniv Rosner 已提交
9337 9338 9339 9340 9341 9342 9343

#define PHY84833_HDSHK_WAIT 300
static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
				   struct link_params *params,
				   struct link_vars *vars)
{
	u32 idx;
9344
	u32 pair_swap;
Y
Yaniv Rosner 已提交
9345
	u16 val;
9346
	u16 data;
Y
Yaniv Rosner 已提交
9347 9348 9349
	struct bnx2x *bp = params->bp;
	/* Do pair swap */

9350 9351 9352 9353 9354 9355 9356 9357 9358 9359
	/* Check for configuration. */
	pair_swap = REG_RD(bp, params->shmem_base +
			   offsetof(struct shmem_region,
			dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
		PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;

	if (pair_swap == 0)
		return 0;

	data = (u16)pair_swap;
Y
Yaniv Rosner 已提交
9360 9361 9362 9363 9364 9365 9366 9367 9368 9369 9370 9371 9372 9373 9374 9375 9376 9377 9378 9379 9380 9381 9382 9383 9384 9385 9386 9387 9388 9389 9390 9391 9392 9393 9394 9395 9396 9397 9398 9399 9400 9401 9402 9403

	/* Write CMD_OPEN_OVERRIDE to STATUS reg */
	bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
			MDIO_84833_TOP_CFG_SCRATCH_REG2,
			PHY84833_CMD_OPEN_OVERRIDE);
	for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
				MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
		if (val == PHY84833_CMD_OPEN_FOR_CMDS)
			break;
		msleep(1);
	}
	if (idx >= PHY84833_HDSHK_WAIT) {
		DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
		return -EINVAL;
	}

	bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
			MDIO_84833_TOP_CFG_SCRATCH_REG4,
			data);
	/* Issue pair swap command */
	bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
			MDIO_84833_TOP_CFG_SCRATCH_REG0,
			PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
	for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
				MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
		if ((val == PHY84833_CMD_COMPLETE_PASS) ||
			(val == PHY84833_CMD_COMPLETE_ERROR))
			break;
		msleep(1);
	}
	if ((idx >= PHY84833_HDSHK_WAIT) ||
		(val == PHY84833_CMD_COMPLETE_ERROR)) {
		DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
		return -EINVAL;
	}
	bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
			MDIO_84833_TOP_CFG_SCRATCH_REG2,
			PHY84833_CMD_CLEAR_COMPLETE);
	DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
	return 0;
}

9404

9405 9406 9407
static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
				      u32 shmem_base_path[],
				      u32 chip_id)
9408 9409 9410 9411 9412 9413 9414 9415 9416 9417 9418 9419 9420 9421 9422 9423 9424 9425 9426 9427 9428 9429 9430 9431 9432 9433 9434 9435 9436 9437 9438 9439
{
	u32 reset_pin[2];
	u32 idx;
	u8 reset_gpios;
	if (CHIP_IS_E3(bp)) {
		/* Assume that these will be GPIOs, not EPIOs. */
		for (idx = 0; idx < 2; idx++) {
			/* Map config param to register bit. */
			reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
				offsetof(struct shmem_region,
				dev_info.port_hw_config[0].e3_cmn_pin_cfg));
			reset_pin[idx] = (reset_pin[idx] &
				PORT_HW_CFG_E3_PHY_RESET_MASK) >>
				PORT_HW_CFG_E3_PHY_RESET_SHIFT;
			reset_pin[idx] -= PIN_CFG_GPIO0_P0;
			reset_pin[idx] = (1 << reset_pin[idx]);
		}
		reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
	} else {
		/* E2, look from diff place of shmem. */
		for (idx = 0; idx < 2; idx++) {
			reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
				offsetof(struct shmem_region,
				dev_info.port_hw_config[0].default_cfg));
			reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
			reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
			reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
			reset_pin[idx] = (1 << reset_pin[idx]);
		}
		reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
	}

9440 9441 9442 9443 9444 9445 9446 9447 9448 9449 9450 9451 9452 9453 9454 9455 9456 9457 9458 9459 9460 9461 9462 9463 9464 9465 9466 9467 9468 9469 9470 9471 9472 9473 9474
	return reset_gpios;
}

static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
				struct link_params *params)
{
	struct bnx2x *bp = params->bp;
	u8 reset_gpios;
	u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
				offsetof(struct shmem2_region,
				other_shmem_base_addr));

	u32 shmem_base_path[2];
	shmem_base_path[0] = params->shmem_base;
	shmem_base_path[1] = other_shmem_base_addr;

	reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
						  params->chip_id);

	bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
	udelay(10);
	DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
		reset_gpios);

	return 0;
}

static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
						u32 shmem_base_path[],
						u32 chip_id)
{
	u8 reset_gpios;

	reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);

9475 9476 9477 9478 9479 9480 9481 9482 9483 9484
	bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
	udelay(10);
	bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
	msleep(800);
	DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
		reset_gpios);

	return 0;
}

Y
Yaniv Rosner 已提交
9485
#define PHY84833_CONSTANT_LATENCY 1193
Y
Yaniv Rosner 已提交
9486 9487 9488
static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
				   struct link_params *params,
				   struct link_vars *vars)
Y
Yaniv Rosner 已提交
9489 9490
{
	struct bnx2x *bp = params->bp;
9491
	u8 port, initialize = 1;
Y
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9492
	u16 val;
Y
Yaniv Rosner 已提交
9493
	u16 temp;
Y
Yaniv Rosner 已提交
9494
	u32 actual_phy_selection, cms_enable, idx;
Y
Yaniv Rosner 已提交
9495
	int rc = 0;
9496

Y
Yaniv Rosner 已提交
9497
	msleep(1);
Y
Yaniv Rosner 已提交
9498 9499

	if (!(CHIP_IS_E1(bp)))
9500 9501 9502
		port = BP_PATH(bp);
	else
		port = params->port;
Y
Yaniv Rosner 已提交
9503 9504 9505 9506 9507 9508

	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
		bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
			       MISC_REGISTERS_GPIO_OUTPUT_HIGH,
			       port);
	} else {
9509
		/* MDIO reset */
Y
Yaniv Rosner 已提交
9510 9511 9512
		bnx2x_cl45_write(bp, phy,
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_CTRL, 0x8000);
9513
		/* Bring PHY out of super isolate mode */
Y
Yaniv Rosner 已提交
9514 9515 9516 9517 9518 9519 9520 9521 9522
		bnx2x_cl45_read(bp, phy,
				MDIO_CTL_DEVAD,
				MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
		val &= ~MDIO_84833_SUPER_ISOLATE;
		bnx2x_cl45_write(bp, phy,
				MDIO_CTL_DEVAD,
				MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
	}

9523 9524 9525 9526 9527
	bnx2x_wait_reset_complete(bp, phy, params);

	/* Wait for GPHY to come out of reset */
	msleep(50);

Y
Yaniv Rosner 已提交
9528 9529 9530
	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
		bnx2x_84833_pair_swap_cfg(phy, params, vars);

9531 9532 9533
	/*
	 * BCM84823 requires that XGXS links up first @ 10G for normal behavior
	 */
Y
Yaniv Rosner 已提交
9534 9535
	temp = vars->line_speed;
	vars->line_speed = SPEED_10000;
Y
Yaniv Rosner 已提交
9536 9537
	bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
	bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
Y
Yaniv Rosner 已提交
9538
	vars->line_speed = temp;
Y
Yaniv Rosner 已提交
9539 9540 9541 9542

	/* Set dual-media configuration according to configuration */

	bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
Y
Yaniv Rosner 已提交
9543
			MDIO_CTL_REG_84823_MEDIA, &val);
Y
Yaniv Rosner 已提交
9544 9545 9546 9547 9548
	val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
		 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
		 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
		 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
		 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9549 9550 9551 9552 9553 9554 9555 9556

	if (CHIP_IS_E3(bp)) {
		val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
			 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
	} else {
		val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
			MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
	}
Y
Yaniv Rosner 已提交
9557 9558 9559 9560 9561

	actual_phy_selection = bnx2x_phy_selection(params);

	switch (actual_phy_selection) {
	case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
L
Lucas De Marchi 已提交
9562
		/* Do nothing. Essentially this is like the priority copper */
Y
Yaniv Rosner 已提交
9563 9564 9565 9566 9567 9568 9569 9570 9571 9572 9573 9574 9575 9576 9577 9578 9579 9580 9581
		break;
	case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
		val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
		break;
	case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
		val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
		break;
	case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
		/* Do nothing here. The first PHY won't be initialized at all */
		break;
	case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
		val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
		initialize = 0;
		break;
	}
	if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
		val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;

	bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
Y
Yaniv Rosner 已提交
9582
			 MDIO_CTL_REG_84823_MEDIA, val);
Y
Yaniv Rosner 已提交
9583 9584 9585
	DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
		   params->multi_phy_config, val);

Y
Yaniv Rosner 已提交
9586 9587 9588 9589 9590 9591 9592 9593 9594 9595 9596 9597 9598 9599 9600 9601 9602 9603 9604 9605 9606 9607 9608 9609 9610 9611 9612 9613 9614 9615 9616 9617 9618 9619 9620 9621 9622 9623 9624 9625 9626 9627 9628 9629 9630 9631 9632 9633 9634 9635 9636 9637 9638 9639 9640 9641 9642 9643 9644 9645
	/* AutogrEEEn */
	if (params->feature_config_flags &
		FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
		/* Ensure that f/w is ready */
		for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
			bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
					MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
			if (val == PHY84833_CMD_OPEN_FOR_CMDS)
				break;
			usleep_range(1000, 1000);
		}
		if (idx >= PHY84833_HDSHK_WAIT) {
			DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
			return -EINVAL;
		}

		/* Select EEE mode */
		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
				MDIO_84833_TOP_CFG_SCRATCH_REG3,
				0x2);

		/* Set Idle and Latency */
		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
				MDIO_84833_TOP_CFG_SCRATCH_REG4,
				PHY84833_CONSTANT_LATENCY + 1);

		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
				MDIO_84833_TOP_CFG_DATA3_REG,
				PHY84833_CONSTANT_LATENCY + 1);

		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
				MDIO_84833_TOP_CFG_DATA4_REG,
				PHY84833_CONSTANT_LATENCY);

		/* Send EEE instruction to command register */
		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
				MDIO_84833_TOP_CFG_SCRATCH_REG0,
				PHY84833_DIAG_CMD_SET_EEE_MODE);

		/* Ensure that the command has completed */
		for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
			bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
					MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
			if ((val == PHY84833_CMD_COMPLETE_PASS) ||
				(val == PHY84833_CMD_COMPLETE_ERROR))
				break;
			usleep_range(1000, 1000);
		}
		if ((idx >= PHY84833_HDSHK_WAIT) ||
			(val == PHY84833_CMD_COMPLETE_ERROR)) {
			DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
			return -EINVAL;
		}

		/* Reset command handler */
		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
			    MDIO_84833_TOP_CFG_SCRATCH_REG2,
			    PHY84833_CMD_CLEAR_COMPLETE);
	}

Y
Yaniv Rosner 已提交
9646 9647 9648 9649
	if (initialize)
		rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
	else
		bnx2x_save_848xx_spirom_version(phy, params);
Y
Yaniv Rosner 已提交
9650 9651 9652
	/* 84833 PHY has a better feature and doesn't need to support this. */
	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
		cms_enable = REG_RD(bp, params->shmem_base +
9653 9654 9655 9656
			offsetof(struct shmem_region,
			dev_info.port_hw_config[params->port].default_cfg)) &
			PORT_HW_CFG_ENABLE_CMS_MASK;

Y
Yaniv Rosner 已提交
9657 9658 9659 9660 9661 9662 9663 9664 9665
		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
				MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
		if (cms_enable)
			val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
		else
			val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
				 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
	}
9666

Y
Yaniv Rosner 已提交
9667
	return rc;
Y
Yaniv Rosner 已提交
9668
}
Y
Yaniv Rosner 已提交
9669

Y
Yaniv Rosner 已提交
9670
static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
Y
Yaniv Rosner 已提交
9671 9672
				  struct link_params *params,
				  struct link_vars *vars)
Y
Yaniv Rosner 已提交
9673 9674
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
9675
	u16 val, val1, val2;
Y
Yaniv Rosner 已提交
9676
	u8 link_up = 0;
Y
Yaniv Rosner 已提交
9677

9678

Y
Yaniv Rosner 已提交
9679 9680 9681 9682 9683
	/* Check 10G-BaseT link status */
	/* Check PMD signal ok */
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD, 0xFFFA, &val1);
	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
9684
			MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
Y
Yaniv Rosner 已提交
9685 9686
			&val2);
	DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
Y
Yaniv Rosner 已提交
9687

Y
Yaniv Rosner 已提交
9688 9689
	/* Check link 10G */
	if (val2 & (1<<11)) {
Y
Yaniv Rosner 已提交
9690
		vars->line_speed = SPEED_10000;
9691
		vars->duplex = DUPLEX_FULL;
Y
Yaniv Rosner 已提交
9692 9693 9694 9695
		link_up = 1;
		bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
	} else { /* Check Legacy speed link */
		u16 legacy_status, legacy_speed;
Y
Yaniv Rosner 已提交
9696

Y
Yaniv Rosner 已提交
9697 9698 9699 9700
		/* Enable expansion register 0x42 (Operation mode status) */
		bnx2x_cl45_write(bp, phy,
				 MDIO_AN_DEVAD,
				 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
Y
Yaniv Rosner 已提交
9701

Y
Yaniv Rosner 已提交
9702 9703 9704 9705 9706
		/* Get legacy speed operation status */
		bnx2x_cl45_read(bp, phy,
				MDIO_AN_DEVAD,
				MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
				&legacy_status);
Y
Yaniv Rosner 已提交
9707

9708 9709
		DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
		   legacy_status);
Y
Yaniv Rosner 已提交
9710 9711 9712 9713 9714 9715 9716 9717 9718 9719 9720
		link_up = ((legacy_status & (1<<11)) == (1<<11));
		if (link_up) {
			legacy_speed = (legacy_status & (3<<9));
			if (legacy_speed == (0<<9))
				vars->line_speed = SPEED_10;
			else if (legacy_speed == (1<<9))
				vars->line_speed = SPEED_100;
			else if (legacy_speed == (2<<9))
				vars->line_speed = SPEED_1000;
			else /* Should not happen */
				vars->line_speed = 0;
Y
Yaniv Rosner 已提交
9721

Y
Yaniv Rosner 已提交
9722 9723 9724 9725
			if (legacy_status & (1<<8))
				vars->duplex = DUPLEX_FULL;
			else
				vars->duplex = DUPLEX_HALF;
Y
Yaniv Rosner 已提交
9726

9727 9728 9729 9730
			DP(NETIF_MSG_LINK,
			   "Link is up in %dMbps, is_duplex_full= %d\n",
			   vars->line_speed,
			   (vars->duplex == DUPLEX_FULL));
Y
Yaniv Rosner 已提交
9731 9732 9733 9734 9735 9736 9737 9738 9739 9740 9741 9742 9743 9744 9745
			/* Check legacy speed AN resolution */
			bnx2x_cl45_read(bp, phy,
					MDIO_AN_DEVAD,
					MDIO_AN_REG_8481_LEGACY_MII_STATUS,
					&val);
			if (val & (1<<5))
				vars->link_status |=
					LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
			bnx2x_cl45_read(bp, phy,
					MDIO_AN_DEVAD,
					MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
					&val);
			if ((val & (1<<0)) == 0)
				vars->link_status |=
					LINK_STATUS_PARALLEL_DETECTION_USED;
Y
Yaniv Rosner 已提交
9746 9747
		}
	}
Y
Yaniv Rosner 已提交
9748 9749 9750 9751 9752
	if (link_up) {
		DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
			   vars->line_speed);
		bnx2x_ext_phy_resolve_fc(phy, params, vars);
	}
E
Eilon Greenstein 已提交
9753

Y
Yaniv Rosner 已提交
9754
	return link_up;
Y
Yaniv Rosner 已提交
9755 9756
}

Y
Yaniv Rosner 已提交
9757 9758

static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
Y
Yaniv Rosner 已提交
9759
{
Y
Yaniv Rosner 已提交
9760
	int status = 0;
Y
Yaniv Rosner 已提交
9761 9762 9763 9764
	u32 spirom_ver;
	spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
	status = bnx2x_format_ver(spirom_ver, str, len);
	return status;
Y
Yaniv Rosner 已提交
9765
}
Y
Yaniv Rosner 已提交
9766 9767 9768

static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
				struct link_params *params)
Y
Yaniv Rosner 已提交
9769
{
Y
Yaniv Rosner 已提交
9770
	bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
Y
Yaniv Rosner 已提交
9771
		       MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
Y
Yaniv Rosner 已提交
9772
	bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
Y
Yaniv Rosner 已提交
9773
		       MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
Y
Yaniv Rosner 已提交
9774
}
Y
Yaniv Rosner 已提交
9775

Y
Yaniv Rosner 已提交
9776 9777 9778 9779 9780 9781 9782 9783 9784 9785 9786 9787 9788
static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
					struct link_params *params)
{
	bnx2x_cl45_write(params->bp, phy,
			 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
	bnx2x_cl45_write(params->bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
}

static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
				   struct link_params *params)
{
	struct bnx2x *bp = params->bp;
9789
	u8 port;
9790
	u16 val16;
Y
Yaniv Rosner 已提交
9791 9792

	if (!(CHIP_IS_E1(bp)))
9793 9794 9795
		port = BP_PATH(bp);
	else
		port = params->port;
Y
Yaniv Rosner 已提交
9796 9797 9798 9799 9800 9801

	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
		bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
			       MISC_REGISTERS_GPIO_OUTPUT_LOW,
			       port);
	} else {
9802 9803 9804
		bnx2x_cl45_read(bp, phy,
				MDIO_CTL_DEVAD,
				0x400f, &val16);
Y
Yaniv Rosner 已提交
9805 9806 9807
		bnx2x_cl45_write(bp, phy,
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_CTRL, 0x800);
Y
Yaniv Rosner 已提交
9808
	}
Y
Yaniv Rosner 已提交
9809 9810
}

9811 9812 9813 9814 9815
static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
				     struct link_params *params, u8 mode)
{
	struct bnx2x *bp = params->bp;
	u16 val;
Y
Yaniv Rosner 已提交
9816 9817 9818 9819 9820 9821
	u8 port;

	if (!(CHIP_IS_E1(bp)))
		port = BP_PATH(bp);
	else
		port = params->port;
9822 9823 9824 9825

	switch (mode) {
	case LED_MODE_OFF:

Y
Yaniv Rosner 已提交
9826
		DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9827 9828 9829 9830 9831 9832 9833 9834 9835 9836 9837 9838 9839 9840 9841 9842 9843 9844 9845 9846 9847 9848 9849 9850 9851 9852 9853 9854 9855 9856 9857 9858 9859 9860 9861

		if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
		    SHARED_HW_CFG_LED_EXTPHY1) {

			/* Set LED masks */
			bnx2x_cl45_write(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_8481_LED1_MASK,
					0x0);

			bnx2x_cl45_write(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_8481_LED2_MASK,
					0x0);

			bnx2x_cl45_write(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_8481_LED3_MASK,
					0x0);

			bnx2x_cl45_write(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_8481_LED5_MASK,
					0x0);

		} else {
			bnx2x_cl45_write(bp, phy,
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED1_MASK,
					 0x0);
		}
		break;
	case LED_MODE_FRONT_PANEL_OFF:

		DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
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9862
		   port);
9863 9864 9865 9866 9867 9868

		if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
		    SHARED_HW_CFG_LED_EXTPHY1) {

			/* Set LED masks */
			bnx2x_cl45_write(bp, phy,
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9869 9870 9871
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED1_MASK,
					 0x0);
9872 9873

			bnx2x_cl45_write(bp, phy,
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9874 9875 9876
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED2_MASK,
					 0x0);
9877 9878

			bnx2x_cl45_write(bp, phy,
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9879 9880 9881
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED3_MASK,
					 0x0);
9882 9883

			bnx2x_cl45_write(bp, phy,
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9884 9885 9886
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED5_MASK,
					 0x20);
9887 9888 9889 9890 9891 9892 9893 9894 9895 9896

		} else {
			bnx2x_cl45_write(bp, phy,
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED1_MASK,
					 0x0);
		}
		break;
	case LED_MODE_ON:

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9897
		DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9898 9899 9900 9901 9902 9903 9904 9905 9906 9907 9908 9909

		if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
		    SHARED_HW_CFG_LED_EXTPHY1) {
			/* Set control reg */
			bnx2x_cl45_read(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_8481_LINK_SIGNAL,
					&val);
			val &= 0x8000;
			val |= 0x2492;

			bnx2x_cl45_write(bp, phy,
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					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LINK_SIGNAL,
					 val);
9913 9914 9915

			/* Set LED masks */
			bnx2x_cl45_write(bp, phy,
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9916 9917 9918
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED1_MASK,
					 0x0);
9919 9920

			bnx2x_cl45_write(bp, phy,
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9921 9922 9923
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED2_MASK,
					 0x20);
9924 9925

			bnx2x_cl45_write(bp, phy,
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9926 9927 9928
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED3_MASK,
					 0x20);
9929 9930

			bnx2x_cl45_write(bp, phy,
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9931 9932 9933
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED5_MASK,
					 0x0);
9934 9935
		} else {
			bnx2x_cl45_write(bp, phy,
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9936 9937 9938
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED1_MASK,
					 0x20);
9939 9940 9941 9942 9943
		}
		break;

	case LED_MODE_OPER:

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9944
		DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9945 9946 9947 9948 9949 9950 9951 9952 9953 9954 9955

		if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
		    SHARED_HW_CFG_LED_EXTPHY1) {

			/* Set control reg */
			bnx2x_cl45_read(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_8481_LINK_SIGNAL,
					&val);

			if (!((val &
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			       MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
			  >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9958
				DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9959 9960 9961 9962 9963 9964 9965 9966
				bnx2x_cl45_write(bp, phy,
						 MDIO_PMA_DEVAD,
						 MDIO_PMA_REG_8481_LINK_SIGNAL,
						 0xa492);
			}

			/* Set LED masks */
			bnx2x_cl45_write(bp, phy,
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					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED1_MASK,
					 0x10);
9970 9971

			bnx2x_cl45_write(bp, phy,
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9972 9973 9974
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED2_MASK,
					 0x80);
9975 9976

			bnx2x_cl45_write(bp, phy,
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9977 9978 9979
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED3_MASK,
					 0x98);
9980 9981

			bnx2x_cl45_write(bp, phy,
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9982 9983 9984
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED5_MASK,
					 0x40);
9985 9986 9987 9988 9989 9990

		} else {
			bnx2x_cl45_write(bp, phy,
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LED1_MASK,
					 0x80);
9991 9992 9993 9994 9995 9996 9997 9998 9999 10000 10001 10002

			/* Tell LED3 to blink on source */
			bnx2x_cl45_read(bp, phy,
					MDIO_PMA_DEVAD,
					MDIO_PMA_REG_8481_LINK_SIGNAL,
					&val);
			val &= ~(7<<6);
			val |= (1<<6); /* A83B[8:6]= 1 */
			bnx2x_cl45_write(bp, phy,
					 MDIO_PMA_DEVAD,
					 MDIO_PMA_REG_8481_LINK_SIGNAL,
					 val);
10003 10004 10005
		}
		break;
	}
10006 10007 10008 10009 10010 10011 10012 10013 10014

	/*
	 * This is a workaround for E3+84833 until autoneg
	 * restart is fixed in f/w
	 */
	if (CHIP_IS_E3(bp)) {
		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
				MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
	}
10015
}
10016

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10017
/******************************************************************/
10018
/*			54618SE PHY SECTION			  */
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10019
/******************************************************************/
10020
static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
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10021 10022 10023 10024 10025 10026 10027 10028
					       struct link_params *params,
					       struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	u8 port;
	u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
	u32 cfg_pin;

10029
	DP(NETIF_MSG_LINK, "54618SE cfg init\n");
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10030 10031 10032 10033 10034 10035 10036 10037 10038 10039 10040 10041 10042 10043 10044 10045 10046 10047 10048 10049 10050 10051 10052 10053 10054 10055 10056 10057 10058 10059 10060 10061 10062 10063 10064 10065 10066 10067 10068 10069 10070 10071 10072 10073 10074 10075 10076 10077 10078 10079 10080 10081 10082 10083 10084 10085 10086 10087 10088 10089 10090 10091 10092 10093 10094 10095 10096 10097 10098 10099 10100 10101 10102 10103 10104 10105 10106 10107 10108 10109 10110 10111 10112 10113 10114 10115 10116 10117 10118 10119 10120 10121 10122 10123 10124 10125 10126 10127 10128 10129 10130 10131 10132 10133 10134 10135 10136 10137 10138 10139 10140 10141 10142 10143 10144 10145 10146 10147 10148 10149 10150 10151 10152 10153 10154 10155 10156 10157 10158 10159 10160 10161 10162 10163 10164 10165 10166 10167 10168 10169 10170 10171 10172 10173 10174 10175 10176 10177
	usleep_range(1000, 1000);

	/* This works with E3 only, no need to check the chip
	   before determining the port. */
	port = params->port;

	cfg_pin = (REG_RD(bp, params->shmem_base +
			offsetof(struct shmem_region,
			dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
			PORT_HW_CFG_E3_PHY_RESET_MASK) >>
			PORT_HW_CFG_E3_PHY_RESET_SHIFT;

	/* Drive pin high to bring the GPHY out of reset. */
	bnx2x_set_cfg_pin(bp, cfg_pin, 1);

	/* wait for GPHY to reset */
	msleep(50);

	/* reset phy */
	bnx2x_cl22_write(bp, phy,
			 MDIO_PMA_REG_CTRL, 0x8000);
	bnx2x_wait_reset_complete(bp, phy, params);

	/*wait for GPHY to reset */
	msleep(50);

	/* Configure LED4: set to INTR (0x6). */
	/* Accessing shadow register 0xe. */
	bnx2x_cl22_write(bp, phy,
			MDIO_REG_GPHY_SHADOW,
			MDIO_REG_GPHY_SHADOW_LED_SEL2);
	bnx2x_cl22_read(bp, phy,
			MDIO_REG_GPHY_SHADOW,
			&temp);
	temp &= ~(0xf << 4);
	temp |= (0x6 << 4);
	bnx2x_cl22_write(bp, phy,
			MDIO_REG_GPHY_SHADOW,
			MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
	/* Configure INTR based on link status change. */
	bnx2x_cl22_write(bp, phy,
			MDIO_REG_INTR_MASK,
			~MDIO_REG_INTR_MASK_LINK_STATUS);

	/* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
	bnx2x_cl22_write(bp, phy,
			MDIO_REG_GPHY_SHADOW,
			MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
	bnx2x_cl22_read(bp, phy,
			MDIO_REG_GPHY_SHADOW,
			&temp);
	temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
	bnx2x_cl22_write(bp, phy,
			MDIO_REG_GPHY_SHADOW,
			MDIO_REG_GPHY_SHADOW_WR_ENA | temp);

	/* Set up fc */
	/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
	bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
	fc_val = 0;
	if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
			MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
		fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;

	if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
			MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
		fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;

	/* read all advertisement */
	bnx2x_cl22_read(bp, phy,
			0x09,
			&an_1000_val);

	bnx2x_cl22_read(bp, phy,
			0x04,
			&an_10_100_val);

	bnx2x_cl22_read(bp, phy,
			MDIO_PMA_REG_CTRL,
			&autoneg_val);

	/* Disable forced speed */
	autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
	an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
			   (1<<11));

	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
			(phy->speed_cap_mask &
			PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
			(phy->req_line_speed == SPEED_1000)) {
		an_1000_val |= (1<<8);
		autoneg_val |= (1<<9 | 1<<12);
		if (phy->req_duplex == DUPLEX_FULL)
			an_1000_val |= (1<<9);
		DP(NETIF_MSG_LINK, "Advertising 1G\n");
	} else
		an_1000_val &= ~((1<<8) | (1<<9));

	bnx2x_cl22_write(bp, phy,
			0x09,
			an_1000_val);
	bnx2x_cl22_read(bp, phy,
			0x09,
			&an_1000_val);

	/* set 100 speed advertisement */
	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
			(phy->speed_cap_mask &
			(PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
			PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
		an_10_100_val |= (1<<7);
		/* Enable autoneg and restart autoneg for legacy speeds */
		autoneg_val |= (1<<9 | 1<<12);

		if (phy->req_duplex == DUPLEX_FULL)
			an_10_100_val |= (1<<8);
		DP(NETIF_MSG_LINK, "Advertising 100M\n");
	}

	/* set 10 speed advertisement */
	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
			(phy->speed_cap_mask &
			(PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
			PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
		an_10_100_val |= (1<<5);
		autoneg_val |= (1<<9 | 1<<12);
		if (phy->req_duplex == DUPLEX_FULL)
			an_10_100_val |= (1<<6);
		DP(NETIF_MSG_LINK, "Advertising 10M\n");
	}

	/* Only 10/100 are allowed to work in FORCE mode */
	if (phy->req_line_speed == SPEED_100) {
		autoneg_val |= (1<<13);
		/* Enabled AUTO-MDIX when autoneg is disabled */
		bnx2x_cl22_write(bp, phy,
				0x18,
				(1<<15 | 1<<9 | 7<<0));
		DP(NETIF_MSG_LINK, "Setting 100M force\n");
	}
	if (phy->req_line_speed == SPEED_10) {
		/* Enabled AUTO-MDIX when autoneg is disabled */
		bnx2x_cl22_write(bp, phy,
				0x18,
				(1<<15 | 1<<9 | 7<<0));
		DP(NETIF_MSG_LINK, "Setting 10M force\n");
	}

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10178 10179 10180 10181 10182 10183 10184 10185 10186 10187 10188 10189 10190 10191 10192 10193 10194 10195 10196 10197 10198 10199 10200 10201
	/* Check if we should turn on Auto-GrEEEn */
	bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
	if (temp == MDIO_REG_GPHY_ID_54618SE) {
		if (params->feature_config_flags &
		    FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
			temp = 6;
			DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
		} else {
			temp = 0;
			DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
		}
		bnx2x_cl22_write(bp, phy,
				 MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
		bnx2x_cl22_write(bp, phy,
				 MDIO_REG_GPHY_CL45_DATA_REG,
				 MDIO_REG_GPHY_EEE_ADV);
		bnx2x_cl22_write(bp, phy,
				 MDIO_REG_GPHY_CL45_ADDR_REG,
				 (0x1 << 14) | MDIO_AN_DEVAD);
		bnx2x_cl22_write(bp, phy,
				 MDIO_REG_GPHY_CL45_DATA_REG,
				 temp);
	}

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10202 10203 10204 10205 10206 10207 10208 10209 10210 10211 10212 10213 10214
	bnx2x_cl22_write(bp, phy,
			0x04,
			an_10_100_val | fc_val);

	if (phy->req_duplex == DUPLEX_FULL)
		autoneg_val |= (1<<8);

	bnx2x_cl22_write(bp, phy,
			MDIO_PMA_REG_CTRL, autoneg_val);

	return 0;
}

10215 10216
static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
				       struct link_params *params, u8 mode)
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10217 10218
{
	struct bnx2x *bp = params->bp;
10219
	DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
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10220 10221 10222 10223 10224 10225 10226 10227 10228 10229 10230
	switch (mode) {
	case LED_MODE_FRONT_PANEL_OFF:
	case LED_MODE_OFF:
	case LED_MODE_OPER:
	case LED_MODE_ON:
	default:
		break;
	}
	return;
}

10231 10232
static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
				     struct link_params *params)
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10233 10234 10235 10236 10237
{
	struct bnx2x *bp = params->bp;
	u32 cfg_pin;
	u8 port;

10238 10239 10240 10241 10242 10243 10244 10245 10246
	/*
	 * In case of no EPIO routed to reset the GPHY, put it
	 * in low power mode.
	 */
	bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
	/*
	 * This works with E3 only, no need to check the chip
	 * before determining the port.
	 */
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10247 10248 10249 10250 10251 10252 10253 10254 10255 10256 10257
	port = params->port;
	cfg_pin = (REG_RD(bp, params->shmem_base +
			offsetof(struct shmem_region,
			dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
			PORT_HW_CFG_E3_PHY_RESET_MASK) >>
			PORT_HW_CFG_E3_PHY_RESET_SHIFT;

	/* Drive pin low to put GPHY in reset. */
	bnx2x_set_cfg_pin(bp, cfg_pin, 0);
}

10258 10259 10260
static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
				    struct link_params *params,
				    struct link_vars *vars)
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10261 10262 10263 10264 10265 10266 10267 10268 10269 10270
{
	struct bnx2x *bp = params->bp;
	u16 val;
	u8 link_up = 0;
	u16 legacy_status, legacy_speed;

	/* Get speed operation status */
	bnx2x_cl22_read(bp, phy,
			0x19,
			&legacy_status);
10271
	DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
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10272 10273 10274 10275 10276 10277 10278 10279 10280 10281 10282 10283 10284 10285 10286 10287 10288 10289 10290 10291 10292 10293 10294 10295 10296 10297 10298 10299 10300 10301 10302 10303 10304

	/* Read status to clear the PHY interrupt. */
	bnx2x_cl22_read(bp, phy,
			MDIO_REG_INTR_STATUS,
			&val);

	link_up = ((legacy_status & (1<<2)) == (1<<2));

	if (link_up) {
		legacy_speed = (legacy_status & (7<<8));
		if (legacy_speed == (7<<8)) {
			vars->line_speed = SPEED_1000;
			vars->duplex = DUPLEX_FULL;
		} else if (legacy_speed == (6<<8)) {
			vars->line_speed = SPEED_1000;
			vars->duplex = DUPLEX_HALF;
		} else if (legacy_speed == (5<<8)) {
			vars->line_speed = SPEED_100;
			vars->duplex = DUPLEX_FULL;
		}
		/* Omitting 100Base-T4 for now */
		else if (legacy_speed == (3<<8)) {
			vars->line_speed = SPEED_100;
			vars->duplex = DUPLEX_HALF;
		} else if (legacy_speed == (2<<8)) {
			vars->line_speed = SPEED_10;
			vars->duplex = DUPLEX_FULL;
		} else if (legacy_speed == (1<<8)) {
			vars->line_speed = SPEED_10;
			vars->duplex = DUPLEX_HALF;
		} else /* Should not happen */
			vars->line_speed = 0;

10305 10306 10307 10308
		DP(NETIF_MSG_LINK,
		   "Link is up in %dMbps, is_duplex_full= %d\n",
		   vars->line_speed,
		   (vars->duplex == DUPLEX_FULL));
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		/* Check legacy speed AN resolution */
		bnx2x_cl22_read(bp, phy,
				0x01,
				&val);
		if (val & (1<<5))
			vars->link_status |=
				LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
		bnx2x_cl22_read(bp, phy,
				0x06,
				&val);
		if ((val & (1<<0)) == 0)
			vars->link_status |=
				LINK_STATUS_PARALLEL_DETECTION_USED;

10324
		DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
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10325
			   vars->line_speed);
10326 10327 10328 10329 10330 10331 10332 10333 10334 10335 10336 10337 10338 10339 10340 10341 10342 10343 10344 10345 10346 10347 10348 10349

		/* Report whether EEE is resolved. */
		bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
		if (val == MDIO_REG_GPHY_ID_54618SE) {
			if (vars->link_status &
			    LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
				val = 0;
			else {
				bnx2x_cl22_write(bp, phy,
					MDIO_REG_GPHY_CL45_ADDR_REG,
					MDIO_AN_DEVAD);
				bnx2x_cl22_write(bp, phy,
					MDIO_REG_GPHY_CL45_DATA_REG,
					MDIO_REG_GPHY_EEE_RESOLVED);
				bnx2x_cl22_write(bp, phy,
					MDIO_REG_GPHY_CL45_ADDR_REG,
					(0x1 << 14) | MDIO_AN_DEVAD);
				bnx2x_cl22_read(bp, phy,
					MDIO_REG_GPHY_CL45_DATA_REG,
					&val);
			}
			DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
		}

Y
Yaniv Rosner 已提交
10350 10351 10352 10353 10354
		bnx2x_ext_phy_resolve_fc(phy, params, vars);
	}
	return link_up;
}

10355 10356
static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
					  struct link_params *params)
Y
Yaniv Rosner 已提交
10357 10358 10359 10360 10361
{
	struct bnx2x *bp = params->bp;
	u16 val;
	u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;

10362
	DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
Y
Yaniv Rosner 已提交
10363 10364 10365 10366 10367 10368 10369 10370 10371 10372 10373 10374 10375 10376 10377 10378 10379 10380 10381 10382 10383 10384 10385 10386 10387 10388 10389 10390 10391 10392 10393 10394 10395

	/* Enable master/slave manual mmode and set to master */
	/* mii write 9 [bits set 11 12] */
	bnx2x_cl22_write(bp, phy, 0x09, 3<<11);

	/* forced 1G and disable autoneg */
	/* set val [mii read 0] */
	/* set val [expr $val & [bits clear 6 12 13]] */
	/* set val [expr $val | [bits set 6 8]] */
	/* mii write 0 $val */
	bnx2x_cl22_read(bp, phy, 0x00, &val);
	val &= ~((1<<6) | (1<<12) | (1<<13));
	val |= (1<<6) | (1<<8);
	bnx2x_cl22_write(bp, phy, 0x00, val);

	/* Set external loopback and Tx using 6dB coding */
	/* mii write 0x18 7 */
	/* set val [mii read 0x18] */
	/* mii write 0x18 [expr $val | [bits set 10 15]] */
	bnx2x_cl22_write(bp, phy, 0x18, 7);
	bnx2x_cl22_read(bp, phy, 0x18, &val);
	bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));

	/* This register opens the gate for the UMAC despite its name */
	REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);

	/*
	 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
	 * length used by the MAC receive logic to check frames.
	 */
	REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
}

Y
Yaniv Rosner 已提交
10396 10397 10398 10399 10400
/******************************************************************/
/*			SFX7101 PHY SECTION			  */
/******************************************************************/
static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
				       struct link_params *params)
Y
Yaniv Rosner 已提交
10401 10402
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
10403 10404 10405
	/* SFX7101_XGXS_TEST1 */
	bnx2x_cl45_write(bp, phy,
			 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
E
Eilon Greenstein 已提交
10406 10407
}

Y
Yaniv Rosner 已提交
10408 10409 10410
static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
				  struct link_params *params,
				  struct link_vars *vars)
Y
Yaniv Rosner 已提交
10411
{
Y
Yaniv Rosner 已提交
10412
	u16 fw_ver1, fw_ver2, val;
Y
Yaniv Rosner 已提交
10413
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
10414
	DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
Y
Yaniv Rosner 已提交
10415

Y
Yaniv Rosner 已提交
10416 10417
	/* Restore normal power mode*/
	bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Y
Yaniv Rosner 已提交
10418
		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
Y
Yaniv Rosner 已提交
10419 10420
	/* HW reset */
	bnx2x_ext_phy_hw_reset(bp, params->port);
10421
	bnx2x_wait_reset_complete(bp, phy, params);
Y
Yaniv Rosner 已提交
10422

Y
Yaniv Rosner 已提交
10423
	bnx2x_cl45_write(bp, phy,
10424
			 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
Y
Yaniv Rosner 已提交
10425 10426 10427
	DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
Y
Yaniv Rosner 已提交
10428

Y
Yaniv Rosner 已提交
10429 10430 10431 10432 10433 10434 10435
	bnx2x_ext_phy_set_pause(params, phy, vars);
	/* Restart autoneg */
	bnx2x_cl45_read(bp, phy,
			MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
	val |= 0x200;
	bnx2x_cl45_write(bp, phy,
			 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
Y
Yaniv Rosner 已提交
10436

Y
Yaniv Rosner 已提交
10437 10438 10439
	/* Save spirom version */
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
Y
Yaniv Rosner 已提交
10440

Y
Yaniv Rosner 已提交
10441 10442 10443 10444 10445 10446
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
	bnx2x_save_spirom_version(bp, params->port,
				  (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
	return 0;
}
Y
Yaniv Rosner 已提交
10447

Y
Yaniv Rosner 已提交
10448 10449 10450
static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
				 struct link_params *params,
				 struct link_vars *vars)
10451 10452
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
10453 10454 10455
	u8 link_up;
	u16 val1, val2;
	bnx2x_cl45_read(bp, phy,
10456
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
Y
Yaniv Rosner 已提交
10457
	bnx2x_cl45_read(bp, phy,
10458
			MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
Y
Yaniv Rosner 已提交
10459 10460 10461 10462 10463 10464 10465 10466 10467
	DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
		   val2, val1);
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
	bnx2x_cl45_read(bp, phy,
			MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
	DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
		   val2, val1);
	link_up = ((val1 & 4) == 4);
10468
	/* if link is up print the AN outcome of the SFX7101 PHY */
Y
Yaniv Rosner 已提交
10469 10470 10471 10472 10473
	if (link_up) {
		bnx2x_cl45_read(bp, phy,
				MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
				&val2);
		vars->line_speed = SPEED_10000;
10474
		vars->duplex = DUPLEX_FULL;
Y
Yaniv Rosner 已提交
10475 10476 10477 10478 10479 10480 10481
		DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
			   val2, (val2 & (1<<14)));
		bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
		bnx2x_ext_phy_resolve_fc(phy, params, vars);
	}
	return link_up;
}
E
Eilon Greenstein 已提交
10482

Y
Yaniv Rosner 已提交
10483
static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
Y
Yaniv Rosner 已提交
10484 10485 10486 10487 10488 10489 10490 10491 10492
{
	if (*len < 5)
		return -EINVAL;
	str[0] = (spirom_ver & 0xFF);
	str[1] = (spirom_ver & 0xFF00) >> 8;
	str[2] = (spirom_ver & 0xFF0000) >> 16;
	str[3] = (spirom_ver & 0xFF000000) >> 24;
	str[4] = '\0';
	*len -= 5;
10493 10494 10495
	return 0;
}

Y
Yaniv Rosner 已提交
10496
void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10497
{
Y
Yaniv Rosner 已提交
10498
	u16 val, cnt;
10499

Y
Yaniv Rosner 已提交
10500
	bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
10501 10502
			MDIO_PMA_DEVAD,
			MDIO_PMA_REG_7101_RESET, &val);
10503

Y
Yaniv Rosner 已提交
10504 10505 10506 10507
	for (cnt = 0; cnt < 10; cnt++) {
		msleep(50);
		/* Writes a self-clearing reset */
		bnx2x_cl45_write(bp, phy,
Y
Yaniv Rosner 已提交
10508 10509 10510
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_7101_RESET,
				 (val | (1<<15)));
Y
Yaniv Rosner 已提交
10511 10512
		/* Wait for clear */
		bnx2x_cl45_read(bp, phy,
Y
Yaniv Rosner 已提交
10513 10514
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_7101_RESET, &val);
10515

Y
Yaniv Rosner 已提交
10516 10517
		if ((val & (1<<15)) == 0)
			break;
10518 10519
	}
}
Y
Yaniv Rosner 已提交
10520

Y
Yaniv Rosner 已提交
10521 10522 10523 10524
static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
				struct link_params *params) {
	/* Low power mode is controlled by GPIO 2 */
	bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
Y
Yaniv Rosner 已提交
10525
		       MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
Y
Yaniv Rosner 已提交
10526 10527
	/* The PHY reset is controlled by GPIO 1 */
	bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
Y
Yaniv Rosner 已提交
10528
		       MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
Y
Yaniv Rosner 已提交
10529
}
Y
Yaniv Rosner 已提交
10530

10531 10532 10533 10534 10535 10536 10537 10538 10539 10540 10541 10542 10543 10544 10545 10546 10547 10548 10549 10550 10551 10552 10553
static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
				    struct link_params *params, u8 mode)
{
	u16 val = 0;
	struct bnx2x *bp = params->bp;
	switch (mode) {
	case LED_MODE_FRONT_PANEL_OFF:
	case LED_MODE_OFF:
		val = 2;
		break;
	case LED_MODE_ON:
		val = 1;
		break;
	case LED_MODE_OPER:
		val = 0;
		break;
	}
	bnx2x_cl45_write(bp, phy,
			 MDIO_PMA_DEVAD,
			 MDIO_PMA_REG_7107_LINK_LED_CNTL,
			 val);
}

Y
Yaniv Rosner 已提交
10554 10555 10556
/******************************************************************/
/*			STATIC PHY DECLARATION			  */
/******************************************************************/
Y
Yaniv Rosner 已提交
10557

Y
Yaniv Rosner 已提交
10558 10559 10560 10561
static struct bnx2x_phy phy_null = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
	.addr		= 0,
	.def_md_devad	= 0,
10562
	.flags		= FLAGS_INIT_XGXS_FIRST,
Y
Yaniv Rosner 已提交
10563 10564 10565 10566 10567 10568
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= 0,
	.media_type	= ETH_PHY_NOT_PRESENT,
	.ver_addr	= 0,
Y
Yaniv Rosner 已提交
10569 10570 10571
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
Y
Yaniv Rosner 已提交
10572 10573 10574 10575 10576 10577 10578 10579
	.req_duplex	= 0,
	.rsrv		= 0,
	.config_init	= (config_init_t)NULL,
	.read_status	= (read_status_t)NULL,
	.link_reset	= (link_reset_t)NULL,
	.config_loopback = (config_loopback_t)NULL,
	.format_fw_ver	= (format_fw_ver_t)NULL,
	.hw_reset	= (hw_reset_t)NULL,
Y
Yaniv Rosner 已提交
10580 10581
	.set_link_led	= (set_link_led_t)NULL,
	.phy_specific_func = (phy_specific_func_t)NULL
Y
Yaniv Rosner 已提交
10582
};
Y
Yaniv Rosner 已提交
10583

Y
Yaniv Rosner 已提交
10584 10585 10586 10587
static struct bnx2x_phy phy_serdes = {
	.type		= PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
	.addr		= 0xff,
	.def_md_devad	= 0,
10588
	.flags		= 0,
Y
Yaniv Rosner 已提交
10589 10590 10591 10592 10593 10594 10595 10596 10597 10598 10599 10600 10601
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10baseT_Half |
			   SUPPORTED_10baseT_Full |
			   SUPPORTED_100baseT_Half |
			   SUPPORTED_100baseT_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_2500baseX_Full |
			   SUPPORTED_TP |
			   SUPPORTED_Autoneg |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
Y
Yaniv Rosner 已提交
10602
	.media_type	= ETH_PHY_BASE_T,
Y
Yaniv Rosner 已提交
10603 10604
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
Y
Yaniv Rosner 已提交
10605 10606
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
Y
Yaniv Rosner 已提交
10607 10608
	.req_duplex	= 0,
	.rsrv		= 0,
Y
Yaniv Rosner 已提交
10609
	.config_init	= (config_init_t)bnx2x_xgxs_config_init,
Y
Yaniv Rosner 已提交
10610 10611 10612 10613 10614
	.read_status	= (read_status_t)bnx2x_link_settings_status,
	.link_reset	= (link_reset_t)bnx2x_int_link_reset,
	.config_loopback = (config_loopback_t)NULL,
	.format_fw_ver	= (format_fw_ver_t)NULL,
	.hw_reset	= (hw_reset_t)NULL,
Y
Yaniv Rosner 已提交
10615 10616
	.set_link_led	= (set_link_led_t)NULL,
	.phy_specific_func = (phy_specific_func_t)NULL
Y
Yaniv Rosner 已提交
10617
};
Y
Yaniv Rosner 已提交
10618 10619 10620 10621 10622

static struct bnx2x_phy phy_xgxs = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
	.addr		= 0xff,
	.def_md_devad	= 0,
10623
	.flags		= 0,
Y
Yaniv Rosner 已提交
10624 10625 10626 10627 10628 10629 10630 10631 10632 10633 10634 10635 10636 10637
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10baseT_Half |
			   SUPPORTED_10baseT_Full |
			   SUPPORTED_100baseT_Half |
			   SUPPORTED_100baseT_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_2500baseX_Full |
			   SUPPORTED_10000baseT_Full |
			   SUPPORTED_FIBRE |
			   SUPPORTED_Autoneg |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
Y
Yaniv Rosner 已提交
10638
	.media_type	= ETH_PHY_CX4,
Y
Yaniv Rosner 已提交
10639 10640
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
Y
Yaniv Rosner 已提交
10641 10642
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
Y
Yaniv Rosner 已提交
10643 10644
	.req_duplex	= 0,
	.rsrv		= 0,
Y
Yaniv Rosner 已提交
10645
	.config_init	= (config_init_t)bnx2x_xgxs_config_init,
Y
Yaniv Rosner 已提交
10646 10647 10648 10649 10650
	.read_status	= (read_status_t)bnx2x_link_settings_status,
	.link_reset	= (link_reset_t)bnx2x_int_link_reset,
	.config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
	.format_fw_ver	= (format_fw_ver_t)NULL,
	.hw_reset	= (hw_reset_t)NULL,
Y
Yaniv Rosner 已提交
10651 10652
	.set_link_led	= (set_link_led_t)NULL,
	.phy_specific_func = (phy_specific_func_t)NULL
Y
Yaniv Rosner 已提交
10653
};
10654 10655 10656 10657
static struct bnx2x_phy phy_warpcore = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
	.addr		= 0xff,
	.def_md_devad	= 0,
10658
	.flags		= FLAGS_HW_LOCK_REQUIRED,
10659 10660 10661 10662 10663 10664 10665 10666 10667 10668 10669 10670 10671 10672 10673 10674 10675 10676 10677 10678 10679 10680 10681 10682 10683 10684 10685
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10baseT_Half |
			     SUPPORTED_10baseT_Full |
			     SUPPORTED_100baseT_Half |
			     SUPPORTED_100baseT_Full |
			     SUPPORTED_1000baseT_Full |
			     SUPPORTED_10000baseT_Full |
			     SUPPORTED_20000baseKR2_Full |
			     SUPPORTED_20000baseMLD2_Full |
			     SUPPORTED_FIBRE |
			     SUPPORTED_Autoneg |
			     SUPPORTED_Pause |
			     SUPPORTED_Asym_Pause),
	.media_type	= ETH_PHY_UNSPECIFIED,
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
	/* req_duplex = */0,
	/* rsrv = */0,
	.config_init	= (config_init_t)bnx2x_warpcore_config_init,
	.read_status	= (read_status_t)bnx2x_warpcore_read_status,
	.link_reset	= (link_reset_t)bnx2x_warpcore_link_reset,
	.config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
	.format_fw_ver	= (format_fw_ver_t)NULL,
10686
	.hw_reset	= (hw_reset_t)bnx2x_warpcore_hw_reset,
10687 10688 10689 10690
	.set_link_led	= (set_link_led_t)NULL,
	.phy_specific_func = (phy_specific_func_t)NULL
};

Y
Yaniv Rosner 已提交
10691 10692 10693 10694 10695

static struct bnx2x_phy phy_7101 = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
	.addr		= 0xff,
	.def_md_devad	= 0,
10696
	.flags		= FLAGS_FAN_FAILURE_DET_REQ,
Y
Yaniv Rosner 已提交
10697 10698 10699 10700 10701 10702 10703 10704 10705 10706 10707
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10000baseT_Full |
			   SUPPORTED_TP |
			   SUPPORTED_Autoneg |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.media_type	= ETH_PHY_BASE_T,
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
Y
Yaniv Rosner 已提交
10708 10709
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
Y
Yaniv Rosner 已提交
10710 10711 10712 10713 10714 10715 10716 10717
	.req_duplex	= 0,
	.rsrv		= 0,
	.config_init	= (config_init_t)bnx2x_7101_config_init,
	.read_status	= (read_status_t)bnx2x_7101_read_status,
	.link_reset	= (link_reset_t)bnx2x_common_ext_link_reset,
	.config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
	.format_fw_ver	= (format_fw_ver_t)bnx2x_7101_format_ver,
	.hw_reset	= (hw_reset_t)bnx2x_7101_hw_reset,
10718
	.set_link_led	= (set_link_led_t)bnx2x_7101_set_link_led,
Y
Yaniv Rosner 已提交
10719
	.phy_specific_func = (phy_specific_func_t)NULL
Y
Yaniv Rosner 已提交
10720 10721 10722 10723 10724
};
static struct bnx2x_phy phy_8073 = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
	.addr		= 0xff,
	.def_md_devad	= 0,
10725
	.flags		= FLAGS_HW_LOCK_REQUIRED,
Y
Yaniv Rosner 已提交
10726 10727 10728 10729 10730 10731 10732 10733 10734 10735
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10000baseT_Full |
			   SUPPORTED_2500baseX_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_FIBRE |
			   SUPPORTED_Autoneg |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
Y
Yaniv Rosner 已提交
10736
	.media_type	= ETH_PHY_KR,
Y
Yaniv Rosner 已提交
10737
	.ver_addr	= 0,
Y
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10738 10739 10740
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
Y
Yaniv Rosner 已提交
10741 10742
	.req_duplex	= 0,
	.rsrv		= 0,
10743
	.config_init	= (config_init_t)bnx2x_8073_config_init,
Y
Yaniv Rosner 已提交
10744 10745 10746 10747 10748
	.read_status	= (read_status_t)bnx2x_8073_read_status,
	.link_reset	= (link_reset_t)bnx2x_8073_link_reset,
	.config_loopback = (config_loopback_t)NULL,
	.format_fw_ver	= (format_fw_ver_t)bnx2x_format_ver,
	.hw_reset	= (hw_reset_t)NULL,
Y
Yaniv Rosner 已提交
10749 10750
	.set_link_led	= (set_link_led_t)NULL,
	.phy_specific_func = (phy_specific_func_t)NULL
Y
Yaniv Rosner 已提交
10751 10752 10753 10754 10755
};
static struct bnx2x_phy phy_8705 = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
	.addr		= 0xff,
	.def_md_devad	= 0,
10756
	.flags		= FLAGS_INIT_XGXS_FIRST,
Y
Yaniv Rosner 已提交
10757 10758 10759 10760 10761 10762 10763 10764 10765 10766 10767 10768 10769 10770 10771 10772 10773 10774 10775 10776
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10000baseT_Full |
			   SUPPORTED_FIBRE |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.media_type	= ETH_PHY_XFP_FIBER,
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
	.req_duplex	= 0,
	.rsrv		= 0,
	.config_init	= (config_init_t)bnx2x_8705_config_init,
	.read_status	= (read_status_t)bnx2x_8705_read_status,
	.link_reset	= (link_reset_t)bnx2x_common_ext_link_reset,
	.config_loopback = (config_loopback_t)NULL,
	.format_fw_ver	= (format_fw_ver_t)bnx2x_null_format_ver,
	.hw_reset	= (hw_reset_t)NULL,
Y
Yaniv Rosner 已提交
10777 10778
	.set_link_led	= (set_link_led_t)NULL,
	.phy_specific_func = (phy_specific_func_t)NULL
Y
Yaniv Rosner 已提交
10779 10780 10781 10782 10783
};
static struct bnx2x_phy phy_8706 = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
	.addr		= 0xff,
	.def_md_devad	= 0,
10784
	.flags		= FLAGS_INIT_XGXS_FIRST,
Y
Yaniv Rosner 已提交
10785 10786 10787 10788 10789 10790 10791 10792 10793 10794 10795 10796 10797 10798 10799 10800 10801 10802 10803 10804 10805
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10000baseT_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_FIBRE |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.media_type	= ETH_PHY_SFP_FIBER,
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
	.req_duplex	= 0,
	.rsrv		= 0,
	.config_init	= (config_init_t)bnx2x_8706_config_init,
	.read_status	= (read_status_t)bnx2x_8706_read_status,
	.link_reset	= (link_reset_t)bnx2x_common_ext_link_reset,
	.config_loopback = (config_loopback_t)NULL,
	.format_fw_ver	= (format_fw_ver_t)bnx2x_format_ver,
	.hw_reset	= (hw_reset_t)NULL,
Y
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10806 10807
	.set_link_led	= (set_link_led_t)NULL,
	.phy_specific_func = (phy_specific_func_t)NULL
Y
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10808 10809 10810 10811 10812
};

static struct bnx2x_phy phy_8726 = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
	.addr		= 0xff,
10813
	.def_md_devad	= 0,
Y
Yaniv Rosner 已提交
10814
	.flags		= (FLAGS_HW_LOCK_REQUIRED |
10815
			   FLAGS_INIT_XGXS_FIRST),
Y
Yaniv Rosner 已提交
10816 10817 10818 10819 10820 10821 10822 10823 10824
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10000baseT_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_Autoneg |
			   SUPPORTED_FIBRE |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
Y
Yaniv Rosner 已提交
10825
	.media_type	= ETH_PHY_NOT_PRESENT,
Y
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10826 10827 10828 10829 10830 10831 10832 10833 10834 10835 10836 10837
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
	.req_duplex	= 0,
	.rsrv		= 0,
	.config_init	= (config_init_t)bnx2x_8726_config_init,
	.read_status	= (read_status_t)bnx2x_8726_read_status,
	.link_reset	= (link_reset_t)bnx2x_8726_link_reset,
	.config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
	.format_fw_ver	= (format_fw_ver_t)bnx2x_format_ver,
	.hw_reset	= (hw_reset_t)NULL,
Y
Yaniv Rosner 已提交
10838 10839
	.set_link_led	= (set_link_led_t)NULL,
	.phy_specific_func = (phy_specific_func_t)NULL
Y
Yaniv Rosner 已提交
10840 10841 10842 10843 10844 10845
};

static struct bnx2x_phy phy_8727 = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
	.addr		= 0xff,
	.def_md_devad	= 0,
10846
	.flags		= FLAGS_FAN_FAILURE_DET_REQ,
Y
Yaniv Rosner 已提交
10847 10848 10849 10850 10851 10852 10853 10854
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10000baseT_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_FIBRE |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
Y
Yaniv Rosner 已提交
10855
	.media_type	= ETH_PHY_NOT_PRESENT,
Y
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10856 10857 10858 10859 10860 10861 10862 10863 10864 10865 10866 10867
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
	.req_duplex	= 0,
	.rsrv		= 0,
	.config_init	= (config_init_t)bnx2x_8727_config_init,
	.read_status	= (read_status_t)bnx2x_8727_read_status,
	.link_reset	= (link_reset_t)bnx2x_8727_link_reset,
	.config_loopback = (config_loopback_t)NULL,
	.format_fw_ver	= (format_fw_ver_t)bnx2x_format_ver,
	.hw_reset	= (hw_reset_t)bnx2x_8727_hw_reset,
10868
	.set_link_led	= (set_link_led_t)bnx2x_8727_set_link_led,
Y
Yaniv Rosner 已提交
10869
	.phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
Y
Yaniv Rosner 已提交
10870 10871 10872 10873
};
static struct bnx2x_phy phy_8481 = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
	.addr		= 0xff,
10874
	.def_md_devad	= 0,
Y
Yaniv Rosner 已提交
10875 10876
	.flags		= FLAGS_FAN_FAILURE_DET_REQ |
			  FLAGS_REARM_LATCH_SIGNAL,
Y
Yaniv Rosner 已提交
10877 10878 10879 10880 10881 10882 10883 10884 10885 10886 10887 10888 10889 10890 10891 10892 10893 10894 10895 10896 10897 10898 10899 10900 10901 10902
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10baseT_Half |
			   SUPPORTED_10baseT_Full |
			   SUPPORTED_100baseT_Half |
			   SUPPORTED_100baseT_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_10000baseT_Full |
			   SUPPORTED_TP |
			   SUPPORTED_Autoneg |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.media_type	= ETH_PHY_BASE_T,
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
	.req_duplex	= 0,
	.rsrv		= 0,
	.config_init	= (config_init_t)bnx2x_8481_config_init,
	.read_status	= (read_status_t)bnx2x_848xx_read_status,
	.link_reset	= (link_reset_t)bnx2x_8481_link_reset,
	.config_loopback = (config_loopback_t)NULL,
	.format_fw_ver	= (format_fw_ver_t)bnx2x_848xx_format_ver,
	.hw_reset	= (hw_reset_t)bnx2x_8481_hw_reset,
10903
	.set_link_led	= (set_link_led_t)bnx2x_848xx_set_link_led,
Y
Yaniv Rosner 已提交
10904
	.phy_specific_func = (phy_specific_func_t)NULL
Y
Yaniv Rosner 已提交
10905 10906
};

Y
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10907 10908 10909
static struct bnx2x_phy phy_84823 = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
	.addr		= 0xff,
10910
	.def_md_devad	= 0,
Y
Yaniv Rosner 已提交
10911 10912
	.flags		= FLAGS_FAN_FAILURE_DET_REQ |
			  FLAGS_REARM_LATCH_SIGNAL,
Y
Yaniv Rosner 已提交
10913 10914 10915 10916 10917 10918 10919 10920 10921 10922 10923 10924 10925 10926 10927 10928 10929 10930 10931 10932 10933 10934 10935 10936 10937 10938
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10baseT_Half |
			   SUPPORTED_10baseT_Full |
			   SUPPORTED_100baseT_Half |
			   SUPPORTED_100baseT_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_10000baseT_Full |
			   SUPPORTED_TP |
			   SUPPORTED_Autoneg |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.media_type	= ETH_PHY_BASE_T,
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
	.req_duplex	= 0,
	.rsrv		= 0,
	.config_init	= (config_init_t)bnx2x_848x3_config_init,
	.read_status	= (read_status_t)bnx2x_848xx_read_status,
	.link_reset	= (link_reset_t)bnx2x_848x3_link_reset,
	.config_loopback = (config_loopback_t)NULL,
	.format_fw_ver	= (format_fw_ver_t)bnx2x_848xx_format_ver,
	.hw_reset	= (hw_reset_t)NULL,
10939
	.set_link_led	= (set_link_led_t)bnx2x_848xx_set_link_led,
Y
Yaniv Rosner 已提交
10940
	.phy_specific_func = (phy_specific_func_t)NULL
Y
Yaniv Rosner 已提交
10941 10942
};

10943 10944 10945
static struct bnx2x_phy phy_84833 = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
	.addr		= 0xff,
10946
	.def_md_devad	= 0,
10947 10948 10949 10950 10951
	.flags		= FLAGS_FAN_FAILURE_DET_REQ |
			    FLAGS_REARM_LATCH_SIGNAL,
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
10952
	.supported	= (SUPPORTED_100baseT_Half |
10953 10954 10955 10956 10957 10958 10959 10960 10961 10962 10963 10964 10965 10966 10967 10968 10969 10970 10971
			   SUPPORTED_100baseT_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_10000baseT_Full |
			   SUPPORTED_TP |
			   SUPPORTED_Autoneg |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.media_type	= ETH_PHY_BASE_T,
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
	.req_duplex	= 0,
	.rsrv		= 0,
	.config_init	= (config_init_t)bnx2x_848x3_config_init,
	.read_status	= (read_status_t)bnx2x_848xx_read_status,
	.link_reset	= (link_reset_t)bnx2x_848x3_link_reset,
	.config_loopback = (config_loopback_t)NULL,
	.format_fw_ver	= (format_fw_ver_t)bnx2x_848xx_format_ver,
10972
	.hw_reset	= (hw_reset_t)bnx2x_84833_hw_reset_phy,
10973 10974 10975 10976
	.set_link_led	= (set_link_led_t)bnx2x_848xx_set_link_led,
	.phy_specific_func = (phy_specific_func_t)NULL
};

10977 10978
static struct bnx2x_phy phy_54618se = {
	.type		= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
Y
Yaniv Rosner 已提交
10979 10980 10981 10982 10983 10984 10985 10986 10987 10988 10989 10990 10991 10992 10993 10994 10995 10996 10997 10998 10999 11000
	.addr		= 0xff,
	.def_md_devad	= 0,
	.flags		= FLAGS_INIT_XGXS_FIRST,
	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
	.mdio_ctrl	= 0,
	.supported	= (SUPPORTED_10baseT_Half |
			   SUPPORTED_10baseT_Full |
			   SUPPORTED_100baseT_Half |
			   SUPPORTED_100baseT_Full |
			   SUPPORTED_1000baseT_Full |
			   SUPPORTED_TP |
			   SUPPORTED_Autoneg |
			   SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.media_type	= ETH_PHY_BASE_T,
	.ver_addr	= 0,
	.req_flow_ctrl	= 0,
	.req_line_speed	= 0,
	.speed_cap_mask	= 0,
	/* req_duplex = */0,
	/* rsrv = */0,
11001 11002 11003 11004
	.config_init	= (config_init_t)bnx2x_54618se_config_init,
	.read_status	= (read_status_t)bnx2x_54618se_read_status,
	.link_reset	= (link_reset_t)bnx2x_54618se_link_reset,
	.config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
Y
Yaniv Rosner 已提交
11005 11006
	.format_fw_ver	= (format_fw_ver_t)NULL,
	.hw_reset	= (hw_reset_t)NULL,
11007
	.set_link_led	= (set_link_led_t)bnx2x_54618se_set_link_led,
Y
Yaniv Rosner 已提交
11008 11009
	.phy_specific_func = (phy_specific_func_t)NULL
};
Y
Yaniv Rosner 已提交
11010 11011 11012 11013 11014 11015 11016 11017 11018 11019 11020 11021 11022
/*****************************************************************/
/*                                                               */
/* Populate the phy according. Main function: bnx2x_populate_phy   */
/*                                                               */
/*****************************************************************/

static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
				     struct bnx2x_phy *phy, u8 port,
				     u8 phy_index)
{
	/* Get the 4 lanes xgxs config rx and tx */
	u32 rx = 0, tx = 0, i;
	for (i = 0; i < 2; i++) {
11023
		/*
Y
Yaniv Rosner 已提交
11024 11025 11026 11027
		 * INT_PHY and EXT_PHY1 share the same value location in the
		 * shmem. When num_phys is greater than 1, than this value
		 * applies only to EXT_PHY1
		 */
Y
Yaniv Rosner 已提交
11028 11029 11030
		if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
			rx = REG_RD(bp, shmem_base +
				    offsetof(struct shmem_region,
Y
Yaniv Rosner 已提交
11031
			  dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
Y
Yaniv Rosner 已提交
11032 11033 11034

			tx = REG_RD(bp, shmem_base +
				    offsetof(struct shmem_region,
Y
Yaniv Rosner 已提交
11035
			  dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
Y
Yaniv Rosner 已提交
11036 11037 11038
		} else {
			rx = REG_RD(bp, shmem_base +
				    offsetof(struct shmem_region,
Y
Yaniv Rosner 已提交
11039
			 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
Y
Yaniv Rosner 已提交
11040

Y
Yaniv Rosner 已提交
11041 11042
			tx = REG_RD(bp, shmem_base +
				    offsetof(struct shmem_region,
Y
Yaniv Rosner 已提交
11043
			 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
Y
Yaniv Rosner 已提交
11044
		}
Y
Yaniv Rosner 已提交
11045 11046 11047 11048 11049 11050 11051 11052 11053 11054 11055 11056 11057 11058 11059 11060 11061 11062 11063

		phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
		phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);

		phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
		phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
	}
}

static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
				    u8 phy_index, u8 port)
{
	u32 ext_phy_config = 0;
	switch (phy_index) {
	case EXT_PHY1:
		ext_phy_config = REG_RD(bp, shmem_base +
					      offsetof(struct shmem_region,
			dev_info.port_hw_config[port].external_phy_config));
		break;
Y
Yaniv Rosner 已提交
11064 11065 11066 11067 11068
	case EXT_PHY2:
		ext_phy_config = REG_RD(bp, shmem_base +
					      offsetof(struct shmem_region,
			dev_info.port_hw_config[port].external_phy_config2));
		break;
Y
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11069 11070 11071 11072 11073 11074 11075
	default:
		DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
		return -EINVAL;
	}

	return ext_phy_config;
}
Y
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11076 11077
static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
				  struct bnx2x_phy *phy)
Y
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11078 11079 11080 11081 11082 11083 11084 11085
{
	u32 phy_addr;
	u32 chip_id;
	u32 switch_cfg = (REG_RD(bp, shmem_base +
				       offsetof(struct shmem_region,
			dev_info.port_feature_config[port].link_config)) &
			  PORT_FEATURE_CONNECTED_SWITCH_MASK);
	chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11086 11087 11088
	DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
	if (USES_WARPCORE(bp)) {
		u32 serdes_net_if;
Y
Yaniv Rosner 已提交
11089
		phy_addr = REG_RD(bp,
11090 11091 11092 11093 11094 11095 11096 11097 11098 11099 11100 11101 11102 11103 11104 11105 11106 11107 11108 11109 11110 11111 11112 11113 11114 11115 11116 11117 11118 11119 11120 11121 11122 11123 11124 11125 11126 11127 11128 11129 11130 11131 11132 11133 11134 11135 11136 11137 11138 11139 11140 11141 11142 11143 11144 11145 11146 11147 11148 11149 11150 11151 11152 11153 11154 11155 11156 11157 11158 11159 11160 11161 11162 11163 11164 11165 11166
				  MISC_REG_WC0_CTRL_PHY_ADDR);
		*phy = phy_warpcore;
		if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
			phy->flags |= FLAGS_4_PORT_MODE;
		else
			phy->flags &= ~FLAGS_4_PORT_MODE;
			/* Check Dual mode */
		serdes_net_if = (REG_RD(bp, shmem_base +
					offsetof(struct shmem_region, dev_info.
					port_hw_config[port].default_cfg)) &
				 PORT_HW_CFG_NET_SERDES_IF_MASK);
		/*
		 * Set the appropriate supported and flags indications per
		 * interface type of the chip
		 */
		switch (serdes_net_if) {
		case PORT_HW_CFG_NET_SERDES_IF_SGMII:
			phy->supported &= (SUPPORTED_10baseT_Half |
					   SUPPORTED_10baseT_Full |
					   SUPPORTED_100baseT_Half |
					   SUPPORTED_100baseT_Full |
					   SUPPORTED_1000baseT_Full |
					   SUPPORTED_FIBRE |
					   SUPPORTED_Autoneg |
					   SUPPORTED_Pause |
					   SUPPORTED_Asym_Pause);
			phy->media_type = ETH_PHY_BASE_T;
			break;
		case PORT_HW_CFG_NET_SERDES_IF_XFI:
			phy->media_type = ETH_PHY_XFP_FIBER;
			break;
		case PORT_HW_CFG_NET_SERDES_IF_SFI:
			phy->supported &= (SUPPORTED_1000baseT_Full |
					   SUPPORTED_10000baseT_Full |
					   SUPPORTED_FIBRE |
					   SUPPORTED_Pause |
					   SUPPORTED_Asym_Pause);
			phy->media_type = ETH_PHY_SFP_FIBER;
			break;
		case PORT_HW_CFG_NET_SERDES_IF_KR:
			phy->media_type = ETH_PHY_KR;
			phy->supported &= (SUPPORTED_1000baseT_Full |
					   SUPPORTED_10000baseT_Full |
					   SUPPORTED_FIBRE |
					   SUPPORTED_Autoneg |
					   SUPPORTED_Pause |
					   SUPPORTED_Asym_Pause);
			break;
		case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
			phy->media_type = ETH_PHY_KR;
			phy->flags |= FLAGS_WC_DUAL_MODE;
			phy->supported &= (SUPPORTED_20000baseMLD2_Full |
					   SUPPORTED_FIBRE |
					   SUPPORTED_Pause |
					   SUPPORTED_Asym_Pause);
			break;
		case PORT_HW_CFG_NET_SERDES_IF_KR2:
			phy->media_type = ETH_PHY_KR;
			phy->flags |= FLAGS_WC_DUAL_MODE;
			phy->supported &= (SUPPORTED_20000baseKR2_Full |
					   SUPPORTED_FIBRE |
					   SUPPORTED_Pause |
					   SUPPORTED_Asym_Pause);
			break;
		default:
			DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
				       serdes_net_if);
			break;
		}

		/*
		 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
		 * was not set as expected. For B0, ECO will be enabled so there
		 * won't be an issue there
		 */
		if (CHIP_REV(bp) == CHIP_REV_Ax)
			phy->flags |= FLAGS_MDC_MDIO_WA;
11167 11168
		else
			phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11169 11170 11171 11172 11173 11174 11175 11176 11177 11178 11179 11180 11181 11182 11183 11184 11185 11186
	} else {
		switch (switch_cfg) {
		case SWITCH_CFG_1G:
			phy_addr = REG_RD(bp,
					  NIG_REG_SERDES0_CTRL_PHY_ADDR +
					  port * 0x10);
			*phy = phy_serdes;
			break;
		case SWITCH_CFG_10G:
			phy_addr = REG_RD(bp,
					  NIG_REG_XGXS0_CTRL_PHY_ADDR +
					  port * 0x18);
			*phy = phy_xgxs;
			break;
		default:
			DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
			return -EINVAL;
		}
Y
Yaniv Rosner 已提交
11187 11188 11189 11190 11191
	}
	phy->addr = (u8)phy_addr;
	phy->mdio_ctrl = bnx2x_get_emac_base(bp,
					    SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
					    port);
D
Dmitry Kravkov 已提交
11192 11193 11194 11195
	if (CHIP_IS_E2(bp))
		phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
	else
		phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
Y
Yaniv Rosner 已提交
11196 11197 11198 11199 11200 11201 11202 11203

	DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
		   port, phy->addr, phy->mdio_ctrl);

	bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
	return 0;
}

Y
Yaniv Rosner 已提交
11204 11205 11206 11207 11208 11209
static int bnx2x_populate_ext_phy(struct bnx2x *bp,
				  u8 phy_index,
				  u32 shmem_base,
				  u32 shmem2_base,
				  u8 port,
				  struct bnx2x_phy *phy)
Y
Yaniv Rosner 已提交
11210 11211 11212 11213 11214 11215 11216 11217 11218 11219 11220 11221 11222 11223 11224 11225 11226 11227 11228 11229 11230 11231 11232 11233 11234 11235 11236 11237
{
	u32 ext_phy_config, phy_type, config2;
	u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
	ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
						  phy_index, port);
	phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
	/* Select the phy type */
	switch (phy_type) {
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
		mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
		*phy = phy_8073;
		break;
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
		*phy = phy_8705;
		break;
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
		*phy = phy_8706;
		break;
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
		mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
		*phy = phy_8726;
		break;
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
		/* BCM8727_NOC => BCM8727 no over current */
		mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
		*phy = phy_8727;
		phy->flags |= FLAGS_NOC;
		break;
Y
Yaniv Rosner 已提交
11238
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
Y
Yaniv Rosner 已提交
11239 11240 11241 11242 11243 11244 11245 11246 11247 11248
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
		mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
		*phy = phy_8727;
		break;
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
		*phy = phy_8481;
		break;
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
		*phy = phy_84823;
		break;
11249 11250 11251
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
		*phy = phy_84833;
		break;
Y
Yaniv Rosner 已提交
11252
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11253 11254
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
		*phy = phy_54618se;
Y
Yaniv Rosner 已提交
11255
		break;
Y
Yaniv Rosner 已提交
11256 11257 11258 11259 11260 11261 11262 11263 11264 11265 11266 11267 11268 11269
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
		*phy = phy_7101;
		break;
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
		*phy = phy_null;
		return -EINVAL;
	default:
		*phy = phy_null;
		return 0;
	}

	phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
	bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);

11270 11271 11272 11273 11274
	/*
	 * The shmem address of the phy version is located on different
	 * structures. In case this structure is too old, do not set
	 * the address
	 */
Y
Yaniv Rosner 已提交
11275 11276
	config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
					dev_info.shared_hw_config.config2));
Y
Yaniv Rosner 已提交
11277 11278 11279
	if (phy_index == EXT_PHY1) {
		phy->ver_addr = shmem_base + offsetof(struct shmem_region,
				port_mb[port].ext_phy_fw_version);
Y
Yaniv Rosner 已提交
11280

Y
Yaniv Rosner 已提交
11281 11282 11283 11284
		/* Check specific mdc mdio settings */
		if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
			mdc_mdio_access = config2 &
			SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
Y
Yaniv Rosner 已提交
11285 11286
	} else {
		u32 size = REG_RD(bp, shmem2_base);
Y
Yaniv Rosner 已提交
11287

Y
Yaniv Rosner 已提交
11288 11289 11290 11291 11292 11293 11294 11295 11296 11297 11298 11299 11300
		if (size >
		    offsetof(struct shmem2_region, ext_phy_fw_version2)) {
			phy->ver_addr = shmem2_base +
			    offsetof(struct shmem2_region,
				     ext_phy_fw_version2[port]);
		}
		/* Check specific mdc mdio settings */
		if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
			mdc_mdio_access = (config2 &
			SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
			(SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
			 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
	}
Y
Yaniv Rosner 已提交
11301 11302
	phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);

11303
	/*
Y
Yaniv Rosner 已提交
11304 11305 11306 11307 11308 11309 11310 11311 11312 11313 11314 11315 11316
	 * In case mdc/mdio_access of the external phy is different than the
	 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
	 * to prevent one port interfere with another port's CL45 operations.
	 */
	if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
		phy->flags |= FLAGS_HW_LOCK_REQUIRED;
	DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
		   phy_type, port, phy_index);
	DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
		   phy->addr, phy->mdio_ctrl);
	return 0;
}

Y
Yaniv Rosner 已提交
11317 11318
static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
			      u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
Y
Yaniv Rosner 已提交
11319
{
Y
Yaniv Rosner 已提交
11320
	int status = 0;
Y
Yaniv Rosner 已提交
11321 11322 11323
	phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
	if (phy_index == INT_PHY)
		return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
Y
Yaniv Rosner 已提交
11324
	status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
Y
Yaniv Rosner 已提交
11325 11326 11327 11328 11329 11330
					port, phy);
	return status;
}

static void bnx2x_phy_def_cfg(struct link_params *params,
			      struct bnx2x_phy *phy,
Y
Yaniv Rosner 已提交
11331
			      u8 phy_index)
Y
Yaniv Rosner 已提交
11332 11333 11334 11335
{
	struct bnx2x *bp = params->bp;
	u32 link_config;
	/* Populate the default phy configuration for MF mode */
Y
Yaniv Rosner 已提交
11336 11337
	if (phy_index == EXT_PHY2) {
		link_config = REG_RD(bp, params->shmem_base +
Y
Yaniv Rosner 已提交
11338
				     offsetof(struct shmem_region, dev_info.
Y
Yaniv Rosner 已提交
11339 11340
			port_feature_config[params->port].link_config2));
		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
Y
Yaniv Rosner 已提交
11341 11342
					     offsetof(struct shmem_region,
						      dev_info.
Y
Yaniv Rosner 已提交
11343 11344 11345
			port_hw_config[params->port].speed_capability_mask2));
	} else {
		link_config = REG_RD(bp, params->shmem_base +
Y
Yaniv Rosner 已提交
11346
				     offsetof(struct shmem_region, dev_info.
Y
Yaniv Rosner 已提交
11347 11348
				port_feature_config[params->port].link_config));
		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
Y
Yaniv Rosner 已提交
11349 11350 11351
					     offsetof(struct shmem_region,
						      dev_info.
			port_hw_config[params->port].speed_capability_mask));
Y
Yaniv Rosner 已提交
11352
	}
11353 11354 11355
	DP(NETIF_MSG_LINK,
	   "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
	   phy_index, link_config, phy->speed_cap_mask);
Y
Yaniv Rosner 已提交
11356 11357 11358 11359 11360 11361 11362 11363 11364 11365 11366 11367 11368 11369 11370 11371 11372 11373 11374 11375 11376 11377 11378 11379 11380 11381 11382 11383 11384 11385 11386 11387 11388 11389 11390 11391 11392 11393 11394 11395 11396 11397 11398 11399 11400 11401

	phy->req_duplex = DUPLEX_FULL;
	switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
	case PORT_FEATURE_LINK_SPEED_10M_HALF:
		phy->req_duplex = DUPLEX_HALF;
	case PORT_FEATURE_LINK_SPEED_10M_FULL:
		phy->req_line_speed = SPEED_10;
		break;
	case PORT_FEATURE_LINK_SPEED_100M_HALF:
		phy->req_duplex = DUPLEX_HALF;
	case PORT_FEATURE_LINK_SPEED_100M_FULL:
		phy->req_line_speed = SPEED_100;
		break;
	case PORT_FEATURE_LINK_SPEED_1G:
		phy->req_line_speed = SPEED_1000;
		break;
	case PORT_FEATURE_LINK_SPEED_2_5G:
		phy->req_line_speed = SPEED_2500;
		break;
	case PORT_FEATURE_LINK_SPEED_10G_CX4:
		phy->req_line_speed = SPEED_10000;
		break;
	default:
		phy->req_line_speed = SPEED_AUTO_NEG;
		break;
	}

	switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
	case PORT_FEATURE_FLOW_CONTROL_AUTO:
		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
		break;
	case PORT_FEATURE_FLOW_CONTROL_TX:
		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
		break;
	case PORT_FEATURE_FLOW_CONTROL_RX:
		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
		break;
	case PORT_FEATURE_FLOW_CONTROL_BOTH:
		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
		break;
	default:
		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
		break;
	}
}

Y
Yaniv Rosner 已提交
11402 11403 11404 11405 11406 11407 11408 11409 11410 11411 11412 11413 11414 11415 11416 11417 11418 11419 11420 11421 11422 11423 11424 11425 11426 11427 11428 11429 11430 11431 11432 11433 11434
u32 bnx2x_phy_selection(struct link_params *params)
{
	u32 phy_config_swapped, prio_cfg;
	u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;

	phy_config_swapped = params->multi_phy_config &
		PORT_HW_CFG_PHY_SWAPPED_ENABLED;

	prio_cfg = params->multi_phy_config &
			PORT_HW_CFG_PHY_SELECTION_MASK;

	if (phy_config_swapped) {
		switch (prio_cfg) {
		case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
		     return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
		     break;
		case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
		     return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
		     break;
		case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
		     return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
		     break;
		case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
		     return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
		     break;
		}
	} else
		return_cfg = prio_cfg;

	return return_cfg;
}


Y
Yaniv Rosner 已提交
11435
int bnx2x_phy_probe(struct link_params *params)
Y
Yaniv Rosner 已提交
11436 11437
{
	u8 phy_index, actual_phy_idx, link_cfg_idx;
Y
Yaniv Rosner 已提交
11438
	u32 phy_config_swapped, sync_offset, media_types;
Y
Yaniv Rosner 已提交
11439 11440 11441 11442
	struct bnx2x *bp = params->bp;
	struct bnx2x_phy *phy;
	params->num_phys = 0;
	DP(NETIF_MSG_LINK, "Begin phy probe\n");
Y
Yaniv Rosner 已提交
11443 11444
	phy_config_swapped = params->multi_phy_config &
		PORT_HW_CFG_PHY_SWAPPED_ENABLED;
Y
Yaniv Rosner 已提交
11445 11446 11447 11448 11449

	for (phy_index = INT_PHY; phy_index < MAX_PHYS;
	      phy_index++) {
		link_cfg_idx = LINK_CONFIG_IDX(phy_index);
		actual_phy_idx = phy_index;
Y
Yaniv Rosner 已提交
11450 11451 11452 11453 11454 11455 11456 11457 11458
		if (phy_config_swapped) {
			if (phy_index == EXT_PHY1)
				actual_phy_idx = EXT_PHY2;
			else if (phy_index == EXT_PHY2)
				actual_phy_idx = EXT_PHY1;
		}
		DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
			       " actual_phy_idx %x\n", phy_config_swapped,
			   phy_index, actual_phy_idx);
Y
Yaniv Rosner 已提交
11459 11460
		phy = &params->phy[actual_phy_idx];
		if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
Y
Yaniv Rosner 已提交
11461
				       params->shmem2_base, params->port,
Y
Yaniv Rosner 已提交
11462 11463 11464 11465 11466 11467 11468 11469 11470 11471 11472 11473 11474
				       phy) != 0) {
			params->num_phys = 0;
			DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
				   phy_index);
			for (phy_index = INT_PHY;
			      phy_index < MAX_PHYS;
			      phy_index++)
				*phy = phy_null;
			return -EINVAL;
		}
		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
			break;

Y
Yaniv Rosner 已提交
11475 11476 11477 11478 11479 11480 11481 11482 11483 11484 11485 11486 11487 11488 11489 11490 11491 11492 11493 11494
		sync_offset = params->shmem_base +
			offsetof(struct shmem_region,
			dev_info.port_hw_config[params->port].media_type);
		media_types = REG_RD(bp, sync_offset);

		/*
		 * Update media type for non-PMF sync only for the first time
		 * In case the media type changes afterwards, it will be updated
		 * using the update_status function
		 */
		if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
				    (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
				     actual_phy_idx))) == 0) {
			media_types |= ((phy->media_type &
					PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
				(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
				 actual_phy_idx));
		}
		REG_WR(bp, sync_offset, media_types);

Y
Yaniv Rosner 已提交
11495
		bnx2x_phy_def_cfg(params, phy, phy_index);
Y
Yaniv Rosner 已提交
11496 11497 11498 11499 11500 11501 11502
		params->num_phys++;
	}

	DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
	return 0;
}

11503 11504
void bnx2x_init_bmac_loopback(struct link_params *params,
			      struct link_vars *vars)
Y
Yaniv Rosner 已提交
11505 11506 11507 11508 11509 11510 11511
{
	struct bnx2x *bp = params->bp;
		vars->link_up = 1;
		vars->line_speed = SPEED_10000;
		vars->duplex = DUPLEX_FULL;
		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
		vars->mac_type = MAC_TYPE_BMAC;
Y
Yaniv Rosner 已提交
11512

Y
Yaniv Rosner 已提交
11513
		vars->phy_flags = PHY_XGXS_FLAG;
Y
Yaniv Rosner 已提交
11514

Y
Yaniv Rosner 已提交
11515
		bnx2x_xgxs_deassert(params);
Y
Yaniv Rosner 已提交
11516

Y
Yaniv Rosner 已提交
11517 11518
		/* set bmac loopback */
		bnx2x_bmac_enable(params, vars, 1);
Y
Yaniv Rosner 已提交
11519

Y
Yaniv Rosner 已提交
11520
		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11521
}
Y
Yaniv Rosner 已提交
11522

11523 11524 11525 11526
void bnx2x_init_emac_loopback(struct link_params *params,
			      struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
11527 11528 11529 11530 11531
		vars->link_up = 1;
		vars->line_speed = SPEED_1000;
		vars->duplex = DUPLEX_FULL;
		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
		vars->mac_type = MAC_TYPE_EMAC;
Y
Yaniv Rosner 已提交
11532

Y
Yaniv Rosner 已提交
11533
		vars->phy_flags = PHY_XGXS_FLAG;
Y
Yaniv Rosner 已提交
11534

Y
Yaniv Rosner 已提交
11535 11536 11537 11538
		bnx2x_xgxs_deassert(params);
		/* set bmac loopback */
		bnx2x_emac_enable(params, vars, 1);
		bnx2x_emac_program(params, vars);
Y
Yaniv Rosner 已提交
11539
		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11540
}
Y
Yaniv Rosner 已提交
11541

11542 11543 11544 11545 11546 11547 11548 11549 11550 11551 11552 11553 11554 11555 11556 11557 11558
void bnx2x_init_xmac_loopback(struct link_params *params,
			      struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	vars->link_up = 1;
	if (!params->req_line_speed[0])
		vars->line_speed = SPEED_10000;
	else
		vars->line_speed = params->req_line_speed[0];
	vars->duplex = DUPLEX_FULL;
	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
	vars->mac_type = MAC_TYPE_XMAC;
	vars->phy_flags = PHY_XGXS_FLAG;
	/*
	 * Set WC to loopback mode since link is required to provide clock
	 * to the XMAC in 20G mode
	 */
Y
Yaniv Rosner 已提交
11559 11560 11561
	bnx2x_set_aer_mmd(params, &params->phy[0]);
	bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
	params->phy[INT_PHY].config_loopback(
11562 11563
			&params->phy[INT_PHY],
			params);
Y
Yaniv Rosner 已提交
11564

11565 11566 11567 11568 11569 11570 11571 11572 11573 11574 11575 11576 11577 11578 11579 11580 11581 11582 11583
	bnx2x_xmac_enable(params, vars, 1);
	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
}

void bnx2x_init_umac_loopback(struct link_params *params,
			      struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	vars->link_up = 1;
	vars->line_speed = SPEED_1000;
	vars->duplex = DUPLEX_FULL;
	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
	vars->mac_type = MAC_TYPE_UMAC;
	vars->phy_flags = PHY_XGXS_FLAG;
	bnx2x_umac_enable(params, vars, 1);

	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
}

11584 11585 11586 11587
void bnx2x_init_xgxs_loopback(struct link_params *params,
			      struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
11588 11589
		vars->link_up = 1;
		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
Y
Yaniv Rosner 已提交
11590
		vars->duplex = DUPLEX_FULL;
11591
	if (params->req_line_speed[0] == SPEED_1000)
Y
Yaniv Rosner 已提交
11592
			vars->line_speed = SPEED_1000;
11593
	else
Y
Yaniv Rosner 已提交
11594
			vars->line_speed = SPEED_10000;
11595

11596 11597
	if (!USES_WARPCORE(bp))
		bnx2x_xgxs_deassert(params);
11598 11599 11600
	bnx2x_link_initialize(params, vars);

	if (params->req_line_speed[0] == SPEED_1000) {
11601 11602 11603 11604 11605 11606 11607 11608 11609 11610 11611 11612
		if (USES_WARPCORE(bp))
			bnx2x_umac_enable(params, vars, 0);
		else {
			bnx2x_emac_program(params, vars);
			bnx2x_emac_enable(params, vars, 0);
		}
	} else {
		if (USES_WARPCORE(bp))
			bnx2x_xmac_enable(params, vars, 0);
		else
			bnx2x_bmac_enable(params, vars, 0);
	}
11613

Y
Yaniv Rosner 已提交
11614 11615 11616 11617 11618
		if (params->loopback_mode == LOOPBACK_XGXS) {
			/* set 10G XGXS loopback */
			params->phy[INT_PHY].config_loopback(
				&params->phy[INT_PHY],
				params);
11619

Y
Yaniv Rosner 已提交
11620 11621 11622 11623 11624 11625 11626 11627 11628 11629 11630
		} else {
			/* set external phy loopback */
			u8 phy_index;
			for (phy_index = EXT_PHY1;
			      phy_index < params->num_phys; phy_index++) {
				if (params->phy[phy_index].config_loopback)
					params->phy[phy_index].config_loopback(
						&params->phy[phy_index],
						params);
			}
		}
Y
Yaniv Rosner 已提交
11631
		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
Y
Yaniv Rosner 已提交
11632

11633 11634 11635 11636 11637 11638 11639 11640 11641 11642 11643 11644 11645 11646 11647 11648 11649 11650 11651 11652 11653 11654 11655 11656 11657 11658 11659 11660 11661 11662 11663 11664 11665 11666 11667 11668 11669 11670 11671 11672 11673 11674 11675
	bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
}

int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	DP(NETIF_MSG_LINK, "Phy Initialization started\n");
	DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
		   params->req_line_speed[0], params->req_flow_ctrl[0]);
	DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
		   params->req_line_speed[1], params->req_flow_ctrl[1]);
	vars->link_status = 0;
	vars->phy_link_up = 0;
	vars->link_up = 0;
	vars->line_speed = 0;
	vars->duplex = DUPLEX_FULL;
	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
	vars->mac_type = MAC_TYPE_NONE;
	vars->phy_flags = 0;

	/* disable attentions */
	bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
		       (NIG_MASK_XGXS0_LINK_STATUS |
			NIG_MASK_XGXS0_LINK10G |
			NIG_MASK_SERDES0_LINK_STATUS |
			NIG_MASK_MI_INT));

	bnx2x_emac_init(params, vars);

	if (params->num_phys == 0) {
		DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
		return -EINVAL;
	}
	set_phy_vars(params, vars);

	DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
	switch (params->loopback_mode) {
	case LOOPBACK_BMAC:
		bnx2x_init_bmac_loopback(params, vars);
		break;
	case LOOPBACK_EMAC:
		bnx2x_init_emac_loopback(params, vars);
		break;
11676 11677 11678 11679 11680 11681
	case LOOPBACK_XMAC:
		bnx2x_init_xmac_loopback(params, vars);
		break;
	case LOOPBACK_UMAC:
		bnx2x_init_umac_loopback(params, vars);
		break;
11682 11683 11684 11685 11686
	case LOOPBACK_XGXS:
	case LOOPBACK_EXT_PHY:
		bnx2x_init_xgxs_loopback(params, vars);
		break;
	default:
11687 11688 11689 11690 11691 11692
		if (!CHIP_IS_E3(bp)) {
			if (params->switch_cfg == SWITCH_CFG_10G)
				bnx2x_xgxs_deassert(params);
			else
				bnx2x_serdes_deassert(bp, params->port);
		}
Y
Yaniv Rosner 已提交
11693 11694 11695
		bnx2x_link_initialize(params, vars);
		msleep(30);
		bnx2x_link_int_enable(params);
11696
		break;
Y
Yaniv Rosner 已提交
11697
	}
Y
Yaniv Rosner 已提交
11698 11699
	return 0;
}
Y
Yaniv Rosner 已提交
11700 11701 11702

int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
		     u8 reset_ext_phy)
Y
Yaniv Rosner 已提交
11703 11704
{
	struct bnx2x *bp = params->bp;
11705
	u8 phy_index, port = params->port, clear_latch_ind = 0;
Y
Yaniv Rosner 已提交
11706 11707 11708 11709 11710
	DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
	/* disable attentions */
	vars->link_status = 0;
	bnx2x_update_mng(params, vars->link_status);
	bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
Y
Yaniv Rosner 已提交
11711 11712 11713 11714
		       (NIG_MASK_XGXS0_LINK_STATUS |
			NIG_MASK_XGXS0_LINK10G |
			NIG_MASK_SERDES0_LINK_STATUS |
			NIG_MASK_MI_INT));
Y
Yaniv Rosner 已提交
11715

Y
Yaniv Rosner 已提交
11716 11717
	/* activate nig drain */
	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
Y
Yaniv Rosner 已提交
11718

Y
Yaniv Rosner 已提交
11719
	/* disable nig egress interface */
11720 11721 11722 11723
	if (!CHIP_IS_E3(bp)) {
		REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
		REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
	}
Y
Yaniv Rosner 已提交
11724

Y
Yaniv Rosner 已提交
11725
	/* Stop BigMac rx */
11726 11727 11728 11729
	if (!CHIP_IS_E3(bp))
		bnx2x_bmac_rx_disable(bp, port);
	else
		bnx2x_xmac_disable(params);
Y
Yaniv Rosner 已提交
11730
	/* disable emac */
11731 11732
	if (!CHIP_IS_E3(bp))
		REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
Y
Yaniv Rosner 已提交
11733

Y
Yaniv Rosner 已提交
11734
	msleep(10);
L
Lucas De Marchi 已提交
11735
	/* The PHY reset is controlled by GPIO 1
Y
Yaniv Rosner 已提交
11736 11737 11738
	 * Hold it as vars low
	 */
	 /* clear link led */
11739 11740
	bnx2x_set_led(params, vars, LED_MODE_OFF, 0);

Y
Yaniv Rosner 已提交
11741
	if (reset_ext_phy) {
11742
		bnx2x_set_mdio_clk(bp, params->chip_id, port);
Y
Yaniv Rosner 已提交
11743 11744
		for (phy_index = EXT_PHY1; phy_index < params->num_phys;
		      phy_index++) {
11745 11746 11747
			if (params->phy[phy_index].link_reset) {
				bnx2x_set_aer_mmd(params,
						  &params->phy[phy_index]);
Y
Yaniv Rosner 已提交
11748 11749 11750
				params->phy[phy_index].link_reset(
					&params->phy[phy_index],
					params);
11751
			}
11752 11753 11754
			if (params->phy[phy_index].flags &
			    FLAGS_REARM_LATCH_SIGNAL)
				clear_latch_ind = 1;
Y
Yaniv Rosner 已提交
11755 11756 11757
		}
	}

11758 11759 11760 11761 11762 11763
	if (clear_latch_ind) {
		/* Clear latching indication */
		bnx2x_rearm_latch_signal(bp, port, 0);
		bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
			       1 << NIG_LATCH_BC_ENABLE_MI_INT);
	}
Y
Yaniv Rosner 已提交
11764 11765 11766 11767 11768 11769
	if (params->phy[INT_PHY].link_reset)
		params->phy[INT_PHY].link_reset(
			&params->phy[INT_PHY], params);
	/* reset BigMac */
	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
	       (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
Y
Yaniv Rosner 已提交
11770

Y
Yaniv Rosner 已提交
11771
	/* disable nig ingress interface */
11772 11773 11774 11775
	if (!CHIP_IS_E3(bp)) {
		REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
		REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
	}
Y
Yaniv Rosner 已提交
11776
	vars->link_up = 0;
11777
	vars->phy_flags = 0;
Y
Yaniv Rosner 已提交
11778 11779 11780
	return 0;
}

Y
Yaniv Rosner 已提交
11781 11782 11783
/****************************************************************************/
/*				Common function				    */
/****************************************************************************/
Y
Yaniv Rosner 已提交
11784 11785 11786 11787
static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
				      u32 shmem_base_path[],
				      u32 shmem2_base_path[], u8 phy_index,
				      u32 chip_id)
Y
Yaniv Rosner 已提交
11788
{
Y
Yaniv Rosner 已提交
11789 11790
	struct bnx2x_phy phy[PORT_MAX];
	struct bnx2x_phy *phy_blk[PORT_MAX];
Y
Yaniv Rosner 已提交
11791
	u16 val;
Y
Yaniv Rosner 已提交
11792
	s8 port = 0;
D
Dmitry Kravkov 已提交
11793
	s8 port_of_path = 0;
Y
Yaniv Rosner 已提交
11794 11795 11796 11797 11798
	u32 swap_val, swap_override;
	swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
	swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
	port ^= (swap_val && swap_override);
	bnx2x_ext_phy_hw_reset(bp, port);
Y
Yaniv Rosner 已提交
11799 11800
	/* PART1 - Reset both phys */
	for (port = PORT_MAX - 1; port >= PORT_0; port--) {
D
Dmitry Kravkov 已提交
11801 11802
		u32 shmem_base, shmem2_base;
		/* In E2, same phy is using for port0 of the two paths */
11803
		if (CHIP_IS_E1x(bp)) {
D
Dmitry Kravkov 已提交
11804 11805 11806
			shmem_base = shmem_base_path[0];
			shmem2_base = shmem2_base_path[0];
			port_of_path = port;
11807 11808 11809 11810
		} else {
			shmem_base = shmem_base_path[port];
			shmem2_base = shmem2_base_path[port];
			port_of_path = 0;
D
Dmitry Kravkov 已提交
11811 11812
		}

Y
Yaniv Rosner 已提交
11813
		/* Extract the ext phy address for the port */
Y
Yaniv Rosner 已提交
11814
		if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
D
Dmitry Kravkov 已提交
11815
				       port_of_path, &phy[port]) !=
Y
Yaniv Rosner 已提交
11816 11817 11818 11819
		    0) {
			DP(NETIF_MSG_LINK, "populate_phy failed\n");
			return -EINVAL;
		}
Y
Yaniv Rosner 已提交
11820
		/* disable attentions */
11821 11822
		bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
			       port_of_path*4,
Y
Yaniv Rosner 已提交
11823 11824 11825 11826
			       (NIG_MASK_XGXS0_LINK_STATUS |
				NIG_MASK_XGXS0_LINK10G |
				NIG_MASK_SERDES0_LINK_STATUS |
				NIG_MASK_MI_INT));
Y
Yaniv Rosner 已提交
11827 11828 11829 11830

		/* Need to take the phy out of low power mode in order
			to write to access its registers */
		bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Y
Yaniv Rosner 已提交
11831 11832
			       MISC_REGISTERS_GPIO_OUTPUT_HIGH,
			       port);
Y
Yaniv Rosner 已提交
11833 11834

		/* Reset the phy */
Y
Yaniv Rosner 已提交
11835
		bnx2x_cl45_write(bp, &phy[port],
Y
Yaniv Rosner 已提交
11836 11837 11838
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_CTRL,
				 1<<15);
Y
Yaniv Rosner 已提交
11839 11840 11841 11842 11843
	}

	/* Add delay of 150ms after reset */
	msleep(150);

Y
Yaniv Rosner 已提交
11844 11845 11846 11847 11848 11849 11850 11851
	if (phy[PORT_0].addr & 0x1) {
		phy_blk[PORT_0] = &(phy[PORT_1]);
		phy_blk[PORT_1] = &(phy[PORT_0]);
	} else {
		phy_blk[PORT_0] = &(phy[PORT_0]);
		phy_blk[PORT_1] = &(phy[PORT_1]);
	}

Y
Yaniv Rosner 已提交
11852 11853
	/* PART2 - Download firmware to both phys */
	for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11854
		if (CHIP_IS_E1x(bp))
D
Dmitry Kravkov 已提交
11855
			port_of_path = port;
11856 11857
		else
			port_of_path = 0;
Y
Yaniv Rosner 已提交
11858

D
Dmitry Kravkov 已提交
11859 11860
		DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
			   phy_blk[port]->addr);
11861 11862
		if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
						      port_of_path))
Y
Yaniv Rosner 已提交
11863 11864 11865
			return -EINVAL;

		/* Only set bit 10 = 1 (Tx power down) */
Y
Yaniv Rosner 已提交
11866
		bnx2x_cl45_read(bp, phy_blk[port],
Y
Yaniv Rosner 已提交
11867 11868
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_TX_POWER_DOWN, &val);
Y
Yaniv Rosner 已提交
11869 11870

		/* Phase1 of TX_POWER_DOWN reset */
Y
Yaniv Rosner 已提交
11871
		bnx2x_cl45_write(bp, phy_blk[port],
Y
Yaniv Rosner 已提交
11872 11873 11874
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_TX_POWER_DOWN,
				 (val | 1<<10));
Y
Yaniv Rosner 已提交
11875 11876
	}

11877 11878 11879 11880
	/*
	 * Toggle Transmitter: Power down and then up with 600ms delay
	 * between
	 */
Y
Yaniv Rosner 已提交
11881 11882 11883 11884
	msleep(600);

	/* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
	for (port = PORT_MAX - 1; port >= PORT_0; port--) {
E
Eilon Greenstein 已提交
11885
		/* Phase2 of POWER_DOWN_RESET */
Y
Yaniv Rosner 已提交
11886
		/* Release bit 10 (Release Tx power down) */
Y
Yaniv Rosner 已提交
11887
		bnx2x_cl45_read(bp, phy_blk[port],
Y
Yaniv Rosner 已提交
11888 11889
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_TX_POWER_DOWN, &val);
Y
Yaniv Rosner 已提交
11890

Y
Yaniv Rosner 已提交
11891
		bnx2x_cl45_write(bp, phy_blk[port],
Y
Yaniv Rosner 已提交
11892 11893
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
Y
Yaniv Rosner 已提交
11894 11895 11896
		msleep(15);

		/* Read modify write the SPI-ROM version select register */
Y
Yaniv Rosner 已提交
11897
		bnx2x_cl45_read(bp, phy_blk[port],
Y
Yaniv Rosner 已提交
11898 11899
				MDIO_PMA_DEVAD,
				MDIO_PMA_REG_EDC_FFE_MAIN, &val);
Y
Yaniv Rosner 已提交
11900
		bnx2x_cl45_write(bp, phy_blk[port],
Y
Yaniv Rosner 已提交
11901 11902
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
Y
Yaniv Rosner 已提交
11903 11904 11905

		/* set GPIO2 back to LOW */
		bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
Y
Yaniv Rosner 已提交
11906
			       MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
Y
Yaniv Rosner 已提交
11907 11908 11909
	}
	return 0;
}
Y
Yaniv Rosner 已提交
11910 11911 11912 11913
static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
				      u32 shmem_base_path[],
				      u32 shmem2_base_path[], u8 phy_index,
				      u32 chip_id)
Y
Yaniv Rosner 已提交
11914 11915 11916 11917 11918 11919 11920 11921 11922 11923 11924
{
	u32 val;
	s8 port;
	struct bnx2x_phy phy;
	/* Use port1 because of the static port-swap */
	/* Enable the module detection interrupt */
	val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
	val |= ((1<<MISC_REGISTERS_GPIO_3)|
		(1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
	REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);

11925
	bnx2x_ext_phy_hw_reset(bp, 0);
Y
Yaniv Rosner 已提交
11926 11927
	msleep(5);
	for (port = 0; port < PORT_MAX; port++) {
D
Dmitry Kravkov 已提交
11928 11929 11930
		u32 shmem_base, shmem2_base;

		/* In E2, same phy is using for port0 of the two paths */
11931
		if (CHIP_IS_E1x(bp)) {
D
Dmitry Kravkov 已提交
11932 11933
			shmem_base = shmem_base_path[0];
			shmem2_base = shmem2_base_path[0];
11934 11935 11936
		} else {
			shmem_base = shmem_base_path[port];
			shmem2_base = shmem2_base_path[port];
D
Dmitry Kravkov 已提交
11937
		}
Y
Yaniv Rosner 已提交
11938
		/* Extract the ext phy address for the port */
Y
Yaniv Rosner 已提交
11939
		if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
Y
Yaniv Rosner 已提交
11940 11941 11942 11943 11944 11945 11946 11947 11948 11949 11950 11951 11952
				       port, &phy) !=
		    0) {
			DP(NETIF_MSG_LINK, "populate phy failed\n");
			return -EINVAL;
		}

		/* Reset phy*/
		bnx2x_cl45_write(bp, &phy,
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);


		/* Set fault module detected LED on */
		bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
Y
Yaniv Rosner 已提交
11953 11954
			       MISC_REGISTERS_GPIO_HIGH,
			       port);
Y
Yaniv Rosner 已提交
11955 11956 11957 11958
	}

	return 0;
}
11959 11960 11961 11962 11963 11964 11965 11966 11967 11968 11969 11970 11971 11972 11973 11974 11975 11976 11977 11978 11979 11980 11981 11982 11983 11984 11985 11986 11987 11988 11989 11990 11991 11992 11993 11994 11995 11996 11997 11998 11999 12000 12001 12002 12003
static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
					 u8 *io_gpio, u8 *io_port)
{

	u32 phy_gpio_reset = REG_RD(bp, shmem_base +
					  offsetof(struct shmem_region,
				dev_info.port_hw_config[PORT_0].default_cfg));
	switch (phy_gpio_reset) {
	case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
		*io_gpio = 0;
		*io_port = 0;
		break;
	case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
		*io_gpio = 1;
		*io_port = 0;
		break;
	case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
		*io_gpio = 2;
		*io_port = 0;
		break;
	case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
		*io_gpio = 3;
		*io_port = 0;
		break;
	case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
		*io_gpio = 0;
		*io_port = 1;
		break;
	case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
		*io_gpio = 1;
		*io_port = 1;
		break;
	case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
		*io_gpio = 2;
		*io_port = 1;
		break;
	case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
		*io_gpio = 3;
		*io_port = 1;
		break;
	default:
		/* Don't override the io_gpio and io_port */
		break;
	}
}
Y
Yaniv Rosner 已提交
12004 12005 12006 12007 12008

static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
				      u32 shmem_base_path[],
				      u32 shmem2_base_path[], u8 phy_index,
				      u32 chip_id)
E
Eilon Greenstein 已提交
12009
{
12010
	s8 port, reset_gpio;
E
Eilon Greenstein 已提交
12011
	u32 swap_val, swap_override;
Y
Yaniv Rosner 已提交
12012 12013
	struct bnx2x_phy phy[PORT_MAX];
	struct bnx2x_phy *phy_blk[PORT_MAX];
D
Dmitry Kravkov 已提交
12014
	s8 port_of_path;
Y
Yaniv Rosner 已提交
12015 12016
	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
E
Eilon Greenstein 已提交
12017

12018
	reset_gpio = MISC_REGISTERS_GPIO_1;
Y
Yaniv Rosner 已提交
12019
	port = 1;
E
Eilon Greenstein 已提交
12020

12021 12022 12023 12024 12025 12026
	/*
	 * Retrieve the reset gpio/port which control the reset.
	 * Default is GPIO1, PORT1
	 */
	bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
				     (u8 *)&reset_gpio, (u8 *)&port);
Y
Yaniv Rosner 已提交
12027 12028 12029 12030

	/* Calculate the port based on port swap */
	port ^= (swap_val && swap_override);

12031 12032 12033 12034 12035 12036 12037
	/* Initiate PHY reset*/
	bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
		       port);
	msleep(1);
	bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
		       port);

Y
Yaniv Rosner 已提交
12038
	msleep(5);
E
Eilon Greenstein 已提交
12039

E
Eilon Greenstein 已提交
12040
	/* PART1 - Reset both phys */
Y
Yaniv Rosner 已提交
12041
	for (port = PORT_MAX - 1; port >= PORT_0; port--) {
D
Dmitry Kravkov 已提交
12042 12043 12044
		u32 shmem_base, shmem2_base;

		/* In E2, same phy is using for port0 of the two paths */
12045
		if (CHIP_IS_E1x(bp)) {
D
Dmitry Kravkov 已提交
12046 12047 12048
			shmem_base = shmem_base_path[0];
			shmem2_base = shmem2_base_path[0];
			port_of_path = port;
12049 12050 12051 12052
		} else {
			shmem_base = shmem_base_path[port];
			shmem2_base = shmem2_base_path[port];
			port_of_path = 0;
D
Dmitry Kravkov 已提交
12053 12054
		}

E
Eilon Greenstein 已提交
12055
		/* Extract the ext phy address for the port */
Y
Yaniv Rosner 已提交
12056
		if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
D
Dmitry Kravkov 已提交
12057
				       port_of_path, &phy[port]) !=
Y
Yaniv Rosner 已提交
12058 12059 12060 12061
				       0) {
			DP(NETIF_MSG_LINK, "populate phy failed\n");
			return -EINVAL;
		}
E
Eilon Greenstein 已提交
12062
		/* disable attentions */
D
Dmitry Kravkov 已提交
12063 12064 12065 12066 12067 12068
		bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
			       port_of_path*4,
			       (NIG_MASK_XGXS0_LINK_STATUS |
				NIG_MASK_XGXS0_LINK10G |
				NIG_MASK_SERDES0_LINK_STATUS |
				NIG_MASK_MI_INT));
E
Eilon Greenstein 已提交
12069 12070 12071


		/* Reset the phy */
Y
Yaniv Rosner 已提交
12072
		bnx2x_cl45_write(bp, &phy[port],
Y
Yaniv Rosner 已提交
12073
				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
E
Eilon Greenstein 已提交
12074 12075 12076 12077
	}

	/* Add delay of 150ms after reset */
	msleep(150);
Y
Yaniv Rosner 已提交
12078 12079 12080 12081 12082 12083 12084
	if (phy[PORT_0].addr & 0x1) {
		phy_blk[PORT_0] = &(phy[PORT_1]);
		phy_blk[PORT_1] = &(phy[PORT_0]);
	} else {
		phy_blk[PORT_0] = &(phy[PORT_0]);
		phy_blk[PORT_1] = &(phy[PORT_1]);
	}
E
Eilon Greenstein 已提交
12085
	/* PART2 - Download firmware to both phys */
Y
Yaniv Rosner 已提交
12086
	for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12087
		if (CHIP_IS_E1x(bp))
D
Dmitry Kravkov 已提交
12088
			port_of_path = port;
12089 12090
		else
			port_of_path = 0;
D
Dmitry Kravkov 已提交
12091 12092
		DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
			   phy_blk[port]->addr);
12093 12094
		if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
						      port_of_path))
E
Eilon Greenstein 已提交
12095
			return -EINVAL;
12096 12097 12098 12099
		/* Disable PHY transmitter output */
		bnx2x_cl45_write(bp, phy_blk[port],
				 MDIO_PMA_DEVAD,
				 MDIO_PMA_REG_TX_DISABLE, 1);
E
Eilon Greenstein 已提交
12100

12101
	}
E
Eilon Greenstein 已提交
12102 12103 12104
	return 0;
}

Y
Yaniv Rosner 已提交
12105 12106 12107
static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
				     u32 shmem2_base_path[], u8 phy_index,
				     u32 ext_phy_type, u32 chip_id)
Y
Yaniv Rosner 已提交
12108
{
Y
Yaniv Rosner 已提交
12109
	int rc = 0;
Y
Yaniv Rosner 已提交
12110 12111 12112

	switch (ext_phy_type) {
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
D
Dmitry Kravkov 已提交
12113 12114 12115
		rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
						shmem2_base_path,
						phy_index, chip_id);
Y
Yaniv Rosner 已提交
12116
		break;
Y
Yaniv Rosner 已提交
12117
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
E
Eilon Greenstein 已提交
12118 12119
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
D
Dmitry Kravkov 已提交
12120 12121 12122
		rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
						shmem2_base_path,
						phy_index, chip_id);
E
Eilon Greenstein 已提交
12123 12124
		break;

E
Eilon Greenstein 已提交
12125
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12126 12127 12128 12129
		/*
		 * GPIO1 affects both ports, so there's need to pull
		 * it for single port alone
		 */
D
Dmitry Kravkov 已提交
12130 12131 12132
		rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
						shmem2_base_path,
						phy_index, chip_id);
Y
Yaniv Rosner 已提交
12133
		break;
12134 12135 12136 12137 12138 12139 12140
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
		/*
		 * GPIO3's are linked, and so both need to be toggled
		 * to obtain required 2us pulse.
		 */
		rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
		break;
Y
Yaniv Rosner 已提交
12141 12142
	case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
		rc = -EINVAL;
Y
Yaniv Rosner 已提交
12143
		break;
Y
Yaniv Rosner 已提交
12144 12145
	default:
		DP(NETIF_MSG_LINK,
12146 12147
			   "ext_phy 0x%x common init not required\n",
			   ext_phy_type);
Y
Yaniv Rosner 已提交
12148 12149 12150
		break;
	}

12151 12152 12153 12154
	if (rc != 0)
		netdev_err(bp->dev,  "Warning: PHY was not initialized,"
				      " Port %d\n",
			 0);
Y
Yaniv Rosner 已提交
12155 12156 12157
	return rc;
}

Y
Yaniv Rosner 已提交
12158 12159
int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
			  u32 shmem2_base_path[], u32 chip_id)
Y
Yaniv Rosner 已提交
12160
{
Y
Yaniv Rosner 已提交
12161
	int rc = 0;
12162 12163
	u32 phy_ver, val;
	u8 phy_index = 0;
Y
Yaniv Rosner 已提交
12164
	u32 ext_phy_type, ext_phy_config;
12165 12166
	bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
	bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
Y
Yaniv Rosner 已提交
12167
	DP(NETIF_MSG_LINK, "Begin common phy init\n");
12168 12169 12170 12171 12172
	if (CHIP_IS_E3(bp)) {
		/* Enable EPIO */
		val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
		REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
	}
12173 12174 12175 12176 12177 12178 12179 12180 12181 12182
	/* Check if common init was already done */
	phy_ver = REG_RD(bp, shmem_base_path[0] +
			 offsetof(struct shmem_region,
				  port_mb[PORT_0].ext_phy_fw_version));
	if (phy_ver) {
		DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
			       phy_ver);
		return 0;
	}

Y
Yaniv Rosner 已提交
12183 12184 12185 12186
	/* Read the ext_phy_type for arbitrary port(0) */
	for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
	      phy_index++) {
		ext_phy_config = bnx2x_get_ext_phy_config(bp,
D
Dmitry Kravkov 已提交
12187
							  shmem_base_path[0],
Y
Yaniv Rosner 已提交
12188 12189
							  phy_index, 0);
		ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
D
Dmitry Kravkov 已提交
12190 12191 12192 12193
		rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
						shmem2_base_path,
						phy_index, ext_phy_type,
						chip_id);
Y
Yaniv Rosner 已提交
12194 12195 12196
	}
	return rc;
}
12197

12198 12199 12200 12201 12202 12203 12204 12205 12206 12207 12208 12209 12210 12211 12212 12213 12214 12215 12216 12217 12218 12219 12220 12221 12222 12223 12224 12225 12226 12227 12228 12229 12230 12231 12232 12233 12234 12235 12236 12237 12238 12239 12240 12241 12242 12243 12244 12245 12246 12247 12248 12249 12250 12251
static void bnx2x_check_over_curr(struct link_params *params,
				  struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	u32 cfg_pin;
	u8 port = params->port;
	u32 pin_val;

	cfg_pin = (REG_RD(bp, params->shmem_base +
			  offsetof(struct shmem_region,
			       dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
		   PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
		PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;

	/* Ignore check if no external input PIN available */
	if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
		return;

	if (!pin_val) {
		if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
			netdev_err(bp->dev, "Error:  Power fault on Port %d has"
					    " been detected and the power to "
					    "that SFP+ module has been removed"
					    " to prevent failure of the card."
					    " Please remove the SFP+ module and"
					    " restart the system to clear this"
					    " error.\n",
			 params->port);
			vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
		}
	} else
		vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
}

static void bnx2x_analyze_link_error(struct link_params *params,
				     struct link_vars *vars, u32 lss_status)
{
	struct bnx2x *bp = params->bp;
	/* Compare new value with previous value */
	u8 led_mode;
	u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;

	if ((lss_status ^ half_open_conn) == 0)
		return;

	/* If values differ */
	DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
		       half_open_conn, lss_status);

	/*
	 * a. Update shmem->link_status accordingly
	 * b. Update link_vars->link_up
	 */
	if (lss_status) {
Y
Yaniv Rosner 已提交
12252
		DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12253 12254 12255 12256 12257 12258 12259 12260 12261
		vars->link_status &= ~LINK_STATUS_LINK_UP;
		vars->link_up = 0;
		vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
		/*
		 * Set LED mode to off since the PHY doesn't know about these
		 * errors
		 */
		led_mode = LED_MODE_OFF;
	} else {
Y
Yaniv Rosner 已提交
12262
		DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12263 12264 12265 12266 12267 12268 12269 12270 12271 12272 12273 12274 12275 12276 12277 12278
		vars->link_status |= LINK_STATUS_LINK_UP;
		vars->link_up = 1;
		vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
		led_mode = LED_MODE_OPER;
	}
	/* Update the LED according to the link state */
	bnx2x_set_led(params, vars, led_mode, SPEED_10000);

	/* Update link status in the shared memory */
	bnx2x_update_mng(params, vars->link_status);

	/* C. Trigger General Attention */
	vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
	bnx2x_notify_link_changed(bp);
}

Y
Yaniv Rosner 已提交
12279 12280 12281 12282 12283 12284 12285 12286 12287
/******************************************************************************
* Description:
*	This function checks for half opened connection change indication.
*	When such change occurs, it calls the bnx2x_analyze_link_error
*	to check if Remote Fault is set or cleared. Reception of remote fault
*	status message in the MAC indicates that the peer's MAC has detected
*	a fault, for example, due to break in the TX side of fiber.
*
******************************************************************************/
12288 12289 12290 12291 12292 12293 12294 12295 12296 12297
static void bnx2x_check_half_open_conn(struct link_params *params,
				       struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
	u32 lss_status = 0;
	u32 mac_base;
	/* In case link status is physically up @ 10G do */
	if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
		return;

Y
Yaniv Rosner 已提交
12298
	if (CHIP_IS_E3(bp) &&
12299
	    (REG_RD(bp, MISC_REG_RESET_REG_2) &
Y
Yaniv Rosner 已提交
12300 12301 12302 12303 12304 12305 12306 12307 12308 12309 12310 12311 12312 12313 12314 12315 12316 12317 12318 12319
	      (MISC_REGISTERS_RESET_REG_2_XMAC))) {
		/* Check E3 XMAC */
		/*
		 * Note that link speed cannot be queried here, since it may be
		 * zero while link is down. In case UMAC is active, LSS will
		 * simply not be set
		 */
		mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;

		/* Clear stick bits (Requires rising edge) */
		REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
		REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
		       XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
		       XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
		if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
			lss_status = 1;

		bnx2x_analyze_link_error(params, vars, lss_status);
	} else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
		   (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12320 12321 12322 12323 12324 12325 12326 12327 12328 12329 12330 12331 12332 12333 12334 12335 12336 12337 12338 12339 12340
		/* Check E1X / E2 BMAC */
		u32 lss_status_reg;
		u32 wb_data[2];
		mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
			NIG_REG_INGRESS_BMAC0_MEM;
		/*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
		if (CHIP_IS_E2(bp))
			lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
		else
			lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;

		REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
		lss_status = (wb_data[0] > 0);

		bnx2x_analyze_link_error(params, vars, lss_status);
	}
}

void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
{
	struct bnx2x *bp = params->bp;
Y
Yaniv Rosner 已提交
12341
	u16 phy_idx;
12342
	if (!params) {
Y
Yaniv Rosner 已提交
12343
		DP(NETIF_MSG_LINK, "Uninitialized params !\n");
12344 12345
		return;
	}
Y
Yaniv Rosner 已提交
12346 12347 12348 12349 12350 12351 12352 12353 12354

	for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
		if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
			bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
			bnx2x_check_half_open_conn(params, vars);
			break;
		}
	}

12355 12356 12357 12358
	if (CHIP_IS_E3(bp))
		bnx2x_check_over_curr(params, vars);
}

Y
Yaniv Rosner 已提交
12359
u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12360 12361 12362 12363 12364
{
	u8 phy_index;
	struct bnx2x_phy phy;
	for (phy_index = INT_PHY; phy_index < MAX_PHYS;
	      phy_index++) {
Y
Yaniv Rosner 已提交
12365
		if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12366 12367 12368 12369 12370 12371 12372 12373 12374 12375 12376 12377 12378
				       0, &phy) != 0) {
			DP(NETIF_MSG_LINK, "populate phy failed\n");
			return 0;
		}

		if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
			return 1;
	}
	return 0;
}

u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
			     u32 shmem_base,
Y
Yaniv Rosner 已提交
12379
			     u32 shmem2_base,
12380 12381 12382 12383 12384 12385
			     u8 port)
{
	u8 phy_index, fan_failure_det_req = 0;
	struct bnx2x_phy phy;
	for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
	      phy_index++) {
Y
Yaniv Rosner 已提交
12386
		if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12387 12388 12389 12390 12391 12392 12393 12394 12395 12396 12397 12398 12399 12400
				       port, &phy)
		    != 0) {
			DP(NETIF_MSG_LINK, "populate phy failed\n");
			return 0;
		}
		fan_failure_det_req |= (phy.flags &
					FLAGS_FAN_FAILURE_DET_REQ);
	}
	return fan_failure_det_req;
}

void bnx2x_hw_reset_phy(struct link_params *params)
{
	u8 phy_index;
12401 12402 12403 12404 12405 12406 12407 12408 12409
	struct bnx2x *bp = params->bp;
	bnx2x_update_mng(params, 0);
	bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
		       (NIG_MASK_XGXS0_LINK_STATUS |
			NIG_MASK_XGXS0_LINK10G |
			NIG_MASK_SERDES0_LINK_STATUS |
			NIG_MASK_MI_INT));

	for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12410 12411 12412 12413 12414 12415 12416 12417 12418
	      phy_index++) {
		if (params->phy[phy_index].hw_reset) {
			params->phy[phy_index].hw_reset(
				&params->phy[phy_index],
				params);
			params->phy[phy_index] = phy_null;
		}
	}
}
12419 12420 12421 12422 12423 12424 12425 12426

void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
			    u32 chip_id, u32 shmem_base, u32 shmem2_base,
			    u8 port)
{
	u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
	u32 val;
	u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12427 12428 12429 12430 12431 12432 12433 12434
	if (CHIP_IS_E3(bp)) {
		if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
					      shmem_base,
					      port,
					      &gpio_num,
					      &gpio_port) != 0)
			return;
	} else {
12435 12436 12437 12438 12439 12440 12441 12442 12443 12444 12445 12446 12447 12448 12449 12450 12451 12452 12453 12454 12455 12456 12457 12458 12459 12460 12461 12462 12463 12464 12465 12466 12467 12468 12469 12470 12471 12472 12473 12474 12475 12476 12477 12478 12479 12480 12481 12482 12483 12484 12485 12486 12487
		struct bnx2x_phy phy;
		for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
		      phy_index++) {
			if (bnx2x_populate_phy(bp, phy_index, shmem_base,
					       shmem2_base, port, &phy)
			    != 0) {
				DP(NETIF_MSG_LINK, "populate phy failed\n");
				return;
			}
			if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
				gpio_num = MISC_REGISTERS_GPIO_3;
				gpio_port = port;
				break;
			}
		}
	}

	if (gpio_num == 0xff)
		return;

	/* Set GPIO3 to trigger SFP+ module insertion/removal */
	bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);

	swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
	swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
	gpio_port ^= (swap_val && swap_override);

	vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
		(gpio_num + (gpio_port << 2));

	sync_offset = shmem_base +
		offsetof(struct shmem_region,
			 dev_info.port_hw_config[port].aeu_int_mask);
	REG_WR(bp, sync_offset, vars->aeu_int_mask);

	DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
		       gpio_num, gpio_port, vars->aeu_int_mask);

	if (port == 0)
		offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
	else
		offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;

	/* Open appropriate AEU for interrupts */
	aeu_mask = REG_RD(bp, offset);
	aeu_mask |= vars->aeu_int_mask;
	REG_WR(bp, offset, aeu_mask);

	/* Enable the GPIO to trigger interrupt */
	val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
	val |= 1 << (gpio_num + (gpio_port << 2));
	REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
}