at32ap700x.c 51.4 KB
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/*
 * Copyright (C) 2005-2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dw_dmac.h>
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#include <linux/fb.h>
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#include <linux/init.h>
#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/gpio.h>
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#include <linux/spi/spi.h>
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#include <linux/usb/atmel_usba_udc.h>
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#include <asm/atmel-mci.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <mach/at32ap700x.h>
#include <mach/board.h>
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#include <mach/hmatrix.h>
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#include <mach/portmux.h>
#include <mach/sram.h>
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#include <video/atmel_lcdc.h>

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#include "clock.h"
#include "pio.h"
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#include "pm.h"

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#define PBMEM(base)					\
	{						\
		.start		= base,			\
		.end		= base + 0x3ff,		\
		.flags		= IORESOURCE_MEM,	\
	}
#define IRQ(num)					\
	{						\
		.start		= num,			\
		.end		= num,			\
		.flags		= IORESOURCE_IRQ,	\
	}
#define NAMED_IRQ(num, _name)				\
	{						\
		.start		= num,			\
		.end		= num,			\
		.name		= _name,		\
		.flags		= IORESOURCE_IRQ,	\
	}

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/* REVISIT these assume *every* device supports DMA, but several
 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
 */
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#define DEFINE_DEV(_name, _id)					\
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static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;		\
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static struct platform_device _name##_id##_device = {		\
	.name		= #_name,				\
	.id		= _id,					\
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	.dev		= {					\
		.dma_mask = &_name##_id##_dma_mask,		\
		.coherent_dma_mask = DMA_32BIT_MASK,		\
	},							\
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	.resource	= _name##_id##_resource,		\
	.num_resources	= ARRAY_SIZE(_name##_id##_resource),	\
}
#define DEFINE_DEV_DATA(_name, _id)				\
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static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;		\
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static struct platform_device _name##_id##_device = {		\
	.name		= #_name,				\
	.id		= _id,					\
	.dev		= {					\
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		.dma_mask = &_name##_id##_dma_mask,		\
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		.platform_data	= &_name##_id##_data,		\
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		.coherent_dma_mask = DMA_32BIT_MASK,		\
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	},							\
	.resource	= _name##_id##_resource,		\
	.num_resources	= ARRAY_SIZE(_name##_id##_resource),	\
}

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#define select_peripheral(port, pin_mask, periph, flags)	\
	at32_select_periph(GPIO_##port##_BASE, pin_mask,	\
			   GPIO_##periph, flags)
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#define DEV_CLK(_name, devname, bus, _index)			\
static struct clk devname##_##_name = {				\
	.name		= #_name,				\
	.dev		= &devname##_device.dev,		\
	.parent		= &bus##_clk,				\
	.mode		= bus##_clk_mode,			\
	.get_rate	= bus##_clk_get_rate,			\
	.index		= _index,				\
}

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static DEFINE_SPINLOCK(pm_lock);

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static struct clk osc0;
static struct clk osc1;

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static unsigned long osc_get_rate(struct clk *clk)
{
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	return at32_board_osc_rates[clk->index];
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}

static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
{
	unsigned long div, mul, rate;

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	div = PM_BFEXT(PLLDIV, control) + 1;
	mul = PM_BFEXT(PLLMUL, control) + 1;
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	rate = clk->parent->get_rate(clk->parent);
	rate = (rate + div / 2) / div;
	rate *= mul;

	return rate;
}

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static long pll_set_rate(struct clk *clk, unsigned long rate,
			 u32 *pll_ctrl)
{
	unsigned long mul;
	unsigned long mul_best_fit = 0;
	unsigned long div;
	unsigned long div_min;
	unsigned long div_max;
	unsigned long div_best_fit = 0;
	unsigned long base;
	unsigned long pll_in;
	unsigned long actual = 0;
	unsigned long rate_error;
	unsigned long rate_error_prev = ~0UL;
	u32 ctrl;

	/* Rate must be between 80 MHz and 200 Mhz. */
	if (rate < 80000000UL || rate > 200000000UL)
		return -EINVAL;

	ctrl = PM_BF(PLLOPT, 4);
	base = clk->parent->get_rate(clk->parent);

	/* PLL input frequency must be between 6 MHz and 32 MHz. */
	div_min = DIV_ROUND_UP(base, 32000000UL);
	div_max = base / 6000000UL;

	if (div_max < div_min)
		return -EINVAL;

	for (div = div_min; div <= div_max; div++) {
		pll_in = (base + div / 2) / div;
		mul = (rate + pll_in / 2) / pll_in;

		if (mul == 0)
			continue;

		actual = pll_in * mul;
		rate_error = abs(actual - rate);

		if (rate_error < rate_error_prev) {
			mul_best_fit = mul;
			div_best_fit = div;
			rate_error_prev = rate_error;
		}

		if (rate_error == 0)
			break;
	}

	if (div_best_fit == 0)
		return -EINVAL;

	ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
	ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
	ctrl |= PM_BF(PLLCOUNT, 16);

	if (clk->parent == &osc1)
		ctrl |= PM_BIT(PLLOSC);

	*pll_ctrl = ctrl;

	return actual;
}

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static unsigned long pll0_get_rate(struct clk *clk)
{
	u32 control;

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	control = pm_readl(PLL0);
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	return pll_get_rate(clk, control);
}

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static void pll1_mode(struct clk *clk, int enabled)
{
	unsigned long timeout;
	u32 status;
	u32 ctrl;

	ctrl = pm_readl(PLL1);

	if (enabled) {
		if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
			pr_debug("clk %s: failed to enable, rate not set\n",
					clk->name);
			return;
		}

		ctrl |= PM_BIT(PLLEN);
		pm_writel(PLL1, ctrl);

		/* Wait for PLL lock. */
		for (timeout = 10000; timeout; timeout--) {
			status = pm_readl(ISR);
			if (status & PM_BIT(LOCK1))
				break;
			udelay(10);
		}

		if (!(status & PM_BIT(LOCK1)))
			printk(KERN_ERR "clk %s: timeout waiting for lock\n",
					clk->name);
	} else {
		ctrl &= ~PM_BIT(PLLEN);
		pm_writel(PLL1, ctrl);
	}
}

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static unsigned long pll1_get_rate(struct clk *clk)
{
	u32 control;

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	control = pm_readl(PLL1);
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	return pll_get_rate(clk, control);
}

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static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
{
	u32 ctrl = 0;
	unsigned long actual_rate;

	actual_rate = pll_set_rate(clk, rate, &ctrl);

	if (apply) {
		if (actual_rate != rate)
			return -EINVAL;
		if (clk->users > 0)
			return -EBUSY;
		pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
				clk->name, rate, actual_rate);
		pm_writel(PLL1, ctrl);
	}

	return actual_rate;
}

static int pll1_set_parent(struct clk *clk, struct clk *parent)
{
	u32 ctrl;

	if (clk->users > 0)
		return -EBUSY;

	ctrl = pm_readl(PLL1);
	WARN_ON(ctrl & PM_BIT(PLLEN));

	if (parent == &osc0)
		ctrl &= ~PM_BIT(PLLOSC);
	else if (parent == &osc1)
		ctrl |= PM_BIT(PLLOSC);
	else
		return -EINVAL;

	pm_writel(PLL1, ctrl);
	clk->parent = parent;

	return 0;
}

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/*
 * The AT32AP7000 has five primary clock sources: One 32kHz
 * oscillator, two crystal oscillators and two PLLs.
 */
static struct clk osc32k = {
	.name		= "osc32k",
	.get_rate	= osc_get_rate,
	.users		= 1,
	.index		= 0,
};
static struct clk osc0 = {
	.name		= "osc0",
	.get_rate	= osc_get_rate,
	.users		= 1,
	.index		= 1,
};
static struct clk osc1 = {
	.name		= "osc1",
	.get_rate	= osc_get_rate,
	.index		= 2,
};
static struct clk pll0 = {
	.name		= "pll0",
	.get_rate	= pll0_get_rate,
	.parent		= &osc0,
};
static struct clk pll1 = {
	.name		= "pll1",
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	.mode		= pll1_mode,
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	.get_rate	= pll1_get_rate,
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	.set_rate	= pll1_set_rate,
	.set_parent	= pll1_set_parent,
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	.parent		= &osc0,
};

/*
 * The main clock can be either osc0 or pll0.  The boot loader may
 * have chosen one for us, so we don't really know which one until we
 * have a look at the SM.
 */
static struct clk *main_clock;

/*
 * Synchronous clocks are generated from the main clock. The clocks
 * must satisfy the constraint
 *   fCPU >= fHSB >= fPB
 * i.e. each clock must not be faster than its parent.
 */
static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
{
	return main_clock->get_rate(main_clock) >> shift;
};

static void cpu_clk_mode(struct clk *clk, int enabled)
{
	unsigned long flags;
	u32 mask;

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	spin_lock_irqsave(&pm_lock, flags);
	mask = pm_readl(CPU_MASK);
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	if (enabled)
		mask |= 1 << clk->index;
	else
		mask &= ~(1 << clk->index);
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	pm_writel(CPU_MASK, mask);
	spin_unlock_irqrestore(&pm_lock, flags);
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}

static unsigned long cpu_clk_get_rate(struct clk *clk)
{
	unsigned long cksel, shift = 0;

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	cksel = pm_readl(CKSEL);
	if (cksel & PM_BIT(CPUDIV))
		shift = PM_BFEXT(CPUSEL, cksel) + 1;
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	return bus_clk_get_rate(clk, shift);
}

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static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
{
	u32 control;
	unsigned long parent_rate, child_div, actual_rate, div;

	parent_rate = clk->parent->get_rate(clk->parent);
	control = pm_readl(CKSEL);

	if (control & PM_BIT(HSBDIV))
		child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
	else
		child_div = 1;

	if (rate > 3 * (parent_rate / 4) || child_div == 1) {
		actual_rate = parent_rate;
		control &= ~PM_BIT(CPUDIV);
	} else {
		unsigned int cpusel;
		div = (parent_rate + rate / 2) / rate;
		if (div > child_div)
			div = child_div;
		cpusel = (div > 1) ? (fls(div) - 2) : 0;
		control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
		actual_rate = parent_rate / (1 << (cpusel + 1));
	}

	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
			clk->name, rate, actual_rate);

	if (apply)
		pm_writel(CKSEL, control);

	return actual_rate;
}

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static void hsb_clk_mode(struct clk *clk, int enabled)
{
	unsigned long flags;
	u32 mask;

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	spin_lock_irqsave(&pm_lock, flags);
	mask = pm_readl(HSB_MASK);
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	if (enabled)
		mask |= 1 << clk->index;
	else
		mask &= ~(1 << clk->index);
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	pm_writel(HSB_MASK, mask);
	spin_unlock_irqrestore(&pm_lock, flags);
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}

static unsigned long hsb_clk_get_rate(struct clk *clk)
{
	unsigned long cksel, shift = 0;

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	cksel = pm_readl(CKSEL);
	if (cksel & PM_BIT(HSBDIV))
		shift = PM_BFEXT(HSBSEL, cksel) + 1;
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	return bus_clk_get_rate(clk, shift);
}

static void pba_clk_mode(struct clk *clk, int enabled)
{
	unsigned long flags;
	u32 mask;

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	spin_lock_irqsave(&pm_lock, flags);
	mask = pm_readl(PBA_MASK);
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	if (enabled)
		mask |= 1 << clk->index;
	else
		mask &= ~(1 << clk->index);
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	pm_writel(PBA_MASK, mask);
	spin_unlock_irqrestore(&pm_lock, flags);
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}

static unsigned long pba_clk_get_rate(struct clk *clk)
{
	unsigned long cksel, shift = 0;

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	cksel = pm_readl(CKSEL);
	if (cksel & PM_BIT(PBADIV))
		shift = PM_BFEXT(PBASEL, cksel) + 1;
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	return bus_clk_get_rate(clk, shift);
}

static void pbb_clk_mode(struct clk *clk, int enabled)
{
	unsigned long flags;
	u32 mask;

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	spin_lock_irqsave(&pm_lock, flags);
	mask = pm_readl(PBB_MASK);
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	if (enabled)
		mask |= 1 << clk->index;
	else
		mask &= ~(1 << clk->index);
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	pm_writel(PBB_MASK, mask);
	spin_unlock_irqrestore(&pm_lock, flags);
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}

static unsigned long pbb_clk_get_rate(struct clk *clk)
{
	unsigned long cksel, shift = 0;

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	cksel = pm_readl(CKSEL);
	if (cksel & PM_BIT(PBBDIV))
		shift = PM_BFEXT(PBBSEL, cksel) + 1;
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	return bus_clk_get_rate(clk, shift);
}

static struct clk cpu_clk = {
	.name		= "cpu",
	.get_rate	= cpu_clk_get_rate,
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	.set_rate	= cpu_clk_set_rate,
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	.users		= 1,
};
static struct clk hsb_clk = {
	.name		= "hsb",
	.parent		= &cpu_clk,
	.get_rate	= hsb_clk_get_rate,
};
static struct clk pba_clk = {
	.name		= "pba",
	.parent		= &hsb_clk,
	.mode		= hsb_clk_mode,
	.get_rate	= pba_clk_get_rate,
	.index		= 1,
};
static struct clk pbb_clk = {
	.name		= "pbb",
	.parent		= &hsb_clk,
	.mode		= hsb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.users		= 1,
	.index		= 2,
};

/* --------------------------------------------------------------------
 *  Generic Clock operations
 * -------------------------------------------------------------------- */

static void genclk_mode(struct clk *clk, int enabled)
{
	u32 control;

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	control = pm_readl(GCCTRL(clk->index));
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	if (enabled)
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		control |= PM_BIT(CEN);
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	else
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		control &= ~PM_BIT(CEN);
	pm_writel(GCCTRL(clk->index), control);
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}

static unsigned long genclk_get_rate(struct clk *clk)
{
	u32 control;
	unsigned long div = 1;

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	control = pm_readl(GCCTRL(clk->index));
	if (control & PM_BIT(DIVEN))
		div = 2 * (PM_BFEXT(DIV, control) + 1);
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	return clk->parent->get_rate(clk->parent) / div;
}

static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
{
	u32 control;
	unsigned long parent_rate, actual_rate, div;

	parent_rate = clk->parent->get_rate(clk->parent);
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	control = pm_readl(GCCTRL(clk->index));
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	if (rate > 3 * parent_rate / 4) {
		actual_rate = parent_rate;
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		control &= ~PM_BIT(DIVEN);
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	} else {
		div = (parent_rate + rate) / (2 * rate) - 1;
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		control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
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		actual_rate = parent_rate / (2 * (div + 1));
	}

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	dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
		clk->name, rate, actual_rate);
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	if (apply)
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		pm_writel(GCCTRL(clk->index), control);
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	return actual_rate;
}

int genclk_set_parent(struct clk *clk, struct clk *parent)
{
	u32 control;

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	dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
		clk->name, parent->name, clk->parent->name);
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	control = pm_readl(GCCTRL(clk->index));
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	if (parent == &osc1 || parent == &pll1)
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		control |= PM_BIT(OSCSEL);
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	else if (parent == &osc0 || parent == &pll0)
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		control &= ~PM_BIT(OSCSEL);
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	else
		return -EINVAL;

	if (parent == &pll0 || parent == &pll1)
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		control |= PM_BIT(PLLSEL);
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	else
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		control &= ~PM_BIT(PLLSEL);
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	pm_writel(GCCTRL(clk->index), control);
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	clk->parent = parent;

	return 0;
}

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static void __init genclk_init_parent(struct clk *clk)
{
	u32 control;
	struct clk *parent;

	BUG_ON(clk->index > 7);

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	control = pm_readl(GCCTRL(clk->index));
	if (control & PM_BIT(OSCSEL))
		parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
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	else
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		parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
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	clk->parent = parent;
}

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static struct dw_dma_platform_data dw_dmac0_data = {
	.nr_channels	= 3,
};

static struct resource dw_dmac0_resource[] = {
	PBMEM(0xff200000),
	IRQ(2),
};
DEFINE_DEV_DATA(dw_dmac, 0);
DEV_CLK(hclk, dw_dmac0, hsb, 10);

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/* --------------------------------------------------------------------
 *  System peripherals
 * -------------------------------------------------------------------- */
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static struct resource at32_pm0_resource[] = {
	{
		.start	= 0xfff00000,
		.end	= 0xfff0007f,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(20),
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};
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static struct resource at32ap700x_rtc0_resource[] = {
	{
		.start	= 0xfff00080,
		.end	= 0xfff000af,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(21),
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};
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static struct resource at32_wdt0_resource[] = {
	{
		.start	= 0xfff000b0,
635
		.end	= 0xfff000cf,
636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658
		.flags	= IORESOURCE_MEM,
	},
};

static struct resource at32_eic0_resource[] = {
	{
		.start	= 0xfff00100,
		.end	= 0xfff0013f,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(19),
};

DEFINE_DEV(at32_pm, 0);
DEFINE_DEV(at32ap700x_rtc, 0);
DEFINE_DEV(at32_wdt, 0);
DEFINE_DEV(at32_eic, 0);

/*
 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 * is always running.
 */
static struct clk at32_pm_pclk = {
659
	.name		= "pclk",
660
	.dev		= &at32_pm0_device.dev,
661 662 663 664 665 666
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.users		= 1,
	.index		= 0,
};
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static struct resource intc0_resource[] = {
	PBMEM(0xfff00400),
};
struct platform_device at32_intc0_device = {
	.name		= "intc",
	.id		= 0,
	.resource	= intc0_resource,
	.num_resources	= ARRAY_SIZE(intc0_resource),
};
DEV_CLK(pclk, at32_intc0, pbb, 1);

static struct clk ebi_clk = {
	.name		= "ebi",
	.parent		= &hsb_clk,
	.mode		= hsb_clk_mode,
	.get_rate	= hsb_clk_get_rate,
	.users		= 1,
};
static struct clk hramc_clk = {
	.name		= "hramc",
	.parent		= &hsb_clk,
	.mode		= hsb_clk_mode,
	.get_rate	= hsb_clk_get_rate,
	.users		= 1,
692
	.index		= 3,
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};
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static struct clk sdramc_clk = {
	.name		= "sdramc_clk",
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.users		= 1,
	.index		= 14,
};
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static struct resource smc0_resource[] = {
	PBMEM(0xfff03400),
};
DEFINE_DEV(smc, 0);
DEV_CLK(pclk, smc0, pbb, 13);
DEV_CLK(mck, smc0, hsb, 0);

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static struct platform_device pdc_device = {
	.name		= "pdc",
	.id		= 0,
};
DEV_CLK(hclk, pdc, hsb, 4);
DEV_CLK(pclk, pdc, pba, 16);

static struct clk pico_clk = {
	.name		= "pico",
	.parent		= &cpu_clk,
	.mode		= cpu_clk_mode,
	.get_rate	= cpu_clk_get_rate,
	.users		= 1,
};

725 726 727 728
/* --------------------------------------------------------------------
 * HMATRIX
 * -------------------------------------------------------------------- */

729
struct clk at32_hmatrix_clk = {
730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745
	.name		= "hmatrix_clk",
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.index		= 2,
	.users		= 1,
};

/*
 * Set bits in the HMATRIX Special Function Register (SFR) used by the
 * External Bus Interface (EBI). This can be used to enable special
 * features like CompactFlash support, NAND Flash support, etc. on
 * certain chipselects.
 */
static inline void set_ebi_sfr_bits(u32 mask)
{
746
	hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
747 748
}

749
/* --------------------------------------------------------------------
750
 *  Timer/Counter (TC)
751
 * -------------------------------------------------------------------- */
752 753

static struct resource at32_tcb0_resource[] = {
754 755 756
	PBMEM(0xfff00c00),
	IRQ(22),
};
757 758
static struct platform_device at32_tcb0_device = {
	.name		= "atmel_tcb",
759
	.id		= 0,
760 761 762 763 764 765 766 767 768 769 770 771 772 773
	.resource	= at32_tcb0_resource,
	.num_resources	= ARRAY_SIZE(at32_tcb0_resource),
};
DEV_CLK(t0_clk, at32_tcb0, pbb, 3);

static struct resource at32_tcb1_resource[] = {
	PBMEM(0xfff01000),
	IRQ(23),
};
static struct platform_device at32_tcb1_device = {
	.name		= "atmel_tcb",
	.id		= 1,
	.resource	= at32_tcb1_resource,
	.num_resources	= ARRAY_SIZE(at32_tcb1_resource),
774
};
775
DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
776

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/* --------------------------------------------------------------------
 *  PIO
 * -------------------------------------------------------------------- */

static struct resource pio0_resource[] = {
	PBMEM(0xffe02800),
	IRQ(13),
};
DEFINE_DEV(pio, 0);
DEV_CLK(mck, pio0, pba, 10);

static struct resource pio1_resource[] = {
	PBMEM(0xffe02c00),
	IRQ(14),
};
DEFINE_DEV(pio, 1);
DEV_CLK(mck, pio1, pba, 11);

static struct resource pio2_resource[] = {
	PBMEM(0xffe03000),
	IRQ(15),
};
DEFINE_DEV(pio, 2);
DEV_CLK(mck, pio2, pba, 12);

static struct resource pio3_resource[] = {
	PBMEM(0xffe03400),
	IRQ(16),
};
DEFINE_DEV(pio, 3);
DEV_CLK(mck, pio3, pba, 13);

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static struct resource pio4_resource[] = {
	PBMEM(0xffe03800),
	IRQ(17),
};
DEFINE_DEV(pio, 4);
DEV_CLK(mck, pio4, pba, 14);

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void __init at32_add_system_devices(void)
{
818
	platform_device_register(&at32_pm0_device);
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	platform_device_register(&at32_intc0_device);
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	platform_device_register(&at32ap700x_rtc0_device);
	platform_device_register(&at32_wdt0_device);
	platform_device_register(&at32_eic0_device);
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	platform_device_register(&smc0_device);
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	platform_device_register(&pdc_device);
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	platform_device_register(&dw_dmac0_device);
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	platform_device_register(&at32_tcb0_device);
	platform_device_register(&at32_tcb1_device);
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	platform_device_register(&pio0_device);
	platform_device_register(&pio1_device);
	platform_device_register(&pio2_device);
	platform_device_register(&pio3_device);
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	platform_device_register(&pio4_device);
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}

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/* --------------------------------------------------------------------
 *  PSIF
 * -------------------------------------------------------------------- */
static struct resource atmel_psif0_resource[] __initdata = {
	{
		.start	= 0xffe03c00,
		.end	= 0xffe03cff,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(18),
};
static struct clk atmel_psif0_pclk = {
	.name		= "pclk",
	.parent		= &pba_clk,
	.mode		= pba_clk_mode,
	.get_rate	= pba_clk_get_rate,
	.index		= 15,
};

static struct resource atmel_psif1_resource[] __initdata = {
	{
		.start	= 0xffe03d00,
		.end	= 0xffe03dff,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(18),
};
static struct clk atmel_psif1_pclk = {
	.name		= "pclk",
	.parent		= &pba_clk,
	.mode		= pba_clk_mode,
	.get_rate	= pba_clk_get_rate,
	.index		= 15,
};

struct platform_device *__init at32_add_device_psif(unsigned int id)
{
	struct platform_device *pdev;
875
	u32 pin_mask;
876 877 878 879 880 881 882 883 884 885

	if (!(id == 0 || id == 1))
		return NULL;

	pdev = platform_device_alloc("atmel_psif", id);
	if (!pdev)
		return NULL;

	switch (id) {
	case 0:
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		pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */

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		if (platform_device_add_resources(pdev, atmel_psif0_resource,
					ARRAY_SIZE(atmel_psif0_resource)))
			goto err_add_resources;
		atmel_psif0_pclk.dev = &pdev->dev;
892
		select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
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		break;
	case 1:
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		pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */

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		if (platform_device_add_resources(pdev, atmel_psif1_resource,
					ARRAY_SIZE(atmel_psif1_resource)))
			goto err_add_resources;
		atmel_psif1_pclk.dev = &pdev->dev;
901
		select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
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		break;
	default:
		return NULL;
	}

	platform_device_add(pdev);
	return pdev;

err_add_resources:
	platform_device_put(pdev);
	return NULL;
}

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/* --------------------------------------------------------------------
 *  USART
 * -------------------------------------------------------------------- */

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static struct atmel_uart_data atmel_usart0_data = {
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};
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static struct resource atmel_usart0_resource[] = {
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	PBMEM(0xffe00c00),
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	IRQ(6),
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};
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DEFINE_DEV_DATA(atmel_usart, 0);
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DEV_CLK(usart, atmel_usart0, pba, 3);
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static struct atmel_uart_data atmel_usart1_data = {
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};
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static struct resource atmel_usart1_resource[] = {
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	PBMEM(0xffe01000),
	IRQ(7),
};
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DEFINE_DEV_DATA(atmel_usart, 1);
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DEV_CLK(usart, atmel_usart1, pba, 4);
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static struct atmel_uart_data atmel_usart2_data = {
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};
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static struct resource atmel_usart2_resource[] = {
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	PBMEM(0xffe01400),
	IRQ(8),
};
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DEFINE_DEV_DATA(atmel_usart, 2);
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DEV_CLK(usart, atmel_usart2, pba, 5);
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static struct atmel_uart_data atmel_usart3_data = {
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};
956
static struct resource atmel_usart3_resource[] = {
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	PBMEM(0xffe01800),
	IRQ(9),
};
960
DEFINE_DEV_DATA(atmel_usart, 3);
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DEV_CLK(usart, atmel_usart3, pba, 6);
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static inline void configure_usart0_pins(void)
{
965 966 967
	u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */

	select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
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}

static inline void configure_usart1_pins(void)
{
972 973 974
	u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */

	select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
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}

static inline void configure_usart2_pins(void)
{
979 980 981
	u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */

	select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
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}

static inline void configure_usart3_pins(void)
{
986 987 988
	u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */

	select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
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}

991
static struct platform_device *__initdata at32_usarts[4];
992 993

void __init at32_map_usart(unsigned int hw_id, unsigned int line)
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{
	struct platform_device *pdev;

997
	switch (hw_id) {
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	case 0:
999
		pdev = &atmel_usart0_device;
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		configure_usart0_pins();
		break;
	case 1:
1003
		pdev = &atmel_usart1_device;
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		configure_usart1_pins();
		break;
	case 2:
1007
		pdev = &atmel_usart2_device;
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		configure_usart2_pins();
		break;
	case 3:
1011
		pdev = &atmel_usart3_device;
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		configure_usart3_pins();
		break;
	default:
1015
		return;
1016 1017 1018 1019 1020 1021
	}

	if (PXSEG(pdev->resource[0].start) == P4SEG) {
		/* Addresses in the P4 segment are permanently mapped 1:1 */
		struct atmel_uart_data *data = pdev->dev.platform_data;
		data->regs = (void __iomem *)pdev->resource[0].start;
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	}

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	pdev->id = line;
	at32_usarts[line] = pdev;
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}

struct platform_device *__init at32_add_device_usart(unsigned int id)
{
1030 1031
	platform_device_register(at32_usarts[id]);
	return at32_usarts[id];
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}

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struct platform_device *atmel_default_console_device;
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void __init at32_setup_serial_console(unsigned int usart_id)
{
1038
	atmel_default_console_device = at32_usarts[usart_id];
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}

/* --------------------------------------------------------------------
 *  Ethernet
 * -------------------------------------------------------------------- */

1045
#ifdef CONFIG_CPU_AT32AP7000
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static struct eth_platform_data macb0_data;
static struct resource macb0_resource[] = {
	PBMEM(0xfff01800),
	IRQ(25),
};
DEFINE_DEV_DATA(macb, 0);
DEV_CLK(hclk, macb0, hsb, 8);
DEV_CLK(pclk, macb0, pbb, 6);

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static struct eth_platform_data macb1_data;
static struct resource macb1_resource[] = {
	PBMEM(0xfff01c00),
	IRQ(26),
};
DEFINE_DEV_DATA(macb, 1);
DEV_CLK(hclk, macb1, hsb, 9);
DEV_CLK(pclk, macb1, pbb, 7);

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struct platform_device *__init
at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
{
	struct platform_device *pdev;
1068
	u32 pin_mask;
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	switch (id) {
	case 0:
		pdev = &macb0_device;

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		pin_mask  = (1 << 3);	/* TXD0 */
		pin_mask |= (1 << 4);	/* TXD1 */
		pin_mask |= (1 << 7);	/* TXEN */
		pin_mask |= (1 << 8);	/* TXCK */
		pin_mask |= (1 << 9);	/* RXD0 */
		pin_mask |= (1 << 10);	/* RXD1 */
		pin_mask |= (1 << 13);	/* RXER */
		pin_mask |= (1 << 15);	/* RXDV */
		pin_mask |= (1 << 16);	/* MDC  */
		pin_mask |= (1 << 17);	/* MDIO */
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		if (!data->is_rmii) {
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			pin_mask |= (1 << 0);	/* COL  */
			pin_mask |= (1 << 1);	/* CRS  */
			pin_mask |= (1 << 2);	/* TXER */
			pin_mask |= (1 << 5);	/* TXD2 */
			pin_mask |= (1 << 6);	/* TXD3 */
			pin_mask |= (1 << 11);	/* RXD2 */
			pin_mask |= (1 << 12);	/* RXD3 */
			pin_mask |= (1 << 14);	/* RXCK */
1094
#ifndef CONFIG_BOARD_MIMC200
1095
			pin_mask |= (1 << 18);	/* SPD  */
1096
#endif
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		}
1098 1099 1100

		select_peripheral(PIOC, pin_mask, PERIPH_A, 0);

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		break;

1103 1104 1105
	case 1:
		pdev = &macb1_device;

1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116
		pin_mask  = (1 << 13);	/* TXD0 */
		pin_mask |= (1 << 14);	/* TXD1 */
		pin_mask |= (1 << 11);	/* TXEN */
		pin_mask |= (1 << 12);	/* TXCK */
		pin_mask |= (1 << 10);	/* RXD0 */
		pin_mask |= (1 << 6);	/* RXD1 */
		pin_mask |= (1 << 5);	/* RXER */
		pin_mask |= (1 << 4);	/* RXDV */
		pin_mask |= (1 << 3);	/* MDC  */
		pin_mask |= (1 << 2);	/* MDIO */

1117
#ifndef CONFIG_BOARD_MIMC200
1118 1119
		if (!data->is_rmii)
			pin_mask |= (1 << 15);	/* SPD  */
1120
#endif
1121 1122

		select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1123 1124

		if (!data->is_rmii) {
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			pin_mask  = (1 << 19);	/* COL  */
			pin_mask |= (1 << 23);	/* CRS  */
			pin_mask |= (1 << 26);	/* TXER */
			pin_mask |= (1 << 27);	/* TXD2 */
			pin_mask |= (1 << 28);	/* TXD3 */
			pin_mask |= (1 << 29);	/* RXD2 */
			pin_mask |= (1 << 30);	/* RXD3 */
			pin_mask |= (1 << 24);	/* RXCK */

			select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
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		}
		break;

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	default:
		return NULL;
	}

	memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
	platform_device_register(pdev);

	return pdev;
}
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#endif
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/* --------------------------------------------------------------------
 *  SPI
 * -------------------------------------------------------------------- */
1152
static struct resource atmel_spi0_resource[] = {
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	PBMEM(0xffe00000),
	IRQ(3),
};
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DEFINE_DEV(atmel_spi, 0);
DEV_CLK(spi_clk, atmel_spi0, pba, 0);

static struct resource atmel_spi1_resource[] = {
	PBMEM(0xffe00400),
	IRQ(4),
};
DEFINE_DEV(atmel_spi, 1);
DEV_CLK(spi_clk, atmel_spi1, pba, 1);
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static void __init
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at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
		      unsigned int n, const u8 *pins)
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{
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	unsigned int pin, mode;

	for (; n; n--, b++) {
		b->bus_num = bus_num;
		if (b->chip_select >= 4)
			continue;
		pin = (unsigned)b->controller_data;
		if (!pin) {
			pin = pins[b->chip_select];
			b->controller_data = (void *)pin;
		}
		mode = AT32_GPIOF_OUTPUT;
		if (!(b->mode & SPI_CS_HIGH))
			mode |= AT32_GPIOF_HIGH;
		at32_select_gpio(pin, mode);
	}
}

struct platform_device *__init
at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
{
	/*
	 * Manage the chipselects as GPIOs, normally using the same pins
	 * the SPI controller expects; but boards can use other pins.
	 */
	static u8 __initdata spi0_pins[] =
		{ GPIO_PIN_PA(3), GPIO_PIN_PA(4),
		  GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
	static u8 __initdata spi1_pins[] =
		{ GPIO_PIN_PB(2), GPIO_PIN_PB(3),
		  GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
H
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1201
	struct platform_device *pdev;
1202
	u32 pin_mask;
H
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1203 1204 1205

	switch (id) {
	case 0:
1206
		pdev = &atmel_spi0_device;
1207 1208
		pin_mask  = (1 << 1) | (1 << 2);	/* MOSI & SCK */

1209
		/* pullup MISO so a level is always defined */
1210 1211 1212
		select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
		select_peripheral(PIOA, pin_mask, PERIPH_A, 0);

1213
		at32_spi_setup_slaves(0, b, n, spi0_pins);
1214 1215 1216 1217
		break;

	case 1:
		pdev = &atmel_spi1_device;
1218 1219
		pin_mask  = (1 << 1) | (1 << 5);	/* MOSI */

1220
		/* pullup MISO so a level is always defined */
1221 1222 1223
		select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
		select_peripheral(PIOB, pin_mask, PERIPH_B, 0);

1224
		at32_spi_setup_slaves(1, b, n, spi1_pins);
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1225 1226 1227 1228 1229 1230
		break;

	default:
		return NULL;
	}

1231
	spi_register_board_info(b, n);
H
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1232 1233 1234 1235
	platform_device_register(pdev);
	return pdev;
}

1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250
/* --------------------------------------------------------------------
 *  TWI
 * -------------------------------------------------------------------- */
static struct resource atmel_twi0_resource[] __initdata = {
	PBMEM(0xffe00800),
	IRQ(5),
};
static struct clk atmel_twi0_pclk = {
	.name		= "twi_pclk",
	.parent		= &pba_clk,
	.mode		= pba_clk_mode,
	.get_rate	= pba_clk_get_rate,
	.index		= 2,
};

1251 1252 1253
struct platform_device *__init at32_add_device_twi(unsigned int id,
						    struct i2c_board_info *b,
						    unsigned int n)
1254 1255
{
	struct platform_device *pdev;
1256
	u32 pin_mask;
1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268

	if (id != 0)
		return NULL;

	pdev = platform_device_alloc("atmel_twi", id);
	if (!pdev)
		return NULL;

	if (platform_device_add_resources(pdev, atmel_twi0_resource,
				ARRAY_SIZE(atmel_twi0_resource)))
		goto err_add_resources;

1269 1270 1271
	pin_mask  = (1 << 6) | (1 << 7);	/* SDA & SDL */

	select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1272 1273 1274

	atmel_twi0_pclk.dev = &pdev->dev;

1275 1276 1277
	if (b)
		i2c_register_board_info(id, b, n);

1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
	platform_device_add(pdev);
	return pdev;

err_add_resources:
	platform_device_put(pdev);
	return NULL;
}

/* --------------------------------------------------------------------
 * MMC
 * -------------------------------------------------------------------- */
static struct resource atmel_mci0_resource[] __initdata = {
	PBMEM(0xfff02400),
	IRQ(28),
};
static struct clk atmel_mci0_pclk = {
	.name		= "mci_clk",
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.index		= 9,
};

1301 1302
struct platform_device *__init
at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1303
{
1304
	struct platform_device		*pdev;
1305
	struct dw_dma_slave		*dws;
1306 1307
	u32				pioa_mask;
	u32				piob_mask;
1308

1309 1310 1311 1312 1313
	if (id != 0 || !data)
		return NULL;

	/* Must have at least one usable slot */
	if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1314 1315 1316 1317
		return NULL;

	pdev = platform_device_alloc("atmel_mci", id);
	if (!pdev)
1318
		goto fail;
1319 1320 1321

	if (platform_device_add_resources(pdev, atmel_mci0_resource,
				ARRAY_SIZE(atmel_mci0_resource)))
1322 1323
		goto fail;

1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338
	if (data->dma_slave)
		dws = kmemdup(to_dw_dma_slave(data->dma_slave),
				sizeof(struct dw_dma_slave), GFP_KERNEL);
	else
		dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);

	dws->slave.dev = &pdev->dev;
	dws->slave.dma_dev = &dw_dmac0_device.dev;
	dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
	dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
				| DWC_CFGH_DST_PER(1));
	dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
				| DWC_CFGL_HS_SRC_POL);

	data->dma_slave = &dws->slave;
1339 1340 1341 1342

	if (platform_device_add_data(pdev, data,
				sizeof(struct mci_platform_data)))
		goto fail;
1343

1344
	/* CLK line is common to both slots */
1345
	pioa_mask = 1 << 10;
1346 1347 1348

	switch (data->slot[0].bus_width) {
	case 4:
1349 1350 1351
		pioa_mask |= 1 << 13;		/* DATA1 */
		pioa_mask |= 1 << 14;		/* DATA2 */
		pioa_mask |= 1 << 15;		/* DATA3 */
1352 1353
		/* fall through */
	case 1:
1354 1355
		pioa_mask |= 1 << 11;		/* CMD	 */
		pioa_mask |= 1 << 12;		/* DATA0 */
1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368

		if (gpio_is_valid(data->slot[0].detect_pin))
			at32_select_gpio(data->slot[0].detect_pin, 0);
		if (gpio_is_valid(data->slot[0].wp_pin))
			at32_select_gpio(data->slot[0].wp_pin, 0);
		break;
	case 0:
		/* Slot is unused */
		break;
	default:
		goto fail;
	}

1369 1370 1371
	select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
	piob_mask = 0;

1372 1373
	switch (data->slot[1].bus_width) {
	case 4:
1374 1375 1376
		piob_mask |= 1 <<  8;		/* DATA1 */
		piob_mask |= 1 <<  9;		/* DATA2 */
		piob_mask |= 1 << 10;		/* DATA3 */
1377 1378
		/* fall through */
	case 1:
1379 1380 1381
		piob_mask |= 1 <<  6;		/* CMD	 */
		piob_mask |= 1 <<  7;		/* DATA0 */
		select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397

		if (gpio_is_valid(data->slot[1].detect_pin))
			at32_select_gpio(data->slot[1].detect_pin, 0);
		if (gpio_is_valid(data->slot[1].wp_pin))
			at32_select_gpio(data->slot[1].wp_pin, 0);
		break;
	case 0:
		/* Slot is unused */
		break;
	default:
		if (!data->slot[0].bus_width)
			goto fail;

		data->slot[1].bus_width = 0;
		break;
	}
1398

1399 1400 1401 1402 1403
	atmel_mci0_pclk.dev = &pdev->dev;

	platform_device_add(pdev);
	return pdev;

1404
fail:
1405 1406 1407 1408
	platform_device_put(pdev);
	return NULL;
}

H
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1409 1410 1411
/* --------------------------------------------------------------------
 *  LCDC
 * -------------------------------------------------------------------- */
1412
#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1413 1414
static struct atmel_lcdfb_info atmel_lcdfb0_data;
static struct resource atmel_lcdfb0_resource[] = {
H
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1415 1416 1417 1418 1419 1420
	{
		.start		= 0xff000000,
		.end		= 0xff000fff,
		.flags		= IORESOURCE_MEM,
	},
	IRQ(1),
1421 1422 1423 1424 1425 1426
	{
		/* Placeholder for pre-allocated fb memory */
		.start		= 0x00000000,
		.end		= 0x00000000,
		.flags		= 0,
	},
H
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1427
};
1428 1429 1430 1431 1432
DEFINE_DEV_DATA(atmel_lcdfb, 0);
DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
static struct clk atmel_lcdfb0_pixclk = {
	.name		= "lcdc_clk",
	.dev		= &atmel_lcdfb0_device.dev,
H
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1433 1434 1435 1436 1437 1438 1439 1440
	.mode		= genclk_mode,
	.get_rate	= genclk_get_rate,
	.set_rate	= genclk_set_rate,
	.set_parent	= genclk_set_parent,
	.index		= 7,
};

struct platform_device *__init
1441
at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1442
		     unsigned long fbmem_start, unsigned long fbmem_len,
1443
		     u64 pin_mask)
H
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1444 1445
{
	struct platform_device *pdev;
1446 1447 1448 1449
	struct atmel_lcdfb_info *info;
	struct fb_monspecs *monspecs;
	struct fb_videomode *modedb;
	unsigned int modedb_size;
1450
	u32 portc_mask, portd_mask, porte_mask;
1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466

	/*
	 * Do a deep copy of the fb data, monspecs and modedb. Make
	 * sure all allocations are done before setting up the
	 * portmux.
	 */
	monspecs = kmemdup(data->default_monspecs,
			   sizeof(struct fb_monspecs), GFP_KERNEL);
	if (!monspecs)
		return NULL;

	modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
	modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
	if (!modedb)
		goto err_dup_modedb;
	monspecs->modedb = modedb;
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1467 1468 1469

	switch (id) {
	case 0:
1470
		pdev = &atmel_lcdfb0_device;
1471

1472 1473 1474 1475 1476
		if (pin_mask == 0ULL)
			/* Default to "full" lcdc control signals and 24bit */
			pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;

		/* LCDC on port C */
1477 1478
		portc_mask = (pin_mask & 0xfff80000) >> 19;
		select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1479 1480

		/* LCDC on port D */
1481 1482
		portd_mask = pin_mask & 0x0003ffff;
		select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1483 1484

		/* LCDC on port E */
1485 1486
		porte_mask = (pin_mask >> 32) & 0x0007ffff;
		select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
H
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1487

1488 1489
		clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
		clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
H
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1490 1491 1492
		break;

	default:
1493
		goto err_invalid_id;
H
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1494 1495
	}

1496 1497 1498 1499 1500 1501 1502 1503 1504
	if (fbmem_len) {
		pdev->resource[2].start = fbmem_start;
		pdev->resource[2].end = fbmem_start + fbmem_len - 1;
		pdev->resource[2].flags = IORESOURCE_MEM;
	}

	info = pdev->dev.platform_data;
	memcpy(info, data, sizeof(struct atmel_lcdfb_info));
	info->default_monspecs = monspecs;
H
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1505 1506 1507

	platform_device_register(pdev);
	return pdev;
1508 1509 1510 1511 1512 1513

err_invalid_id:
	kfree(modedb);
err_dup_modedb:
	kfree(monspecs);
	return NULL;
H
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1514
}
1515
#endif
H
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1516

1517 1518 1519 1520 1521 1522 1523 1524
/* --------------------------------------------------------------------
 *  PWM
 * -------------------------------------------------------------------- */
static struct resource atmel_pwm0_resource[] __initdata = {
	PBMEM(0xfff01400),
	IRQ(24),
};
static struct clk atmel_pwm0_mck = {
1525
	.name		= "pwm_clk",
1526 1527 1528 1529 1530 1531 1532 1533 1534
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.index		= 5,
};

struct platform_device *__init at32_add_device_pwm(u32 mask)
{
	struct platform_device *pdev;
1535
	u32 pin_mask;
1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550

	if (!mask)
		return NULL;

	pdev = platform_device_alloc("atmel_pwm", 0);
	if (!pdev)
		return NULL;

	if (platform_device_add_resources(pdev, atmel_pwm0_resource,
				ARRAY_SIZE(atmel_pwm0_resource)))
		goto out_free_pdev;

	if (platform_device_add_data(pdev, &mask, sizeof(mask)))
		goto out_free_pdev;

1551
	pin_mask = 0;
1552
	if (mask & (1 << 0))
1553
		pin_mask |= (1 << 28);
1554
	if (mask & (1 << 1))
1555 1556 1557 1558 1559
		pin_mask |= (1 << 29);
	if (pin_mask > 0)
		select_peripheral(PIOA, pin_mask, PERIPH_A, 0);

	pin_mask = 0;
1560
	if (mask & (1 << 2))
1561
		pin_mask |= (1 << 21);
1562
	if (mask & (1 << 3))
1563 1564 1565
		pin_mask |= (1 << 22);
	if (pin_mask > 0)
		select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577

	atmel_pwm0_mck.dev = &pdev->dev;

	platform_device_add(pdev);

	return pdev;

out_free_pdev:
	platform_device_put(pdev);
	return NULL;
}

1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605
/* --------------------------------------------------------------------
 *  SSC
 * -------------------------------------------------------------------- */
static struct resource ssc0_resource[] = {
	PBMEM(0xffe01c00),
	IRQ(10),
};
DEFINE_DEV(ssc, 0);
DEV_CLK(pclk, ssc0, pba, 7);

static struct resource ssc1_resource[] = {
	PBMEM(0xffe02000),
	IRQ(11),
};
DEFINE_DEV(ssc, 1);
DEV_CLK(pclk, ssc1, pba, 8);

static struct resource ssc2_resource[] = {
	PBMEM(0xffe02400),
	IRQ(12),
};
DEFINE_DEV(ssc, 2);
DEV_CLK(pclk, ssc2, pba, 9);

struct platform_device *__init
at32_add_device_ssc(unsigned int id, unsigned int flags)
{
	struct platform_device *pdev;
1606
	u32 pin_mask = 0;
1607 1608 1609 1610 1611

	switch (id) {
	case 0:
		pdev = &ssc0_device;
		if (flags & ATMEL_SSC_RF)
1612
			pin_mask |= (1 << 21);	/* RF */
1613
		if (flags & ATMEL_SSC_RK)
1614
			pin_mask |= (1 << 22);	/* RK */
1615
		if (flags & ATMEL_SSC_TK)
1616
			pin_mask |= (1 << 23);	/* TK */
1617
		if (flags & ATMEL_SSC_TF)
1618
			pin_mask |= (1 << 24);	/* TF */
1619
		if (flags & ATMEL_SSC_TD)
1620
			pin_mask |= (1 << 25);	/* TD */
1621
		if (flags & ATMEL_SSC_RD)
1622 1623 1624 1625 1626
			pin_mask |= (1 << 26);	/* RD */

		if (pin_mask > 0)
			select_peripheral(PIOA, pin_mask, PERIPH_A, 0);

1627 1628 1629 1630
		break;
	case 1:
		pdev = &ssc1_device;
		if (flags & ATMEL_SSC_RF)
1631
			pin_mask |= (1 << 0);	/* RF */
1632
		if (flags & ATMEL_SSC_RK)
1633
			pin_mask |= (1 << 1);	/* RK */
1634
		if (flags & ATMEL_SSC_TK)
1635
			pin_mask |= (1 << 2);	/* TK */
1636
		if (flags & ATMEL_SSC_TF)
1637
			pin_mask |= (1 << 3);	/* TF */
1638
		if (flags & ATMEL_SSC_TD)
1639
			pin_mask |= (1 << 4);	/* TD */
1640
		if (flags & ATMEL_SSC_RD)
1641 1642 1643 1644 1645
			pin_mask |= (1 << 5);	/* RD */

		if (pin_mask > 0)
			select_peripheral(PIOA, pin_mask, PERIPH_B, 0);

1646 1647 1648 1649
		break;
	case 2:
		pdev = &ssc2_device;
		if (flags & ATMEL_SSC_TD)
1650
			pin_mask |= (1 << 13);	/* TD */
1651
		if (flags & ATMEL_SSC_RD)
1652
			pin_mask |= (1 << 14);	/* RD */
1653
		if (flags & ATMEL_SSC_TK)
1654
			pin_mask |= (1 << 15);	/* TK */
1655
		if (flags & ATMEL_SSC_TF)
1656
			pin_mask |= (1 << 16);	/* TF */
1657
		if (flags & ATMEL_SSC_RF)
1658
			pin_mask |= (1 << 17);	/* RF */
1659
		if (flags & ATMEL_SSC_RK)
1660 1661 1662 1663 1664
			pin_mask |= (1 << 18);	/* RK */

		if (pin_mask > 0)
			select_peripheral(PIOB, pin_mask, PERIPH_A, 0);

1665 1666 1667 1668 1669 1670 1671 1672 1673
		break;
	default:
		return NULL;
	}

	platform_device_register(pdev);
	return pdev;
}

H
Haavard Skinnemoen 已提交
1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703
/* --------------------------------------------------------------------
 *  USB Device Controller
 * -------------------------------------------------------------------- */
static struct resource usba0_resource[] __initdata = {
	{
		.start		= 0xff300000,
		.end		= 0xff3fffff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= 0xfff03000,
		.end		= 0xfff033ff,
		.flags		= IORESOURCE_MEM,
	},
	IRQ(31),
};
static struct clk usba0_pclk = {
	.name		= "pclk",
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.index		= 12,
};
static struct clk usba0_hclk = {
	.name		= "hclk",
	.parent		= &hsb_clk,
	.mode		= hsb_clk_mode,
	.get_rate	= hsb_clk_get_rate,
	.index		= 6,
};

1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
#define EP(nam, idx, maxpkt, maxbk, dma, isoc)			\
	[idx] = {						\
		.name		= nam,				\
		.index		= idx,				\
		.fifo_size	= maxpkt,			\
		.nr_banks	= maxbk,			\
		.can_dma	= dma,				\
		.can_isoc	= isoc,				\
	}

static struct usba_ep_data at32_usba_ep[] __initdata = {
	EP("ep0",     0,   64, 1, 0, 0),
	EP("ep1",     1,  512, 2, 1, 1),
	EP("ep2",     2,  512, 2, 1, 1),
	EP("ep3-int", 3,   64, 3, 1, 0),
	EP("ep4-int", 4,   64, 3, 1, 0),
	EP("ep5",     5, 1024, 3, 1, 1),
	EP("ep6",     6, 1024, 3, 1, 1),
};

#undef EP

H
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1726 1727 1728
struct platform_device *__init
at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
{
1729 1730 1731 1732 1733 1734 1735 1736
	/*
	 * pdata doesn't have room for any endpoints, so we need to
	 * append room for the ones we need right after it.
	 */
	struct {
		struct usba_platform_data pdata;
		struct usba_ep_data ep[7];
	} usba_data;
H
Haavard Skinnemoen 已提交
1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749
	struct platform_device *pdev;

	if (id != 0)
		return NULL;

	pdev = platform_device_alloc("atmel_usba_udc", 0);
	if (!pdev)
		return NULL;

	if (platform_device_add_resources(pdev, usba0_resource,
					  ARRAY_SIZE(usba0_resource)))
		goto out_free_pdev;

1750 1751 1752 1753
	if (data)
		usba_data.pdata.vbus_pin = data->vbus_pin;
	else
		usba_data.pdata.vbus_pin = -EINVAL;
H
Haavard Skinnemoen 已提交
1754

1755 1756 1757 1758 1759 1760 1761 1762 1763
	data = &usba_data.pdata;
	data->num_ep = ARRAY_SIZE(at32_usba_ep);
	memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));

	if (platform_device_add_data(pdev, data, sizeof(usba_data)))
		goto out_free_pdev;

	if (data->vbus_pin >= 0)
		at32_select_gpio(data->vbus_pin, 0);
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1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776

	usba0_pclk.dev = &pdev->dev;
	usba0_hclk.dev = &pdev->dev;

	platform_device_add(pdev);

	return pdev;

out_free_pdev:
	platform_device_put(pdev);
	return NULL;
}

1777
/* --------------------------------------------------------------------
1778
 * IDE / CompactFlash
1779
 * -------------------------------------------------------------------- */
1780
#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1781
static struct resource at32_smc_cs4_resource[] __initdata = {
1782 1783 1784 1785 1786 1787 1788
	{
		.start	= 0x04000000,
		.end	= 0x07ffffff,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(~0UL), /* Magic IRQ will be overridden */
};
1789 1790 1791 1792 1793 1794 1795 1796
static struct resource at32_smc_cs5_resource[] __initdata = {
	{
		.start	= 0x20000000,
		.end	= 0x23ffffff,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(~0UL), /* Magic IRQ will be overridden */
};
1797

1798 1799
static int __init at32_init_ide_or_cf(struct platform_device *pdev,
		unsigned int cs, unsigned int extint)
1800
{
1801
	static unsigned int extint_pin_map[4] __initdata = {
1802 1803 1804 1805
		(1 << 25),
		(1 << 26),
		(1 << 27),
		(1 << 28),
1806 1807
	};
	static bool common_pins_initialized __initdata = false;
1808
	unsigned int extint_pin;
1809
	int ret;
1810
	u32 pin_mask;
1811

1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823
	if (extint >= ARRAY_SIZE(extint_pin_map))
		return -EINVAL;
	extint_pin = extint_pin_map[extint];

	switch (cs) {
	case 4:
		ret = platform_device_add_resources(pdev,
				at32_smc_cs4_resource,
				ARRAY_SIZE(at32_smc_cs4_resource));
		if (ret)
			return ret;

1824 1825
		/* NCS4   -> OE_N  */
		select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1826
		hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1827
		break;
1828 1829 1830 1831 1832 1833 1834
	case 5:
		ret = platform_device_add_resources(pdev,
				at32_smc_cs5_resource,
				ARRAY_SIZE(at32_smc_cs5_resource));
		if (ret)
			return ret;

1835 1836
		/* NCS5   -> OE_N  */
		select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1837
		hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1838 1839
		break;
	default:
1840
		return -EINVAL;
1841 1842
	}

1843
	if (!common_pins_initialized) {
1844 1845 1846 1847 1848 1849 1850
		pin_mask  = (1 << 19);	/* CFCE1  -> CS0_N */
		pin_mask |= (1 << 20);	/* CFCE2  -> CS1_N */
		pin_mask |= (1 << 23);	/* CFRNW  -> DIR   */
		pin_mask |= (1 << 24);	/* NWAIT  <- IORDY */

		select_peripheral(PIOE, pin_mask, PERIPH_A, 0);

1851
		common_pins_initialized = true;
1852 1853
	}

1854
	select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1855 1856 1857 1858

	pdev->resource[1].start = EIM_IRQ_BASE + extint;
	pdev->resource[1].end = pdev->resource[1].start;

1859 1860
	return 0;
}
1861

1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895
struct platform_device *__init
at32_add_device_ide(unsigned int id, unsigned int extint,
		    struct ide_platform_data *data)
{
	struct platform_device *pdev;

	pdev = platform_device_alloc("at32_ide", id);
	if (!pdev)
		goto fail;

	if (platform_device_add_data(pdev, data,
				sizeof(struct ide_platform_data)))
		goto fail;

	if (at32_init_ide_or_cf(pdev, data->cs, extint))
		goto fail;

	platform_device_add(pdev);
	return pdev;

fail:
	platform_device_put(pdev);
	return NULL;
}

struct platform_device *__init
at32_add_device_cf(unsigned int id, unsigned int extint,
		    struct cf_platform_data *data)
{
	struct platform_device *pdev;

	pdev = platform_device_alloc("at32_cf", id);
	if (!pdev)
		goto fail;
1896

1897 1898 1899 1900 1901 1902 1903
	if (platform_device_add_data(pdev, data,
				sizeof(struct cf_platform_data)))
		goto fail;

	if (at32_init_ide_or_cf(pdev, data->cs, extint))
		goto fail;

D
David Brownell 已提交
1904
	if (gpio_is_valid(data->detect_pin))
1905
		at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
D
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1906
	if (gpio_is_valid(data->reset_pin))
1907
		at32_select_gpio(data->reset_pin, 0);
D
David Brownell 已提交
1908
	if (gpio_is_valid(data->vcc_pin))
1909 1910 1911 1912
		at32_select_gpio(data->vcc_pin, 0);
	/* READY is used as extint, so we can't select it as gpio */

	platform_device_add(pdev);
1913
	return pdev;
1914 1915 1916 1917

fail:
	platform_device_put(pdev);
	return NULL;
1918
}
1919
#endif
1920

1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955
/* --------------------------------------------------------------------
 * NAND Flash / SmartMedia
 * -------------------------------------------------------------------- */
static struct resource smc_cs3_resource[] __initdata = {
	{
		.start	= 0x0c000000,
		.end	= 0x0fffffff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= 0xfff03c00,
		.end	= 0xfff03fff,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device *__init
at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
{
	struct platform_device *pdev;

	if (id != 0 || !data)
		return NULL;

	pdev = platform_device_alloc("atmel_nand", id);
	if (!pdev)
		goto fail;

	if (platform_device_add_resources(pdev, smc_cs3_resource,
				ARRAY_SIZE(smc_cs3_resource)))
		goto fail;

	if (platform_device_add_data(pdev, data,
				sizeof(struct atmel_nand_data)))
		goto fail;

1956
	hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972
	if (data->enable_pin)
		at32_select_gpio(data->enable_pin,
				AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
	if (data->rdy_pin)
		at32_select_gpio(data->rdy_pin, 0);
	if (data->det_pin)
		at32_select_gpio(data->det_pin, 0);

	platform_device_add(pdev);
	return pdev;

fail:
	platform_device_put(pdev);
	return NULL;
}

1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987
/* --------------------------------------------------------------------
 * AC97C
 * -------------------------------------------------------------------- */
static struct resource atmel_ac97c0_resource[] __initdata = {
	PBMEM(0xfff02800),
	IRQ(29),
};
static struct clk atmel_ac97c0_pclk = {
	.name		= "pclk",
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.index		= 10,
};

1988 1989
struct platform_device *__init
at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1990 1991
{
	struct platform_device *pdev;
1992
	struct ac97c_platform_data _data;
1993
	u32 pin_mask;
1994 1995 1996 1997 1998 1999 2000 2001 2002 2003

	if (id != 0)
		return NULL;

	pdev = platform_device_alloc("atmel_ac97c", id);
	if (!pdev)
		return NULL;

	if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
				ARRAY_SIZE(atmel_ac97c0_resource)))
2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014
		goto fail;

	if (!data) {
		data = &_data;
		memset(data, 0, sizeof(struct ac97c_platform_data));
		data->reset_pin = GPIO_PIN_NONE;
	}

	data->dma_rx_periph_id = 3;
	data->dma_tx_periph_id = 4;
	data->dma_controller_id = 0;
2015

2016 2017 2018 2019
	if (platform_device_add_data(pdev, data,
				sizeof(struct ac97c_platform_data)))
		goto fail;

2020 2021 2022 2023
	pin_mask  = (1 << 20) | (1 << 21);	/* SDO & SYNC */
	pin_mask |= (1 << 22) | (1 << 23);	/* SCLK & SDI */

	select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2024 2025 2026 2027

	/* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
	if (data->reset_pin != GPIO_PIN_NONE)
		at32_select_gpio(data->reset_pin, 0);
2028 2029 2030 2031 2032 2033

	atmel_ac97c0_pclk.dev = &pdev->dev;

	platform_device_add(pdev);
	return pdev;

2034
fail:
2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064
	platform_device_put(pdev);
	return NULL;
}

/* --------------------------------------------------------------------
 * ABDAC
 * -------------------------------------------------------------------- */
static struct resource abdac0_resource[] __initdata = {
	PBMEM(0xfff02000),
	IRQ(27),
};
static struct clk abdac0_pclk = {
	.name		= "pclk",
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.index		= 8,
};
static struct clk abdac0_sample_clk = {
	.name		= "sample_clk",
	.mode		= genclk_mode,
	.get_rate	= genclk_get_rate,
	.set_rate	= genclk_set_rate,
	.set_parent	= genclk_set_parent,
	.index		= 6,
};

struct platform_device *__init at32_add_device_abdac(unsigned int id)
{
	struct platform_device *pdev;
2065
	u32 pin_mask;
2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077

	if (id != 0)
		return NULL;

	pdev = platform_device_alloc("abdac", id);
	if (!pdev)
		return NULL;

	if (platform_device_add_resources(pdev, abdac0_resource,
				ARRAY_SIZE(abdac0_resource)))
		goto err_add_resources;

2078 2079 2080 2081
	pin_mask  = (1 << 20) | (1 << 22);	/* DATA1 & DATAN1 */
	pin_mask |= (1 << 21) | (1 << 23);	/* DATA0 & DATAN0 */

	select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093

	abdac0_pclk.dev = &pdev->dev;
	abdac0_sample_clk.dev = &pdev->dev;

	platform_device_add(pdev);
	return pdev;

err_add_resources:
	platform_device_put(pdev);
	return NULL;
}

2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137
/* --------------------------------------------------------------------
 *  GCLK
 * -------------------------------------------------------------------- */
static struct clk gclk0 = {
	.name		= "gclk0",
	.mode		= genclk_mode,
	.get_rate	= genclk_get_rate,
	.set_rate	= genclk_set_rate,
	.set_parent	= genclk_set_parent,
	.index		= 0,
};
static struct clk gclk1 = {
	.name		= "gclk1",
	.mode		= genclk_mode,
	.get_rate	= genclk_get_rate,
	.set_rate	= genclk_set_rate,
	.set_parent	= genclk_set_parent,
	.index		= 1,
};
static struct clk gclk2 = {
	.name		= "gclk2",
	.mode		= genclk_mode,
	.get_rate	= genclk_get_rate,
	.set_rate	= genclk_set_rate,
	.set_parent	= genclk_set_parent,
	.index		= 2,
};
static struct clk gclk3 = {
	.name		= "gclk3",
	.mode		= genclk_mode,
	.get_rate	= genclk_get_rate,
	.set_rate	= genclk_set_rate,
	.set_parent	= genclk_set_parent,
	.index		= 3,
};
static struct clk gclk4 = {
	.name		= "gclk4",
	.mode		= genclk_mode,
	.get_rate	= genclk_get_rate,
	.set_rate	= genclk_set_rate,
	.set_parent	= genclk_set_parent,
	.index		= 4,
};

2138
static __initdata struct clk *init_clocks[] = {
H
Haavard Skinnemoen 已提交
2139 2140 2141 2142 2143 2144 2145 2146 2147
	&osc32k,
	&osc0,
	&osc1,
	&pll0,
	&pll1,
	&cpu_clk,
	&hsb_clk,
	&pba_clk,
	&pbb_clk,
2148
	&at32_pm_pclk,
H
Haavard Skinnemoen 已提交
2149
	&at32_intc0_pclk,
2150
	&at32_hmatrix_clk,
H
Haavard Skinnemoen 已提交
2151 2152
	&ebi_clk,
	&hramc_clk,
2153
	&sdramc_clk,
2154 2155
	&smc0_pclk,
	&smc0_mck,
H
Haavard Skinnemoen 已提交
2156 2157
	&pdc_hclk,
	&pdc_pclk,
2158
	&dw_dmac0_hclk,
H
Haavard Skinnemoen 已提交
2159 2160 2161 2162 2163
	&pico_clk,
	&pio0_mck,
	&pio1_mck,
	&pio2_mck,
	&pio3_mck,
2164
	&pio4_mck,
2165 2166
	&at32_tcb0_t0_clk,
	&at32_tcb1_t0_clk,
2167 2168
	&atmel_psif0_pclk,
	&atmel_psif1_pclk,
2169 2170 2171 2172
	&atmel_usart0_usart,
	&atmel_usart1_usart,
	&atmel_usart2_usart,
	&atmel_usart3_usart,
2173
	&atmel_pwm0_mck,
2174
#if defined(CONFIG_CPU_AT32AP7000)
H
Haavard Skinnemoen 已提交
2175 2176
	&macb0_hclk,
	&macb0_pclk,
2177 2178
	&macb1_hclk,
	&macb1_pclk,
2179
#endif
2180 2181
	&atmel_spi0_spi_clk,
	&atmel_spi1_spi_clk,
2182 2183
	&atmel_twi0_pclk,
	&atmel_mci0_pclk,
2184
#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2185 2186
	&atmel_lcdfb0_hck1,
	&atmel_lcdfb0_pixclk,
2187
#endif
2188 2189 2190
	&ssc0_pclk,
	&ssc1_pclk,
	&ssc2_pclk,
H
Haavard Skinnemoen 已提交
2191 2192
	&usba0_hclk,
	&usba0_pclk,
2193 2194 2195
	&atmel_ac97c0_pclk,
	&abdac0_pclk,
	&abdac0_sample_clk,
2196 2197 2198 2199 2200
	&gclk0,
	&gclk1,
	&gclk2,
	&gclk3,
	&gclk4,
H
Haavard Skinnemoen 已提交
2201 2202
};

2203
void __init setup_platform(void)
H
Haavard Skinnemoen 已提交
2204 2205 2206 2207
{
	u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
	int i;

2208
	if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
H
Haavard Skinnemoen 已提交
2209
		main_clock = &pll0;
2210 2211
		cpu_clk.parent = &pll0;
	} else {
H
Haavard Skinnemoen 已提交
2212
		main_clock = &osc0;
2213 2214
		cpu_clk.parent = &osc0;
	}
H
Haavard Skinnemoen 已提交
2215

2216
	if (pm_readl(PLL0) & PM_BIT(PLLOSC))
H
Haavard Skinnemoen 已提交
2217
		pll0.parent = &osc1;
2218
	if (pm_readl(PLL1) & PM_BIT(PLLOSC))
H
Haavard Skinnemoen 已提交
2219 2220
		pll1.parent = &osc1;

2221 2222 2223 2224 2225
	genclk_init_parent(&gclk0);
	genclk_init_parent(&gclk1);
	genclk_init_parent(&gclk2);
	genclk_init_parent(&gclk3);
	genclk_init_parent(&gclk4);
2226
#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2227
	genclk_init_parent(&atmel_lcdfb0_pixclk);
2228
#endif
2229
	genclk_init_parent(&abdac0_sample_clk);
2230

H
Haavard Skinnemoen 已提交
2231
	/*
2232 2233 2234 2235 2236 2237 2238
	 * Build initial dynamic clock list by registering all clocks
	 * from the array.
	 * At the same time, turn on all clocks that have at least one
	 * user already, and turn off everything else. We only do this
	 * for module clocks, and even though it isn't particularly
	 * pretty to  check the address of the mode function, it should
	 * do the trick...
H
Haavard Skinnemoen 已提交
2239
	 */
2240 2241 2242 2243 2244
	for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
		struct clk *clk = init_clocks[i];

		/* first, register clock */
		at32_clk_register(clk);
H
Haavard Skinnemoen 已提交
2245

2246 2247 2248
		if (clk->users == 0)
			continue;

H
Haavard Skinnemoen 已提交
2249 2250 2251 2252 2253 2254 2255 2256 2257 2258
		if (clk->mode == &cpu_clk_mode)
			cpu_mask |= 1 << clk->index;
		else if (clk->mode == &hsb_clk_mode)
			hsb_mask |= 1 << clk->index;
		else if (clk->mode == &pba_clk_mode)
			pba_mask |= 1 << clk->index;
		else if (clk->mode == &pbb_clk_mode)
			pbb_mask |= 1 << clk->index;
	}

2259 2260 2261 2262
	pm_writel(CPU_MASK, cpu_mask);
	pm_writel(HSB_MASK, hsb_mask);
	pm_writel(PBA_MASK, pba_mask);
	pm_writel(PBB_MASK, pbb_mask);
2263 2264 2265 2266 2267 2268 2269

	/* Initialize the port muxes */
	at32_init_pio(&pio0_device);
	at32_init_pio(&pio1_device);
	at32_init_pio(&pio2_device);
	at32_init_pio(&pio3_device);
	at32_init_pio(&pio4_device);
H
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2270
}
2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295

struct gen_pool *sram_pool;

static int __init sram_init(void)
{
	struct gen_pool *pool;

	/* 1KiB granularity */
	pool = gen_pool_create(10, -1);
	if (!pool)
		goto fail;

	if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
		goto err_pool_add;

	sram_pool = pool;
	return 0;

err_pool_add:
	gen_pool_destroy(pool);
fail:
	pr_err("Failed to create SRAM pool\n");
	return -ENOMEM;
}
core_initcall(sram_init);