entry_64.S 29.5 KB
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/*
 *  PowerPC version 
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
 *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
 *  Adapted for Power Macintosh by Paul Mackerras.
 *  Low-level exception handlers and MMU support
 *  rewritten by Paul Mackerras.
 *    Copyright (C) 1996 Paul Mackerras.
 *  MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
 *
 *  This file contains the system call entry code, context switch
 *  code, and exception/interrupt return code for PowerPC.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#include <linux/errno.h>
#include <asm/unistd.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cputable.h>
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#include <asm/firmware.h>
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#include <asm/bug.h>
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#include <asm/ptrace.h>
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#include <asm/irqflags.h>
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#include <asm/ftrace.h>
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#include <asm/hw_irq.h>
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#include <asm/context_tracking.h>
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/*
 * System calls.
 */
	.section	".toc","aw"
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SYS_CALL_TABLE:
	.tc sys_call_table[TC],sys_call_table
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/* This value is used to mark exception frames on the stack. */
exception_marker:
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	.tc	ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
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	.section	".text"
	.align 7

#undef SHOW_SYSCALLS

	.globl system_call_common
system_call_common:
	andi.	r10,r12,MSR_PR
	mr	r10,r1
	addi	r1,r1,-INT_FRAME_SIZE
	beq-	1f
	ld	r1,PACAKSAVE(r13)
1:	std	r10,0(r1)
	std	r11,_NIP(r1)
	std	r12,_MSR(r1)
	std	r0,GPR0(r1)
	std	r10,GPR1(r1)
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	beq	2f			/* if from kernel mode */
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	ACCOUNT_CPU_USER_ENTRY(r10, r11)
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2:	std	r2,GPR2(r1)
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	std	r3,GPR3(r1)
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	mfcr	r2
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	std	r4,GPR4(r1)
	std	r5,GPR5(r1)
	std	r6,GPR6(r1)
	std	r7,GPR7(r1)
	std	r8,GPR8(r1)
	li	r11,0
	std	r11,GPR9(r1)
	std	r11,GPR10(r1)
	std	r11,GPR11(r1)
	std	r11,GPR12(r1)
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	std	r11,_XER(r1)
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	std	r11,_CTR(r1)
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	std	r9,GPR13(r1)
	mflr	r10
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	/*
	 * This clears CR0.SO (bit 28), which is the error indication on
	 * return from this system call.
	 */
	rldimi	r2,r11,28,(63-28)
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	li	r11,0xc01
	std	r10,_LINK(r1)
	std	r11,_TRAP(r1)
	std	r3,ORIG_GPR3(r1)
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	std	r2,_CCR(r1)
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	ld	r2,PACATOC(r13)
	addi	r9,r1,STACK_FRAME_OVERHEAD
	ld	r11,exception_marker@toc(r2)
	std	r11,-16(r9)		/* "regshere" marker */
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#if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
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BEGIN_FW_FTR_SECTION
	beq	33f
	/* if from user, see if there are any DTL entries to process */
	ld	r10,PACALPPACAPTR(r13)	/* get ptr to VPA */
	ld	r11,PACA_DTL_RIDX(r13)	/* get log read index */
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	addi	r10,r10,LPPACA_DTLIDX
	LDX_BE	r10,0,r10		/* get log write index */
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	cmpd	cr1,r11,r10
	beq+	cr1,33f
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	bl	accumulate_stolen_time
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	REST_GPR(0,r1)
	REST_4GPRS(3,r1)
	REST_2GPRS(7,r1)
	addi	r9,r1,STACK_FRAME_OVERHEAD
33:
END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
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#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
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	/*
	 * A syscall should always be called with interrupts enabled
	 * so we just unconditionally hard-enable here. When some kind
	 * of irq tracing is used, we additionally check that condition
	 * is correct
	 */
#if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
	lbz	r10,PACASOFTIRQEN(r13)
	xori	r10,r10,1
1:	tdnei	r10,0
	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
#endif
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#ifdef CONFIG_PPC_BOOK3E
	wrteei	1
#else
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	ld	r11,PACAKMSR(r13)
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	ori	r11,r11,MSR_EE
	mtmsrd	r11,1
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#endif /* CONFIG_PPC_BOOK3E */
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	/* We do need to set SOFTE in the stack frame or the return
	 * from interrupt will be painful
	 */
	li	r10,1
	std	r10,SOFTE(r1)

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#ifdef SHOW_SYSCALLS
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	bl	do_show_syscall
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	REST_GPR(0,r1)
	REST_4GPRS(3,r1)
	REST_2GPRS(7,r1)
	addi	r9,r1,STACK_FRAME_OVERHEAD
#endif
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	CURRENT_THREAD_INFO(r11, r1)
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	ld	r10,TI_FLAGS(r11)
	andi.	r11,r10,_TIF_SYSCALL_T_OR_A
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	bne	syscall_dotrace
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.Lsyscall_dotrace_cont:
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	cmpldi	0,r0,NR_syscalls
	bge-	syscall_enosys

system_call:			/* label this so stack traces look sane */
/*
 * Need to vector to 32 Bit or default sys_call_table here,
 * based on caller's run-mode / personality.
 */
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	ld	r11,SYS_CALL_TABLE@toc(2)
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	andi.	r10,r10,_TIF_32BIT
	beq	15f
	addi	r11,r11,8	/* use 32-bit syscall entries */
	clrldi	r3,r3,32
	clrldi	r4,r4,32
	clrldi	r5,r5,32
	clrldi	r6,r6,32
	clrldi	r7,r7,32
	clrldi	r8,r8,32
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	slwi	r0,r0,4
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	ldx	r12,r11,r0	/* Fetch system call handler [ptr] */
	mtctr   r12
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	bctrl			/* Call handler */

syscall_exit:
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	std	r3,RESULT(r1)
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#ifdef SHOW_SYSCALLS
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	bl	do_show_syscall_exit
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	ld	r3,RESULT(r1)
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#endif
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	CURRENT_THREAD_INFO(r12, r1)
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	ld	r8,_MSR(r1)
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#ifdef CONFIG_PPC_BOOK3S
	/* No MSR:RI on BookE */
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	andi.	r10,r8,MSR_RI
	beq-	unrecov_restore
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#endif
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	/*
	 * Disable interrupts so current_thread_info()->flags can't change,
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	 * and so that we don't get interrupted after loading SRR0/1.
	 */
#ifdef CONFIG_PPC_BOOK3E
	wrteei	0
#else
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	ld	r10,PACAKMSR(r13)
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	/*
	 * For performance reasons we clear RI the same time that we
	 * clear EE. We only need to clear RI just before we restore r13
	 * below, but batching it with EE saves us one expensive mtmsrd call.
	 * We have to be careful to restore RI if we branch anywhere from
	 * here (eg syscall_exit_work).
	 */
	li	r9,MSR_RI
	andc	r11,r10,r9
	mtmsrd	r11,1
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#endif /* CONFIG_PPC_BOOK3E */

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	ld	r9,TI_FLAGS(r12)
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	li	r11,-_LAST_ERRNO
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	andi.	r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
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	bne-	syscall_exit_work
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	cmpld	r3,r11
	ld	r5,_CCR(r1)
	bge-	syscall_error
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.Lsyscall_error_cont:
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	ld	r7,_NIP(r1)
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BEGIN_FTR_SECTION
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	stdcx.	r0,0,r1			/* to clear the reservation */
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END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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	andi.	r6,r8,MSR_PR
	ld	r4,_LINK(r1)
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	beq-	1f
	ACCOUNT_CPU_USER_EXIT(r11, r12)
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	HMT_MEDIUM_LOW_HAS_PPR
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	ld	r13,GPR13(r1)	/* only restore r13 if returning to usermode */
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1:	ld	r2,GPR2(r1)
	ld	r1,GPR1(r1)
	mtlr	r4
	mtcr	r5
	mtspr	SPRN_SRR0,r7
	mtspr	SPRN_SRR1,r8
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	RFI
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	b	.	/* prevent speculative execution */

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syscall_error:	
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	oris	r5,r5,0x1000	/* Set SO bit in CR */
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	neg	r3,r3
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	std	r5,_CCR(r1)
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	b	.Lsyscall_error_cont
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/* Traced system call support */
syscall_dotrace:
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	bl	save_nvgprs
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	addi	r3,r1,STACK_FRAME_OVERHEAD
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	bl	do_syscall_trace_enter
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	/*
	 * Restore argument registers possibly just changed.
	 * We use the return value of do_syscall_trace_enter
	 * for the call number to look up in the table (r0).
	 */
	mr	r0,r3
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	ld	r3,GPR3(r1)
	ld	r4,GPR4(r1)
	ld	r5,GPR5(r1)
	ld	r6,GPR6(r1)
	ld	r7,GPR7(r1)
	ld	r8,GPR8(r1)
	addi	r9,r1,STACK_FRAME_OVERHEAD
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	CURRENT_THREAD_INFO(r10, r1)
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	ld	r10,TI_FLAGS(r10)
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	b	.Lsyscall_dotrace_cont
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syscall_enosys:
	li	r3,-ENOSYS
	b	syscall_exit
	
syscall_exit_work:
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#ifdef CONFIG_PPC_BOOK3S
	mtmsrd	r10,1		/* Restore RI */
#endif
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	/* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
	 If TIF_NOERROR is set, just save r3 as it is. */

	andi.	r0,r9,_TIF_RESTOREALL
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	beq+	0f
	REST_NVGPRS(r1)
	b	2f
0:	cmpld	r3,r11		/* r10 is -LAST_ERRNO */
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	blt+	1f
	andi.	r0,r9,_TIF_NOERROR
	bne-	1f
	ld	r5,_CCR(r1)
	neg	r3,r3
	oris	r5,r5,0x1000	/* Set SO bit in CR */
	std	r5,_CCR(r1)
1:	std	r3,GPR3(r1)
2:	andi.	r0,r9,(_TIF_PERSYSCALL_MASK)
	beq	4f

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	/* Clear per-syscall TIF flags if any are set.  */
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	li	r11,_TIF_PERSYSCALL_MASK
	addi	r12,r12,TI_FLAGS
3:	ldarx	r10,0,r12
	andc	r10,r10,r11
	stdcx.	r10,0,r12
	bne-	3b
	subi	r12,r12,TI_FLAGS
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4:	/* Anything else left to do? */
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	SET_DEFAULT_THREAD_PPR(r3, r10)		/* Set thread.ppr = 3 */
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	andi.	r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
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	beq	ret_from_except_lite
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	/* Re-enable interrupts */
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#ifdef CONFIG_PPC_BOOK3E
	wrteei	1
#else
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	ld	r10,PACAKMSR(r13)
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	ori	r10,r10,MSR_EE
	mtmsrd	r10,1
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#endif /* CONFIG_PPC_BOOK3E */
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	bl	save_nvgprs
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	addi	r3,r1,STACK_FRAME_OVERHEAD
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	bl	do_syscall_trace_leave
	b	ret_from_except
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/* Save non-volatile GPRs, if not already saved. */
_GLOBAL(save_nvgprs)
	ld	r11,_TRAP(r1)
	andi.	r0,r11,1
	beqlr-
	SAVE_NVGPRS(r1)
	clrrdi	r0,r11,1
	std	r0,_TRAP(r1)
	blr

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/*
 * The sigsuspend and rt_sigsuspend system calls can call do_signal
 * and thus put the process into the stopped state where we might
 * want to examine its user state with ptrace.  Therefore we need
 * to save all the nonvolatile registers (r14 - r31) before calling
 * the C code.  Similarly, fork, vfork and clone need the full
 * register state on the stack so that it can be copied to the child.
 */

_GLOBAL(ppc_fork)
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	bl	save_nvgprs
	bl	sys_fork
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	b	syscall_exit

_GLOBAL(ppc_vfork)
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	bl	save_nvgprs
	bl	sys_vfork
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	b	syscall_exit

_GLOBAL(ppc_clone)
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	bl	save_nvgprs
	bl	sys_clone
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	b	syscall_exit

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_GLOBAL(ppc32_swapcontext)
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	bl	save_nvgprs
	bl	compat_sys_swapcontext
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	b	syscall_exit

_GLOBAL(ppc64_swapcontext)
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	bl	save_nvgprs
	bl	sys_swapcontext
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	b	syscall_exit

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_GLOBAL(ret_from_fork)
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	bl	schedule_tail
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	REST_NVGPRS(r1)
	li	r3,0
	b	syscall_exit

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Al Viro 已提交
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_GLOBAL(ret_from_kernel_thread)
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	bl	schedule_tail
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	REST_NVGPRS(r1)
	mtlr	r14
	mr	r3,r15
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#if defined(_CALL_ELF) && _CALL_ELF == 2
	mr	r12,r14
#endif
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	blrl
	li	r3,0
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	b	syscall_exit

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/*
 * This routine switches between two different tasks.  The process
 * state of one is saved on its kernel stack.  Then the state
 * of the other is restored from its kernel stack.  The memory
 * management hardware is updated to the second process's state.
 * Finally, we can return to the second process, via ret_from_except.
 * On entry, r3 points to the THREAD for the current task, r4
 * points to the THREAD for the new task.
 *
 * Note: there are two ways to get to the "going out" portion
 * of this code; either by coming in via the entry (_switch)
 * or via "fork" which must set up an environment equivalent
 * to the "_switch" path.  If you change this you'll have to change
 * the fork code also.
 *
 * The code which creates the new task context is in 'copy_thread'
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 * in arch/powerpc/kernel/process.c 
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 */
	.align	7
_GLOBAL(_switch)
	mflr	r0
	std	r0,16(r1)
	stdu	r1,-SWITCH_FRAME_SIZE(r1)
	/* r3-r13 are caller saved -- Cort */
	SAVE_8GPRS(14, r1)
	SAVE_10GPRS(22, r1)
	mflr	r20		/* Return to switch caller */
	mfmsr	r22
	li	r0, MSR_FP
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#ifdef CONFIG_VSX
BEGIN_FTR_SECTION
	oris	r0,r0,MSR_VSX@h	/* Disable VSX */
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
#endif /* CONFIG_VSX */
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#ifdef CONFIG_ALTIVEC
BEGIN_FTR_SECTION
	oris	r0,r0,MSR_VEC@h	/* Disable altivec */
	mfspr	r24,SPRN_VRSAVE	/* save vrsave register value */
	std	r24,THREAD_VRSAVE(r3)
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
#endif /* CONFIG_ALTIVEC */
	and.	r0,r0,r22
	beq+	1f
	andc	r22,r22,r0
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	MTMSRD(r22)
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	isync
1:	std	r20,_NIP(r1)
	mfcr	r23
	std	r23,_CCR(r1)
	std	r1,KSP(r3)	/* Set old stack pointer */

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#ifdef CONFIG_PPC_BOOK3S_64
BEGIN_FTR_SECTION
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	/* Event based branch registers */
	mfspr	r0, SPRN_BESCR
	std	r0, THREAD_BESCR(r3)
	mfspr	r0, SPRN_EBBHR
	std	r0, THREAD_EBBHR(r3)
	mfspr	r0, SPRN_EBBRR
	std	r0, THREAD_EBBRR(r3)
450
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
451 452
#endif

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#ifdef CONFIG_SMP
	/* We need a sync somewhere here to make sure that if the
	 * previous task gets rescheduled on another CPU, it sees all
	 * stores it has performed on this one.
	 */
	sync
#endif /* CONFIG_SMP */

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	/*
	 * If we optimise away the clear of the reservation in system
	 * calls because we know the CPU tracks the address of the
	 * reservation, then we need to clear it here to cover the
	 * case that the kernel context switch path has no larx
	 * instructions.
	 */
BEGIN_FTR_SECTION
	ldarx	r6,0,r1
END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)

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#ifdef CONFIG_PPC_BOOK3S
/* Cancel all explict user streams as they will have no use after context
 * switch and will stop the HW from creating streams itself
 */
	DCBT_STOP_ALL_STREAM_IDS(r6)
#endif

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	addi	r6,r4,-THREAD	/* Convert THREAD to 'current' */
	std	r6,PACACURRENT(r13)	/* Set new 'current' */

	ld	r8,KSP(r4)	/* new stack pointer */
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#ifdef CONFIG_PPC_BOOK3S
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Paul Mackerras 已提交
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BEGIN_FTR_SECTION
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	clrrdi	r6,r8,28	/* get its ESID */
	clrrdi	r9,r1,28	/* get current sp ESID */
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FTR_SECTION_ELSE
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	clrrdi	r6,r8,40	/* get its 1T ESID */
	clrrdi	r9,r1,40	/* get current sp 1T ESID */
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
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	clrldi.	r0,r6,2		/* is new ESID c00000000? */
	cmpd	cr1,r6,r9	/* or is new ESID the same as current ESID? */
	cror	eq,4*cr1+eq,eq
	beq	2f		/* if yes, don't slbie it */

	/* Bolt in the new stack SLB entry */
	ld	r7,KSP_VSID(r4)	/* Get new stack's VSID */
	oris	r0,r6,(SLB_ESID_V)@h
	ori	r0,r0,(SLB_NUM_BOLTED-1)@l
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BEGIN_FTR_SECTION
	li	r9,MMU_SEGSIZE_1T	/* insert B field */
	oris	r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
	rldimi	r7,r9,SLB_VSID_SSIZE_SHIFT,0
504
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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	/* Update the last bolted SLB.  No write barriers are needed
	 * here, provided we only update the current CPU's SLB shadow
	 * buffer.
	 */
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	ld	r9,PACA_SLBSHADOWPTR(r13)
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	li	r12,0
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	std	r12,SLBSHADOW_STACKESID(r9)	/* Clear ESID */
	li	r12,SLBSHADOW_STACKVSID
	STDX_BE	r7,r12,r9			/* Save VSID */
	li	r12,SLBSHADOW_STACKESID
	STDX_BE	r0,r12,r9			/* Save ESID */
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518
	/* No need to check for MMU_FTR_NO_SLBIE_B here, since when
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	 * we have 1TB segments, the only CPUs known to have the errata
	 * only support less than 1TB of system memory and we'll never
	 * actually hit this code path.
	 */

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	slbie	r6
	slbie	r6		/* Workaround POWER5 < DD2.1 issue */
	slbmte	r7,r0
	isync
2:
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#endif /* !CONFIG_PPC_BOOK3S */

531
	CURRENT_THREAD_INFO(r7, r8)  /* base of new stack */
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	/* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
	   because we don't need to leave the 288-byte ABI gap at the
	   top of the kernel stack. */
	addi	r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE

	mr	r1,r8		/* start using new stack pointer */
	std	r7,PACAKSAVE(r13)

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#ifdef CONFIG_PPC_BOOK3S_64
BEGIN_FTR_SECTION
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	/* Event based branch registers */
	ld	r0, THREAD_BESCR(r4)
	mtspr	SPRN_BESCR, r0
	ld	r0, THREAD_EBBHR(r4)
	mtspr	SPRN_EBBHR, r0
	ld	r0, THREAD_EBBRR(r4)
	mtspr	SPRN_EBBRR, r0

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	ld	r0,THREAD_TAR(r4)
	mtspr	SPRN_TAR,r0
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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#endif

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#ifdef CONFIG_ALTIVEC
BEGIN_FTR_SECTION
	ld	r0,THREAD_VRSAVE(r4)
	mtspr	SPRN_VRSAVE,r0		/* if G4, restore VRSAVE reg */
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
#endif /* CONFIG_ALTIVEC */
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#ifdef CONFIG_PPC64
BEGIN_FTR_SECTION
563
	lwz	r6,THREAD_DSCR_INHERIT(r4)
564
	ld	r0,THREAD_DSCR(r4)
565 566
	cmpwi	r6,0
	bne	1f
567
	ld	r0,PACA_DSCR(r13)
568
1:
569 570 571 572 573 574
BEGIN_FTR_SECTION_NESTED(70)
	mfspr	r8, SPRN_FSCR
	rldimi	r8, r6, FSCR_DSCR_LG, (63 - FSCR_DSCR_LG)
	mtspr	SPRN_FSCR, r8
END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
	cmpd	r0,r25
575
	beq	2f
576
	mtspr	SPRN_DSCR,r0
577
2:
578 579
END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
#endif
580

581 582 583
	ld	r6,_CCR(r1)
	mtcrf	0xFF,r6

584 585 586 587 588 589 590 591 592 593 594 595 596 597 598
	/* r3-r13 are destroyed -- Cort */
	REST_8GPRS(14, r1)
	REST_10GPRS(22, r1)

	/* convert old thread to its task_struct for return value */
	addi	r3,r3,-THREAD
	ld	r7,_NIP(r1)	/* Return to _switch caller in new task */
	mtlr	r7
	addi	r1,r1,SWITCH_FRAME_SIZE
	blr

	.align	7
_GLOBAL(ret_from_except)
	ld	r11,_TRAP(r1)
	andi.	r0,r11,1
599
	bne	ret_from_except_lite
600 601 602 603 604 605 606 607
	REST_NVGPRS(r1)

_GLOBAL(ret_from_except_lite)
	/*
	 * Disable interrupts so that current_thread_info()->flags
	 * can't change between when we test it and when we return
	 * from the interrupt.
	 */
608 609 610
#ifdef CONFIG_PPC_BOOK3E
	wrteei	0
#else
611 612
	ld	r10,PACAKMSR(r13) /* Get kernel MSR without EE */
	mtmsrd	r10,1		  /* Update machine state */
613
#endif /* CONFIG_PPC_BOOK3E */
614

615
	CURRENT_THREAD_INFO(r9, r1)
616
	ld	r3,_MSR(r1)
617 618 619
#ifdef CONFIG_PPC_BOOK3E
	ld	r10,PACACURRENT(r13)
#endif /* CONFIG_PPC_BOOK3E */
620 621
	ld	r4,TI_FLAGS(r9)
	andi.	r3,r3,MSR_PR
622
	beq	resume_kernel
623 624 625
#ifdef CONFIG_PPC_BOOK3E
	lwz	r3,(THREAD+THREAD_DBCR0)(r10)
#endif /* CONFIG_PPC_BOOK3E */
626 627

	/* Check current_thread_info()->flags */
628
	andi.	r0,r4,_TIF_USER_WORK_MASK
629 630 631 632 633 634 635
#ifdef CONFIG_PPC_BOOK3E
	bne	1f
	/*
	 * Check to see if the dbcr0 register is set up to debug.
	 * Use the internal debug mode bit to do this.
	 */
	andis.	r0,r3,DBCR0_IDM@h
636
	beq	restore
637 638 639 640 641 642 643 644 645 646 647 648
	mfmsr	r0
	rlwinm	r0,r0,0,~MSR_DE	/* Clear MSR.DE */
	mtmsr	r0
	mtspr	SPRN_DBCR0,r3
	li	r10, -1
	mtspr	SPRN_DBSR,r10
	b	restore
#else
	beq	restore
#endif
1:	andi.	r0,r4,_TIF_NEED_RESCHED
	beq	2f
649
	bl	restore_interrupts
650
	SCHEDULE_USER
651
	b	ret_from_except_lite
652 653 654 655 656
2:
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	andi.	r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM
	bne	3f		/* only restore TM if nothing else to do */
	addi	r3,r1,STACK_FRAME_OVERHEAD
657
	bl	restore_tm_state
658 659 660
	b	restore
3:
#endif
661 662
	bl	save_nvgprs
	bl	restore_interrupts
663
	addi	r3,r1,STACK_FRAME_OVERHEAD
664 665
	bl	do_notify_resume
	b	ret_from_except
666 667

resume_kernel:
668
	/* check current_thread_info, _TIF_EMULATE_STACK_STORE */
669
	andis.	r8,r4,_TIF_EMULATE_STACK_STORE@h
670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694
	beq+	1f

	addi	r8,r1,INT_FRAME_SIZE	/* Get the kprobed function entry */

	lwz	r3,GPR1(r1)
	subi	r3,r3,INT_FRAME_SIZE	/* dst: Allocate a trampoline exception frame */
	mr	r4,r1			/* src:  current exception frame */
	mr	r1,r3			/* Reroute the trampoline frame to r1 */

	/* Copy from the original to the trampoline. */
	li	r5,INT_FRAME_SIZE/8	/* size: INT_FRAME_SIZE */
	li	r6,0			/* start offset: 0 */
	mtctr	r5
2:	ldx	r0,r6,r4
	stdx	r0,r6,r3
	addi	r6,r6,8
	bdnz	2b

	/* Do real store operation to complete stwu */
	lwz	r5,GPR1(r1)
	std	r8,0(r5)

	/* Clear _TIF_EMULATE_STACK_STORE flag */
	lis	r11,_TIF_EMULATE_STACK_STORE@h
	addi	r5,r9,TI_FLAGS
695
0:	ldarx	r4,0,r5
696 697 698 699 700
	andc	r4,r4,r11
	stdcx.	r4,0,r5
	bne-	0b
1:

701 702 703 704 705 706 707 708 709 710 711 712 713 714
#ifdef CONFIG_PREEMPT
	/* Check if we need to preempt */
	andi.	r0,r4,_TIF_NEED_RESCHED
	beq+	restore
	/* Check that preempt_count() == 0 and interrupts are enabled */
	lwz	r8,TI_PREEMPT(r9)
	cmpwi	cr1,r8,0
	ld	r0,SOFTE(r1)
	cmpdi	r0,0
	crandc	eq,cr1*4+eq,eq
	bne	restore

	/*
	 * Here we are preempting the current task. We want to make
715
	 * sure we are soft-disabled first and reconcile irq state.
716
	 */
717
	RECONCILE_IRQ_STATE(r3,r4)
718
1:	bl	preempt_schedule_irq
719 720

	/* Re-test flags and eventually loop */
721
	CURRENT_THREAD_INFO(r9, r1)
722
	ld	r4,TI_FLAGS(r9)
723 724
	andi.	r0,r4,_TIF_NEED_RESCHED
	bne	1b
725 726 727 728 729 730 731 732 733 734 735 736 737

	/*
	 * arch_local_irq_restore() from preempt_schedule_irq above may
	 * enable hard interrupt but we really should disable interrupts
	 * when we return from the interrupt, and so that we don't get
	 * interrupted after loading SRR0/1.
	 */
#ifdef CONFIG_PPC_BOOK3E
	wrteei	0
#else
	ld	r10,PACAKMSR(r13) /* Get kernel MSR without EE */
	mtmsrd	r10,1		  /* Update machine state */
#endif /* CONFIG_PPC_BOOK3E */
738
#endif /* CONFIG_PREEMPT */
739

740 741
	.globl	fast_exc_return_irq
fast_exc_return_irq:
742
restore:
743
	/*
744 745
	 * This is the main kernel exit path. First we check if we
	 * are about to re-enable interrupts
746
	 */
747
	ld	r5,SOFTE(r1)
748
	lbz	r6,PACASOFTIRQEN(r13)
749 750
	cmpwi	cr0,r5,0
	beq	restore_irq_off
751

752 753 754
	/* We are enabling, were we already enabled ? Yes, just return */
	cmpwi	cr0,r6,1
	beq	cr0,do_restore
755

756
	/*
757 758 759 760 761 762 763
	 * We are about to soft-enable interrupts (we are hard disabled
	 * at this point). We check if there's anything that needs to
	 * be replayed first.
	 */
	lbz	r0,PACAIRQHAPPENED(r13)
	cmpwi	cr0,r0,0
	bne-	restore_check_irq_replay
764

765 766 767 768 769 770 771 772 773 774 775 776 777
	/*
	 * Get here when nothing happened while soft-disabled, just
	 * soft-enable and move-on. We will hard-enable as a side
	 * effect of rfi
	 */
restore_no_replay:
	TRACE_ENABLE_INTS
	li	r0,1
	stb	r0,PACASOFTIRQEN(r13);

	/*
	 * Final return path. BookE is handled in a different file
	 */
778
do_restore:
779
#ifdef CONFIG_PPC_BOOK3E
780
	b	exception_return_book3e
781
#else
782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801
	/*
	 * Clear the reservation. If we know the CPU tracks the address of
	 * the reservation then we can potentially save some cycles and use
	 * a larx. On POWER6 and POWER7 this is significantly faster.
	 */
BEGIN_FTR_SECTION
	stdcx.	r0,0,r1		/* to clear the reservation */
FTR_SECTION_ELSE
	ldarx	r4,0,r1
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)

	/*
	 * Some code path such as load_up_fpu or altivec return directly
	 * here. They run entirely hard disabled and do not alter the
	 * interrupt state. They also don't use lwarx/stwcx. and thus
	 * are known not to leave dangling reservations.
	 */
	.globl	fast_exception_return
fast_exception_return:
	ld	r3,_MSR(r1)
802 803 804 805 806 807 808 809 810
	ld	r4,_CTR(r1)
	ld	r0,_LINK(r1)
	mtctr	r4
	mtlr	r0
	ld	r4,_XER(r1)
	mtspr	SPRN_XER,r4

	REST_8GPRS(5, r1)

811 812 813
	andi.	r0,r3,MSR_RI
	beq-	unrecov_restore

814 815 816 817 818 819
	/* Load PPR from thread struct before we clear MSR:RI */
BEGIN_FTR_SECTION
	ld	r2,PACACURRENT(r13)
	ld	r2,TASKTHREADPPR(r2)
END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)

820 821 822 823 824
	/*
	 * Clear RI before restoring r13.  If we are returning to
	 * userspace and we take an exception after restoring r13,
	 * we end up corrupting the userspace r13 value.
	 */
825 826
	ld	r4,PACAKMSR(r13) /* Get kernel MSR without EE */
	andc	r4,r4,r0	 /* r0 contains MSR_RI here */
827
	mtmsrd	r4,1
828

829 830 831 832
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	/* TM debug */
	std	r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
#endif
833 834
	/*
	 * r13 is our per cpu area, only restore it if we are returning to
835 836
	 * userspace the value stored in the stack frame may belong to
	 * another CPU.
837
	 */
838
	andi.	r0,r3,MSR_PR
839
	beq	1f
840 841 842
BEGIN_FTR_SECTION
	mtspr	SPRN_PPR,r2	/* Restore PPR */
END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
843
	ACCOUNT_CPU_USER_EXIT(r2, r4)
844 845
	REST_GPR(13, r1)
1:
846
	mtspr	SPRN_SRR1,r3
847 848 849 850 851 852 853 854 855 856 857 858 859 860 861

	ld	r2,_CCR(r1)
	mtcrf	0xFF,r2
	ld	r2,_NIP(r1)
	mtspr	SPRN_SRR0,r2

	ld	r0,GPR0(r1)
	ld	r2,GPR2(r1)
	ld	r3,GPR3(r1)
	ld	r4,GPR4(r1)
	ld	r1,GPR1(r1)

	rfid
	b	.	/* prevent speculative execution */

862 863
#endif /* CONFIG_PPC_BOOK3E */

864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882
	/*
	 * We are returning to a context with interrupts soft disabled.
	 *
	 * However, we may also about to hard enable, so we need to
	 * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
	 * or that bit can get out of sync and bad things will happen
	 */
restore_irq_off:
	ld	r3,_MSR(r1)
	lbz	r7,PACAIRQHAPPENED(r13)
	andi.	r0,r3,MSR_EE
	beq	1f
	rlwinm	r7,r7,0,~PACA_IRQ_HARD_DIS
	stb	r7,PACAIRQHAPPENED(r13)
1:	li	r0,0
	stb	r0,PACASOFTIRQEN(r13);
	TRACE_DISABLE_INTS
	b	do_restore

883 884 885 886 887 888 889 890 891 892 893 894
	/*
	 * Something did happen, check if a re-emit is needed
	 * (this also clears paca->irq_happened)
	 */
restore_check_irq_replay:
	/* XXX: We could implement a fast path here where we check
	 * for irq_happened being just 0x01, in which case we can
	 * clear it and return. That means that we would potentially
	 * miss a decrementer having wrapped all the way around.
	 *
	 * Still, this might be useful for things like hash_page
	 */
895
	bl	__check_irq_replay
896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915
	cmpwi	cr0,r3,0
 	beq	restore_no_replay
 
	/*
	 * We need to re-emit an interrupt. We do so by re-using our
	 * existing exception frame. We first change the trap value,
	 * but we need to ensure we preserve the low nibble of it
	 */
	ld	r4,_TRAP(r1)
	clrldi	r4,r4,60
	or	r4,r4,r3
	std	r4,_TRAP(r1)

	/*
	 * Then find the right handler and call it. Interrupts are
	 * still soft-disabled and we keep them that way.
	*/
	cmpwi	cr0,r3,0x500
	bne	1f
	addi	r3,r1,STACK_FRAME_OVERHEAD;
916 917
 	bl	do_IRQ
	b	ret_from_except
918 919 920
1:	cmpwi	cr0,r3,0x900
	bne	1f
	addi	r3,r1,STACK_FRAME_OVERHEAD;
921 922
	bl	timer_interrupt
	b	ret_from_except
923 924
#ifdef CONFIG_PPC_DOORBELL
1:
925
#ifdef CONFIG_PPC_BOOK3E
926 927 928 929 930 931 932 933
	cmpwi	cr0,r3,0x280
#else
	BEGIN_FTR_SECTION
		cmpwi	cr0,r3,0xe80
	FTR_SECTION_ELSE
		cmpwi	cr0,r3,0xa00
	ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
#endif /* CONFIG_PPC_BOOK3E */
934 935
	bne	1f
	addi	r3,r1,STACK_FRAME_OVERHEAD;
936 937
	bl	doorbell_exception
	b	ret_from_except
938
#endif /* CONFIG_PPC_DOORBELL */
939
1:	b	ret_from_except /* What else to do here ? */
940
 
941 942
unrecov_restore:
	addi	r3,r1,STACK_FRAME_OVERHEAD
943
	bl	unrecoverable_exception
944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979
	b	unrecov_restore

#ifdef CONFIG_PPC_RTAS
/*
 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
 * called with the MMU off.
 *
 * In addition, we need to be in 32b mode, at least for now.
 * 
 * Note: r3 is an input parameter to rtas, so don't trash it...
 */
_GLOBAL(enter_rtas)
	mflr	r0
	std	r0,16(r1)
        stdu	r1,-RTAS_FRAME_SIZE(r1)	/* Save SP and create stack space. */

	/* Because RTAS is running in 32b mode, it clobbers the high order half
	 * of all registers that it saves.  We therefore save those registers
	 * RTAS might touch to the stack.  (r0, r3-r13 are caller saved)
   	 */
	SAVE_GPR(2, r1)			/* Save the TOC */
	SAVE_GPR(13, r1)		/* Save paca */
	SAVE_8GPRS(14, r1)		/* Save the non-volatiles */
	SAVE_10GPRS(22, r1)		/* ditto */

	mfcr	r4
	std	r4,_CCR(r1)
	mfctr	r5
	std	r5,_CTR(r1)
	mfspr	r6,SPRN_XER
	std	r6,_XER(r1)
	mfdar	r7
	std	r7,_DAR(r1)
	mfdsisr	r8
	std	r8,_DSISR(r1)

980 981 982 983 984 985
	/* Temporary workaround to clear CR until RTAS can be modified to
	 * ignore all bits.
	 */
	li	r0,0
	mtcr	r0

986
#ifdef CONFIG_BUG	
987 988 989
	/* There is no way it is acceptable to get here with interrupts enabled,
	 * check it with the asm equivalent of WARN_ON
	 */
990
	lbz	r0,PACASOFTIRQEN(r13)
991
1:	tdnei	r0,0
992 993 994
	EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
#endif
	
995 996 997 998 999 1000
	/* Hard-disable interrupts */
	mfmsr	r6
	rldicl	r7,r6,48,1
	rotldi	r7,r7,16
	mtmsrd	r7,1

1001 1002 1003 1004 1005 1006 1007 1008
	/* Unfortunately, the stack pointer and the MSR are also clobbered,
	 * so they are saved in the PACA which allows us to restore
	 * our original state after RTAS returns.
         */
	std	r1,PACAR1(r13)
        std	r6,PACASAVEDMSR(r13)

	/* Setup our real return addr */	
1009
	LOAD_REG_ADDR(r4,rtas_return_loc)
1010
	clrldi	r4,r4,2			/* convert to realmode address */
1011 1012 1013 1014 1015 1016 1017 1018
       	mtlr	r4

	li	r0,0
	ori	r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
	andc	r0,r6,r0
	
        li      r9,1
        rldicr  r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
1019
	ori	r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
1020 1021 1022 1023
	andc	r6,r0,r9
	sync				/* disable interrupts so SRR0/1 */
	mtmsrd	r0			/* don't get trashed */

1024
	LOAD_REG_ADDR(r4, rtas)
1025 1026 1027 1028 1029 1030 1031 1032
	ld	r5,RTASENTRY(r4)	/* get the rtas->entry value */
	ld	r4,RTASBASE(r4)		/* get the rtas->base value */
	
	mtspr	SPRN_SRR0,r5
	mtspr	SPRN_SRR1,r6
	rfid
	b	.	/* prevent speculative execution */

1033
rtas_return_loc:
1034 1035
	FIXUP_ENDIAN

1036
	/* relocation is off at this point */
1037
	GET_PACA(r4)
1038
	clrldi	r4,r4,2			/* convert to realmode address */
1039

1040 1041
	bcl	20,31,$+4
0:	mflr	r3
1042
	ld	r3,(1f-0b)(r3)		/* get &rtas_restore_regs */
1043

1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057
	mfmsr   r6
	li	r0,MSR_RI
	andc	r6,r6,r0
	sync	
	mtmsrd  r6
        
        ld	r1,PACAR1(r4)           /* Restore our SP */
        ld	r4,PACASAVEDMSR(r4)     /* Restore our MSR */

	mtspr	SPRN_SRR0,r3
	mtspr	SPRN_SRR1,r4
	rfid
	b	.	/* prevent speculative execution */

1058
	.align	3
1059
1:	.llong	rtas_restore_regs
1060

1061
rtas_restore_regs:
1062 1063 1064 1065 1066 1067
	/* relocation is on at this point */
	REST_GPR(2, r1)			/* Restore the TOC */
	REST_GPR(13, r1)		/* Restore paca */
	REST_8GPRS(14, r1)		/* Restore the non-volatiles */
	REST_10GPRS(22, r1)		/* ditto */

1068
	GET_PACA(r13)
1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097

	ld	r4,_CCR(r1)
	mtcr	r4
	ld	r5,_CTR(r1)
	mtctr	r5
	ld	r6,_XER(r1)
	mtspr	SPRN_XER,r6
	ld	r7,_DAR(r1)
	mtdar	r7
	ld	r8,_DSISR(r1)
	mtdsisr	r8

        addi	r1,r1,RTAS_FRAME_SIZE	/* Unstack our frame */
	ld	r0,16(r1)		/* get return address */

	mtlr    r0
        blr				/* return to caller */

#endif /* CONFIG_PPC_RTAS */

_GLOBAL(enter_prom)
	mflr	r0
	std	r0,16(r1)
        stdu	r1,-PROM_FRAME_SIZE(r1)	/* Save SP and create stack space */

	/* Because PROM is running in 32b mode, it clobbers the high order half
	 * of all registers that it saves.  We therefore save those registers
	 * PROM might touch to the stack.  (r0, r3-r13 are caller saved)
   	 */
1098
	SAVE_GPR(2, r1)
1099 1100 1101
	SAVE_GPR(13, r1)
	SAVE_8GPRS(14, r1)
	SAVE_10GPRS(22, r1)
1102
	mfcr	r10
1103
	mfmsr	r11
1104
	std	r10,_CCR(r1)
1105 1106
	std	r11,_MSR(r1)

1107 1108 1109 1110 1111 1112 1113 1114
	/* Put PROM address in SRR0 */
	mtsrr0	r4

	/* Setup our trampoline return addr in LR */
	bcl	20,31,$+4
0:	mflr	r4
	addi	r4,r4,(1f - 0b)
       	mtlr	r4
1115

1116
	/* Prepare a 32-bit mode big endian MSR
1117
	 */
1118 1119
#ifdef CONFIG_PPC_BOOK3E
	rlwinm	r11,r11,0,1,31
1120 1121
	mtsrr1	r11
	rfi
1122
#else /* CONFIG_PPC_BOOK3E */
1123 1124 1125 1126
	LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
	andc	r11,r11,r12
	mtsrr1	r11
	rfid
1127
#endif /* CONFIG_PPC_BOOK3E */
1128

1129 1130
1:	/* Return from OF */
	FIXUP_ENDIAN
1131 1132 1133 1134 1135 1136 1137 1138

	/* Just make sure that r1 top 32 bits didn't get
	 * corrupt by OF
	 */
	rldicl	r1,r1,0,32

	/* Restore the MSR (back to 64 bits) */
	ld	r0,_MSR(r1)
1139
	MTMSRD(r0)
1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153
        isync

	/* Restore other registers */
	REST_GPR(2, r1)
	REST_GPR(13, r1)
	REST_8GPRS(14, r1)
	REST_10GPRS(22, r1)
	ld	r4,_CCR(r1)
	mtcr	r4
	
        addi	r1,r1,PROM_FRAME_SIZE
	ld	r0,16(r1)
	mtlr    r0
        blr
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1155
#ifdef CONFIG_FUNCTION_TRACER
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#ifdef CONFIG_DYNAMIC_FTRACE
_GLOBAL(mcount)
_GLOBAL(_mcount)
	blr

1161
_GLOBAL_TOC(ftrace_caller)
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	/* Taken from output of objdump from lib64/glibc */
	mflr	r3
	ld	r11, 0(r1)
	stdu	r1, -112(r1)
	std	r3, 128(r1)
	ld	r4, 16(r11)
1168
	subi	r3, r3, MCOUNT_INSN_SIZE
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.globl ftrace_call
ftrace_call:
	bl	ftrace_stub
	nop
1173 1174 1175 1176 1177 1178
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
.globl ftrace_graph_call
ftrace_graph_call:
	b	ftrace_graph_stub
_GLOBAL(ftrace_graph_stub)
#endif
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	ld	r0, 128(r1)
	mtlr	r0
	addi	r1, r1, 112
_GLOBAL(ftrace_stub)
	blr
#else
1185
_GLOBAL_TOC(_mcount)
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	/* Taken from output of objdump from lib64/glibc */
	mflr	r3
	ld	r11, 0(r1)
	stdu	r1, -112(r1)
	std	r3, 128(r1)
	ld	r4, 16(r11)

1193
	subi	r3, r3, MCOUNT_INSN_SIZE
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	LOAD_REG_ADDR(r5,ftrace_trace_function)
	ld	r5,0(r5)
	ld	r5,0(r5)
	mtctr	r5
	bctrl
	nop
1200 1201 1202 1203 1204


#ifdef CONFIG_FUNCTION_GRAPH_TRACER
	b	ftrace_graph_caller
#endif
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	ld	r0, 128(r1)
	mtlr	r0
	addi	r1, r1, 112
_GLOBAL(ftrace_stub)
	blr

1211 1212 1213
#endif /* CONFIG_DYNAMIC_FTRACE */

#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1214
_GLOBAL(ftrace_graph_caller)
1215 1216 1217 1218 1219 1220 1221 1222
	/* load r4 with local address */
	ld	r4, 128(r1)
	subi	r4, r4, MCOUNT_INSN_SIZE

	/* get the parent address */
	ld	r11, 112(r1)
	addi	r3, r11, 16

1223
	bl	prepare_ftrace_return
1224 1225 1226 1227 1228 1229 1230 1231
	nop

	ld	r0, 128(r1)
	mtlr	r0
	addi	r1, r1, 112
	blr

_GLOBAL(return_to_handler)
1232 1233 1234 1235 1236 1237 1238
	/* need to save return values */
	std	r4,  -24(r1)
	std	r3,  -16(r1)
	std	r31, -8(r1)
	mr	r31, r1
	stdu	r1, -112(r1)

1239
	bl	ftrace_return_to_handler
1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253
	nop

	/* return value has real return address */
	mtlr	r3

	ld	r1, 0(r1)
	ld	r4,  -24(r1)
	ld	r3,  -16(r1)
	ld	r31, -8(r1)

	/* Jump back to real return address */
	blr

_GLOBAL(mod_return_to_handler)
1254 1255 1256 1257 1258 1259 1260 1261 1262
	/* need to save return values */
	std	r4,  -32(r1)
	std	r3,  -24(r1)
	/* save TOC */
	std	r2,  -16(r1)
	std	r31, -8(r1)
	mr	r31, r1
	stdu	r1, -112(r1)

1263 1264 1265 1266
	/*
	 * We are in a module using the module's TOC.
	 * Switch to our TOC to run inside the core kernel.
	 */
1267
	ld	r2, PACATOC(r13)
1268

1269
	bl	ftrace_return_to_handler
1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
	nop

	/* return value has real return address */
	mtlr	r3

	ld	r1, 0(r1)
	ld	r4,  -32(r1)
	ld	r3,  -24(r1)
	ld	r2,  -16(r1)
	ld	r31, -8(r1)

	/* Jump back to real return address */
	blr
#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
#endif /* CONFIG_FUNCTION_TRACER */