sun4i-a10.dtsi 2.3 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
/*
 * Copyright 2012 Stefan Roese
 * Stefan Roese <sr@denx.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "sunxi.dtsi"

/ {
	memory {
		reg = <0x40000000 0x80000000>;
	};
19 20

	soc {
21
		pio: pinctrl@01c20800 {
22 23
			compatible = "allwinner,sun4i-a10-pinctrl";
			reg = <0x01c20800 0x400>;
24
			gpio-controller;
25 26
			#address-cells = <1>;
			#size-cells = <0>;
27
			#gpio-cells = <3>;
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart0_pins_b: uart0@1 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			uart1_pins_a: uart1@0 {
				allwinner,pins = "PA10", "PA11";
				allwinner,function = "uart1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
49
		};
50 51 52 53 54 55 56 57 58 59

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			status = "disabled";
		};
60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <17>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <18>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <19>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <20>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			status = "disabled";
		};
110
	};
111
};