malta-int.c 20.0 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
 * Copyright (C) 2001 Ralf Baechle
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Routines for generic manipulation of the interrupts found on the MIPS
 * Malta board.
 * The interrupt controller is located in the South Bridge a PIIX4 device
 * with two internal 82C95 interrupt controllers.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
27
#include <linux/smp.h>
L
Linus Torvalds 已提交
28 29
#include <linux/slab.h>
#include <linux/interrupt.h>
30
#include <linux/io.h>
L
Linus Torvalds 已提交
31
#include <linux/kernel_stat.h>
32
#include <linux/kernel.h>
L
Linus Torvalds 已提交
33 34
#include <linux/random.h>

35
#include <asm/traps.h>
L
Linus Torvalds 已提交
36
#include <asm/i8259.h>
37
#include <asm/irq_cpu.h>
38
#include <asm/irq_regs.h>
L
Linus Torvalds 已提交
39 40 41 42 43 44
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/mips-boards/piix4.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/msc01_pci.h>
45
#include <asm/msc01_ic.h>
46 47 48 49 50 51 52 53
#include <asm/gic.h>
#include <asm/gcmpregs.h>

int gcmp_present = -1;
int gic_present;
static unsigned long _msc01_biu_base;
static unsigned long _gcmp_base;
static unsigned int ipi_map[NR_CPUS];
L
Linus Torvalds 已提交
54 55 56 57 58 59

static DEFINE_SPINLOCK(mips_irq_lock);

static inline int mips_pcibios_iack(void)
{
	int irq;
60
	u32 dummy;
L
Linus Torvalds 已提交
61 62 63 64 65

	/*
	 * Determine highest priority pending interrupt by performing
	 * a PCI Interrupt Acknowledge cycle.
	 */
66 67 68 69 70
	switch (mips_revision_sconid) {
	case MIPS_REVISION_SCON_SOCIT:
	case MIPS_REVISION_SCON_ROCIT:
	case MIPS_REVISION_SCON_SOCITSC:
	case MIPS_REVISION_SCON_SOCITSCP:
71
		MSC_READ(MSC01_PCI_IACK, irq);
L
Linus Torvalds 已提交
72 73
		irq &= 0xff;
		break;
74
	case MIPS_REVISION_SCON_GT64120:
L
Linus Torvalds 已提交
75 76 77
		irq = GT_READ(GT_PCI0_IACK_OFS);
		irq &= 0xff;
		break;
78
	case MIPS_REVISION_SCON_BONITO:
L
Linus Torvalds 已提交
79 80 81 82 83 84 85 86 87 88 89
		/* The following will generate a PCI IACK cycle on the
		 * Bonito controller. It's a little bit kludgy, but it
		 * was the easiest way to implement it in hardware at
		 * the given time.
		 */
		BONITO_PCIMAP_CFG = 0x20000;

		/* Flush Bonito register block */
		dummy = BONITO_PCIMAP_CFG;
		iob();    /* sync */

90
		irq = readl((u32 *)_pcictrl_bonito_pcicfg);
L
Linus Torvalds 已提交
91 92 93 94 95
		iob();    /* sync */
		irq &= 0xff;
		BONITO_PCIMAP_CFG = 0;
		break;
	default:
96
		printk(KERN_WARNING "Unknown system controller.\n");
L
Linus Torvalds 已提交
97 98 99 100 101
		return -1;
	}
	return irq;
}

102
static inline int get_int(void)
L
Linus Torvalds 已提交
103 104
{
	unsigned long flags;
105
	int irq;
L
Linus Torvalds 已提交
106 107
	spin_lock_irqsave(&mips_irq_lock, flags);

108
	irq = mips_pcibios_iack();
L
Linus Torvalds 已提交
109 110

	/*
R
Ralf Baechle 已提交
111 112 113
	 * The only way we can decide if an interrupt is spurious
	 * is by checking the 8259 registers.  This needs a spinlock
	 * on an SMP system,  so leave it up to the generic code...
L
Linus Torvalds 已提交
114 115 116 117
	 */

	spin_unlock_irqrestore(&mips_irq_lock, flags);

118
	return irq;
L
Linus Torvalds 已提交
119 120
}

121
static void malta_hw0_irqdispatch(void)
L
Linus Torvalds 已提交
122 123 124
{
	int irq;

125
	irq = get_int();
126
	if (irq < 0) {
127 128
		/* interrupt has already been cleared */
		return;
129
	}
L
Linus Torvalds 已提交
130

131
	do_IRQ(MALTA_INT_BASE + irq);
L
Linus Torvalds 已提交
132 133
}

134 135 136 137 138 139 140 141 142 143 144
static void malta_ipi_irqdispatch(void)
{
	int irq;

	irq = gic_get_int();
	if (irq < 0)
		return;  /* interrupt has already been cleared */

	do_IRQ(MIPS_GIC_IRQ_BASE + irq);
}

145
static void corehi_irqdispatch(void)
L
Linus Torvalds 已提交
146
{
147
	unsigned int intedge, intsteer, pcicmd, pcibadaddr;
148
	unsigned int pcimstat, intisr, inten, intpol;
149
	unsigned int intrcause, datalo, datahi;
150
	struct pt_regs *regs = get_irq_regs();
L
Linus Torvalds 已提交
151

152 153
	printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
	printk(KERN_EMERG "epc   : %08lx\nStatus: %08lx\n"
154 155 156
			"Cause : %08lx\nbadVaddr : %08lx\n",
			regs->cp0_epc, regs->cp0_status,
			regs->cp0_cause, regs->cp0_badvaddr);
157 158 159 160 161 162

	/* Read all the registers and then print them as there is a
	   problem with interspersed printk's upsetting the Bonito controller.
	   Do it for the others too.
	*/

163
	switch (mips_revision_sconid) {
164
	case MIPS_REVISION_SCON_SOCIT:
165 166 167
	case MIPS_REVISION_SCON_ROCIT:
	case MIPS_REVISION_SCON_SOCITSC:
	case MIPS_REVISION_SCON_SOCITSCP:
168 169 170 171 172 173
		ll_msc_irq();
		break;
	case MIPS_REVISION_SCON_GT64120:
		intrcause = GT_READ(GT_INTRCAUSE_OFS);
		datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
		datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
174 175 176
		printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
		printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
				datahi, datalo);
177 178 179 180 181 182 183 184 185 186
		break;
	case MIPS_REVISION_SCON_BONITO:
		pcibadaddr = BONITO_PCIBADADDR;
		pcimstat = BONITO_PCIMSTAT;
		intisr = BONITO_INTISR;
		inten = BONITO_INTEN;
		intpol = BONITO_INTPOL;
		intedge = BONITO_INTEDGE;
		intsteer = BONITO_INTSTEER;
		pcicmd = BONITO_PCICMD;
187 188 189 190 191 192 193 194
		printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
		printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
		printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
		printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
		printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
		printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
		printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
		printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
195 196
		break;
	}
L
Linus Torvalds 已提交
197

198
	die("CoreHi interrupt", regs);
L
Linus Torvalds 已提交
199 200
}

201 202
static inline int clz(unsigned long x)
{
203
	__asm__(
204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
	"	.set	push					\n"
	"	.set	mips32					\n"
	"	clz	%0, %1					\n"
	"	.set	pop					\n"
	: "=r" (x)
	: "r" (x));

	return x;
}

/*
 * Version of ffs that only looks at bits 12..15.
 */
static inline unsigned int irq_ffs(unsigned int pending)
{
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
	return -clz(pending) + 31 - CAUSEB_IP;
#else
	unsigned int a0 = 7;
	unsigned int t0;

225
	t0 = pending & 0xf000;
226 227 228
	t0 = t0 < 1;
	t0 = t0 << 2;
	a0 = a0 - t0;
229
	pending = pending << t0;
230

231
	t0 = pending & 0xc000;
232 233 234
	t0 = t0 < 1;
	t0 = t0 << 1;
	a0 = a0 - t0;
235
	pending = pending << t0;
236

237
	t0 = pending & 0x8000;
238
	t0 = t0 < 1;
239
	/* t0 = t0 << 2; */
240
	a0 = a0 - t0;
241
	/* pending = pending << t0; */
242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271

	return a0;
#endif
}

/*
 * IRQs on the Malta board look basically (barring software IRQs which we
 * don't use at all and all external interrupt sources are combined together
 * on hardware interrupt 0 (MIPS IRQ 2)) like:
 *
 *	MIPS IRQ	Source
 *      --------        ------
 *             0	Software (ignored)
 *             1        Software (ignored)
 *             2        Combined hardware interrupt (hw0)
 *             3        Hardware (ignored)
 *             4        Hardware (ignored)
 *             5        Hardware (ignored)
 *             6        Hardware (ignored)
 *             7        R4k timer (what we use)
 *
 * We handle the IRQ according to _our_ priority which is:
 *
 * Highest ----     R4k Timer
 * Lowest  ----     Combined hardware interrupt
 *
 * then we just return, if multiple IRQs are pending then we will just take
 * another exception, big deal.
 */

272
asmlinkage void plat_irq_dispatch(void)
273 274 275 276 277 278 279
{
	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
	int irq;

	irq = irq_ffs(pending);

	if (irq == MIPSCPU_INT_I8259A)
280
		malta_hw0_irqdispatch();
281 282
	else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
		malta_ipi_irqdispatch();
283
	else if (irq >= 0)
284
		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
285
	else
286
		spurious_interrupt();
287 288
}

289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333
#ifdef CONFIG_MIPS_MT_SMP


#define GIC_MIPS_CPU_IPI_RESCHED_IRQ	3
#define GIC_MIPS_CPU_IPI_CALL_IRQ	4

#define MIPS_CPU_IPI_RESCHED_IRQ 0	/* SW int 0 for resched */
#define C_RESCHED C_SW0
#define MIPS_CPU_IPI_CALL_IRQ 1		/* SW int 1 for resched */
#define C_CALL C_SW1
static int cpu_ipi_resched_irq, cpu_ipi_call_irq;

static void ipi_resched_dispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
}

static void ipi_call_dispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
}

static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
	return IRQ_HANDLED;
}

static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
	smp_call_function_interrupt();

	return IRQ_HANDLED;
}

static struct irqaction irq_resched = {
	.handler	= ipi_resched_interrupt,
	.flags		= IRQF_DISABLED|IRQF_PERCPU,
	.name		= "IPI_resched"
};

static struct irqaction irq_call = {
	.handler	= ipi_call_interrupt,
	.flags		= IRQF_DISABLED|IRQF_PERCPU,
	.name		= "IPI_call"
};
334 335 336 337 338

static int gic_resched_int_base;
static int gic_call_int_base;
#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
T
Tim Anderson 已提交
339 340 341 342 343 344 345 346 347 348

unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
{
	return GIC_CALL_INT(cpu);
}

unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
{
	return GIC_RESCHED_INT(cpu);
}
349 350
#endif /* CONFIG_MIPS_MT_SMP */

351 352 353 354 355 356 357 358 359 360
static struct irqaction i8259irq = {
	.handler = no_action,
	.name = "XT-PIC cascade"
};

static struct irqaction corehi_irqaction = {
	.handler = no_action,
	.name = "CoreHi"
};

361
static msc_irqmap_t __initdata msc_irqmap[] = {
362 363 364
	{MSC01C_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01C_INT_PCI,		MSC01_IRQ_LEVEL, 0},
};
365
static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
366

367
static msc_irqmap_t __initdata msc_eicirqmap[] = {
368 369 370 371 372 373 374 375 376 377 378
	{MSC01E_INT_SW0,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SW1,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_I8259A,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SMI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_COREHI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CORELO,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01E_INT_PCI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_PERFCTR,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CPUCTR,		MSC01_IRQ_LEVEL, 0}
};
379

380
static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
381

382
#if defined(CONFIG_MIPS_MT_SMP)
383 384 385 386 387
/*
 * This GIC specific tabular array defines the association between External
 * Interrupts and CPUs/Core Interrupts. The nature of the External
 * Interrupts is also defined here - polarity/trigger.
 */
388
static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404
	{ GIC_EXT_INTR(0), 	X,	X,		X, 		X,		0 },
	{ GIC_EXT_INTR(1), 	X,	X,		X, 		X,		0 },
	{ GIC_EXT_INTR(2), 	X,	X,		X, 		X,		0 },
	{ GIC_EXT_INTR(3), 	0,	GIC_CPU_INT0,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(4), 	0,	GIC_CPU_INT1,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(5), 	0,	GIC_CPU_INT2,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(6), 	0,	GIC_CPU_INT3,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(7), 	0,	GIC_CPU_INT4,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(8), 	0,	GIC_CPU_INT3,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(9), 	0,	GIC_CPU_INT3,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(10), 	X,	X,		X, 		X,		0 },
	{ GIC_EXT_INTR(11), 	X,	X,		X, 		X,		0 },
	{ GIC_EXT_INTR(12), 	0,	GIC_CPU_INT3,	GIC_POL_POS, 	GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(13), 	0,	GIC_MAP_TO_NMI_MSK,	GIC_POL_POS, GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(14), 	0,	GIC_MAP_TO_NMI_MSK,	GIC_POL_POS, GIC_TRIG_LEVEL,	0 },
	{ GIC_EXT_INTR(15), 	X,	X,		X, 		X,		0 },
405
/* This is the end of the general interrupts now we do IPI ones */
406
};
407
#endif
408 409 410 411

/*
 * GCMP needs to be detected before any SMP initialisation
 */
412
static int __init gcmp_probe(unsigned long addr, unsigned long size)
413 414 415 416 417 418 419 420 421 422 423 424 425
{
	if (gcmp_present >= 0)
		return gcmp_present;

	_gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
	_msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
	gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;

	if (gcmp_present)
		printk(KERN_DEBUG "GCMP present\n");
	return gcmp_present;
}

426
#if defined(CONFIG_MIPS_MT_SMP)
427 428 429 430 431 432 433 434 435 436 437 438
static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
{
	int intr = baseintr + cpu;
	gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr);
	gic_intr_map[intr].cpunum = cpu;
	gic_intr_map[intr].pin = cpupin;
	gic_intr_map[intr].polarity = GIC_POL_POS;
	gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
	gic_intr_map[intr].ipiflag = 1;
	ipi_map[cpu] |= (1 << (cpupin + 2));
}

439
static void __init fill_ipi_map(void)
440
{
441
	int cpu;
442

443 444 445
	for (cpu = 0; cpu < NR_CPUS; cpu++) {
		fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
		fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
446 447
	}
}
448
#endif
449

L
Linus Torvalds 已提交
450 451
void __init arch_init_irq(void)
{
452 453
	int gic_present, gcmp_present;

L
Linus Torvalds 已提交
454
	init_i8259_irqs();
455 456

	if (!cpu_has_veic)
457
		mips_cpu_irq_init();
458

459 460 461 462 463 464 465 466 467 468 469 470
	gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
	if (gcmp_present)  {
		GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
		gic_present = 1;
	} else {
		_msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
		gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
		MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF;
	}
	if (gic_present)
		printk(KERN_DEBUG "GIC present\n");

471 472 473
	switch (mips_revision_sconid) {
	case MIPS_REVISION_SCON_SOCIT:
	case MIPS_REVISION_SCON_ROCIT:
474
		if (cpu_has_veic)
475 476 477
			init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
					MSC01E_INT_BASE, msc_eicirqmap,
					msc_nr_eicirqs);
478
		else
479 480 481
			init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
					MSC01C_INT_BASE, msc_irqmap,
					msc_nr_irqs);
482 483
		break;

484 485
	case MIPS_REVISION_SCON_SOCITSC:
	case MIPS_REVISION_SCON_SOCITSCP:
486
		if (cpu_has_veic)
487 488 489
			init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
					MSC01E_INT_BASE, msc_eicirqmap,
					msc_nr_eicirqs);
490
		else
491 492 493
			init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
					MSC01C_INT_BASE, msc_irqmap,
					msc_nr_irqs);
494 495 496
	}

	if (cpu_has_veic) {
497 498 499 500
		set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
		setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
		setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
501
	} else if (cpu_has_vint) {
502 503
		set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
504
#ifdef CONFIG_MIPS_MT_SMTC
505
		setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
506
			(0x100 << MIPSCPU_INT_I8259A));
507
		setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
508
			&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
509 510 511 512 513 514 515 516 517 518 519 520
		/*
		 * Temporary hack to ensure that the subsidiary device
		 * interrupts coing in via the i8259A, but associated
		 * with low IRQ numbers, will restore the Status.IM
		 * value associated with the i8259A.
		 */
		{
			int i;

			for (i = 0; i < 16; i++)
				irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
		}
521
#else /* Not SMTC */
522
		setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
523 524
		setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
						&corehi_irqaction);
525
#endif /* CONFIG_MIPS_MT_SMTC */
526
	} else {
527
		setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
528 529
		setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
						&corehi_irqaction);
530
	}
531 532 533 534 535

#if defined(CONFIG_MIPS_MT_SMP)
	if (gic_present) {
		/* FIXME */
		int i;
536 537 538 539

		gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
		gic_resched_int_base = gic_call_int_base - NR_CPUS;

540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560
		fill_ipi_map();
		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
		if (!gcmp_present) {
			/* Enable the GIC */
			i = REG(_msc01_biu_base, MSC01_SC_CFG);
			REG(_msc01_biu_base, MSC01_SC_CFG) =
				(i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
			pr_debug("GIC Enabled\n");
		}

		/* set up ipi interrupts */
		if (cpu_has_vint) {
			set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
			set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
		}
		/* Argh.. this really needs sorting out.. */
		printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
		write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
		printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
		write_c0_status(0x1100dc00);
		printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
561 562 563 564 565 566 567 568 569
		for (i = 0; i < NR_CPUS; i++) {
			setup_irq(MIPS_GIC_IRQ_BASE +
					GIC_RESCHED_INT(i), &irq_resched);
			setup_irq(MIPS_GIC_IRQ_BASE +
					GIC_CALL_INT(i), &irq_call);
			set_irq_handler(MIPS_GIC_IRQ_BASE +
					GIC_RESCHED_INT(i), handle_percpu_irq);
			set_irq_handler(MIPS_GIC_IRQ_BASE +
					GIC_CALL_INT(i), handle_percpu_irq);
570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720
		}
	} else {
		/* set up ipi interrupts */
		if (cpu_has_veic) {
			set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
			set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
			cpu_ipi_resched_irq = MSC01E_INT_SW0;
			cpu_ipi_call_irq = MSC01E_INT_SW1;
		} else {
			if (cpu_has_vint) {
				set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
				set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
			}
			cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
			cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
		}

		setup_irq(cpu_ipi_resched_irq, &irq_resched);
		setup_irq(cpu_ipi_call_irq, &irq_call);

		set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
		set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
	}
#endif
}

void malta_be_init(void)
{
	if (gcmp_present) {
		/* Could change CM error mask register */
	}
}


static char *tr[8] = {
	"mem",	"gcr",	"gic",	"mmio",
	"0x04",	"0x05",	"0x06",	"0x07"
};

static char *mcmd[32] = {
	[0x00] = "0x00",
	[0x01] = "Legacy Write",
	[0x02] = "Legacy Read",
	[0x03] = "0x03",
	[0x04] = "0x04",
	[0x05] = "0x05",
	[0x06] = "0x06",
	[0x07] = "0x07",
	[0x08] = "Coherent Read Own",
	[0x09] = "Coherent Read Share",
	[0x0a] = "Coherent Read Discard",
	[0x0b] = "Coherent Ready Share Always",
	[0x0c] = "Coherent Upgrade",
	[0x0d] = "Coherent Writeback",
	[0x0e] = "0x0e",
	[0x0f] = "0x0f",
	[0x10] = "Coherent Copyback",
	[0x11] = "Coherent Copyback Invalidate",
	[0x12] = "Coherent Invalidate",
	[0x13] = "Coherent Write Invalidate",
	[0x14] = "Coherent Completion Sync",
	[0x15] = "0x15",
	[0x16] = "0x16",
	[0x17] = "0x17",
	[0x18] = "0x18",
	[0x19] = "0x19",
	[0x1a] = "0x1a",
	[0x1b] = "0x1b",
	[0x1c] = "0x1c",
	[0x1d] = "0x1d",
	[0x1e] = "0x1e",
	[0x1f] = "0x1f"
};

static char *core[8] = {
	"Invalid/OK", 	"Invalid/Data",
	"Shared/OK",	"Shared/Data",
	"Modified/OK",	"Modified/Data",
	"Exclusive/OK",	"Exclusive/Data"
};

static char *causes[32] = {
	"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
	"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
	"0x08", "0x09", "0x0a", "0x0b",
	"0x0c", "0x0d", "0x0e", "0x0f",
	"0x10", "0x11", "0x12", "0x13",
	"0x14", "0x15", "0x16", "INTVN_WR_ERR",
	"INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
	"0x1c", "0x1d", "0x1e", "0x1f"
};

int malta_be_handler(struct pt_regs *regs, int is_fixup)
{
	/* This duplicates the handling in do_be which seems wrong */
	int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;

	if (gcmp_present) {
		unsigned long cm_error = GCMPGCB(GCMEC);
		unsigned long cm_addr = GCMPGCB(GCMEA);
		unsigned long cm_other = GCMPGCB(GCMEO);
		unsigned long cause, ocause;
		char buf[256];

		cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
		if (cause != 0) {
			cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
			if (cause < 16) {
				unsigned long cca_bits = (cm_error >> 15) & 7;
				unsigned long tr_bits = (cm_error >> 12) & 7;
				unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
				unsigned long stag_bits = (cm_error >> 3) & 15;
				unsigned long sport_bits = (cm_error >> 0) & 7;

				snprintf(buf, sizeof(buf),
					 "CCA=%lu TR=%s MCmd=%s STag=%lu "
					 "SPort=%lu\n",
					 cca_bits, tr[tr_bits], mcmd[mcmd_bits],
					 stag_bits, sport_bits);
			} else {
				/* glob state & sresp together */
				unsigned long c3_bits = (cm_error >> 18) & 7;
				unsigned long c2_bits = (cm_error >> 15) & 7;
				unsigned long c1_bits = (cm_error >> 12) & 7;
				unsigned long c0_bits = (cm_error >> 9) & 7;
				unsigned long sc_bit = (cm_error >> 8) & 1;
				unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
				unsigned long sport_bits = (cm_error >> 0) & 7;
				snprintf(buf, sizeof(buf),
					 "C3=%s C2=%s C1=%s C0=%s SC=%s "
					 "MCmd=%s SPort=%lu\n",
					 core[c3_bits], core[c2_bits],
					 core[c1_bits], core[c0_bits],
					 sc_bit ? "True" : "False",
					 mcmd[mcmd_bits], sport_bits);
			}

			ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
				 GCMP_GCB_GMEO_ERROR_2ND_SHF;

			printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
			       causes[cause], buf);
			printk("CM_ADDR =%08lx\n", cm_addr);
			printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);

			/* reprime cause register */
			GCMPGCB(GCMEC) = 0;
		}
	}

	return retval;
L
Linus Torvalds 已提交
721
}