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  1. 17 12月, 2015 2 次提交
    • A
      target-i386/kvm: Hyper-V SynIC timers MSR's support · ff99aa64
      由 Andrey Smetanin 提交于 
      Hyper-V SynIC timers are host timers that are configurable
by guest through corresponding MSR's (HV_X64_MSR_STIMER*).
Guest setup and use fired by host events(SynIC interrupt
and appropriate timer expiration message) as guest clock
events.

The state of Hyper-V SynIC timers are stored in corresponding
MSR's. This patch seria implements such MSR's support and migration.
Signed-off-by: NAndrey Smetanin <asmetanin@virtuozzo.com>
CC: Paolo Bonzini <pbonzini@redhat.com>
CC: Richard Henderson <rth@twiddle.net>
CC: Eduardo Habkost <ehabkost@redhat.com>
CC: "Andreas Färber" <afaerber@suse.de>
CC: Marcelo Tosatti <mtosatti@redhat.com>
CC: Denis V. Lunev <den@openvz.org>
CC: Roman Kagan <rkagan@virtuozzo.com>
CC: kvm@vger.kernel.org

Message-Id: <1448464885-8300-3-git-send-email-asmetanin@virtuozzo.com>
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      ff99aa64
    • A
      target-i386/kvm: Hyper-V SynIC MSR's support · 866eea9a
      由 Andrey Smetanin 提交于 
      This patch does Hyper-V Synthetic interrupt
controller(Hyper-V SynIC) MSR's support and
migration. Hyper-V SynIC is enabled by cpu's
'hv-synic' option.

This patch does not allow cpu creation if
'hv-synic' option specified but kernel
doesn't support Hyper-V SynIC.

Changes v3:
* removed 'msr_hv_synic_version' migration because
it's value always the same
* moved SynIC msr's initialization into kvm_arch_init_vcpu
Signed-off-by: NAndrey Smetanin <asmetanin@virtuozzo.com>
Reviewed-by: NRoman Kagan <rkagan@virtuozzo.com>
Signed-off-by: NDenis V. Lunev <den@openvz.org>
CC: Paolo Bonzini <pbonzini@redhat.com>
CC: Richard Henderson <rth@twiddle.net>
CC: Eduardo Habkost <ehabkost@redhat.com>
CC: "Andreas Färber" <afaerber@suse.de>
CC: Marcelo Tosatti <mtosatti@redhat.com>
CC: Roman Kagan <rkagan@virtuozzo.com>
CC: Denis V. Lunev <den@openvz.org>
CC: kvm@vger.kernel.org
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      866eea9a
  3. 23 10月, 2015 1 次提交
  5. 13 10月, 2015 1 次提交
  7. 16 9月, 2015 1 次提交
  9. 12 6月, 2015 1 次提交
    • J
      migration: Use normal VMStateDescriptions for Subsections · 5cd8cada
      由 Juan Quintela 提交于 
      We create optional sections with this patch.  But we already have
optional subsections.  Instead of having two mechanism that do the
same, we can just generalize it.

For subsections we just change:

- Add a needed function to VMStateDescription
- Remove VMStateSubsection (after removal of the needed function
  it is just a VMStateDescription)
- Adjust the whole tree, moving the needed function to the corresponding
  VMStateDescription
Signed-off-by: NJuan Quintela <quintela@redhat.com>
      5cd8cada
  11. 05 6月, 2015 1 次提交
  13. 26 1月, 2015 2 次提交
    • P
      target-i386: make xmm_regs 512-bit wide · b7711471
      由 Paolo Bonzini 提交于 
      Right now, the AVX512 registers are split in many different fields:
xmm_regs for the low 128 bits of the first 16 registers, ymmh_regs
for the next 128 bits of the same first 16 registers, zmmh_regs
for the next 256 bits of the same first 16 registers, and finally
hi16_zmm_regs for the full 512 bits of the second 16 bit registers.

This makes it simple to move data in and out of the xsave region,
but would be a nightmare for a hypothetical TCG implementation and
leads to a proliferation of [XYZ]MM_[BWLSQD] macros.  Instead,
this patch marshals data manually from the xsave region to a single
32x512-bit array, simplifying the macro jungle and clarifying which
bits are in which vmstate subsection.

The migration format is unaffected.
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      b7711471
    • P
      target-i386: use vmstate_offset_sub_array for AVX registers · a03c3e90
      由 Paolo Bonzini 提交于 
      After the next patch, each vmstate field will extract parts of a larger
(32x512-bit) array, so we cannot check the vmstate field against the
type of the array.

While changing this, change the macros to accept the index of the first
element (which will not be 0 for Hi16_ZMM_REGS) instead of the number
of elements (which is always CPU_NB_REGS).
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      a03c3e90
  15. 15 12月, 2014 1 次提交
  17. 25 10月, 2014 1 次提交
  19. 18 9月, 2014 1 次提交
  21. 26 8月, 2014 1 次提交
  23. 26 6月, 2014 1 次提交
  25. 16 6月, 2014 1 次提交
  27. 22 5月, 2014 1 次提交
    • P
      target-i386: get CPL from SS.DPL · 7125c937
      由 Paolo Bonzini 提交于 
      CS.RPL is not equal to the CPL in the few instructions between
setting CR0.PE and reloading CS.  We get this right in the common
case, because writes to CR0 do not modify the CPL, but it would
not be enough if an SMI comes exactly during that brief period.
Were this to happen, the RSM instruction would erroneously set
CPL to the low two bits of the real-mode selector; and if they are
not 00, the next instruction fetch cannot access the code segment
and causes a triple fault.

However, SS.DPL *is* always equal to the CPL.  In real processors
(AMD only) there is a weird case of SYSRET setting SS.DPL=SS.RPL
from the STAR register while forcing CPL=3, but we do not emulate
that.
Tested-by: NKevin O'Connor <kevin@koconnor.net>
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      7125c937
  29. 05 4月, 2014 1 次提交
  31. 14 3月, 2014 3 次提交
  33. 04 2月, 2014 3 次提交
  35. 12 12月, 2013 1 次提交
  37. 20 9月, 2013 1 次提交
  39. 10 8月, 2013 1 次提交
  41. 25 7月, 2013 1 次提交
  43. 23 7月, 2013 2 次提交
  45. 18 4月, 2013 1 次提交
  47. 09 4月, 2013 1 次提交
    • P
      hw: move headers to include/ · 0d09e41a
      由 Paolo Bonzini 提交于 
      Many of these should be cleaned up with proper qdev-/QOM-ification.
Right now there are many catch-all headers in include/hw/ARCH depending
on cpu.h, and this makes it necessary to compile these files per-target.
However, fixing this does not belong in these patches.
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      0d09e41a
  49. 12 3月, 2013 2 次提交
  51. 15 1月, 2013 1 次提交
  53. 19 12月, 2012 1 次提交
  55. 15 12月, 2012 1 次提交
    • W
      target-i386: Enabling IA32_TSC_ADJUST for QEMU KVM guest VMs · f28558d3
      由 Will Auld 提交于 
      CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported

Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR whether through rdmsr or rdtsc.

As this is a new MSR that the guest may access and modify its value needs
to be migrated along with the other MRSs. The changes here are specifically
for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added
for migrating its value.
Signed-off-by: NWill Auld <will.auld@intel.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>
      f28558d3
  57. 29 8月, 2012 1 次提交
  59. 15 3月, 2012 1 次提交
  61. 25 10月, 2011 2 次提交