Modern linux supports arbitrary header size,
which makes it possible to pass mrg buf header
to tap directly without iovec mangling.
Use this capability when it is there.

This removes the need to deal with it in
vhost-net as we do now.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

There's no reason to query header support at random
times: at load or feature query.
Driver also might not query functions.
Cleaner to do it at device init.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

During packet filtering, we can now use host hdr len
to offset incoming buffer unconditionally.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Remove code duplication using guest header length that we track.
Drop specific layout requirement for rx buffers: things work
using generic iovec functions in any case.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Avoid mangling iovec manually: use safe iov_*
functions.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

We know offset is 0, assert that.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Now that we know host hdr length, we don't need to
duplicate the logic in receive_hdr: caller can
figure out the offset itself.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Avoid magling iov manually: use safe iov operations
for processing packets incoming to guest.
This also removes the requirement for virtio header to
fit the first s/g entry exactly.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Avoid tweaking iovec during receive. This removes
the need to copy the vector.
Note: we currently have an evil cast in work_around_broken_dhclient
and unfortunately this patch does not fix it - just
pushes the evil cast to another place.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Add API to copy part of iovec safely.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Tracking these in device state instead of
re-calculating on each packet. No functional
changes.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Let's use PCIExpressHost with QOM.
Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
Acked-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NJason Baron <jbaron@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

This allows q35 to pass/set the size of the pcie window in its update routine.
Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: NJason Baron <jbaron@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

[jbaron@redhat.com: add PCI_CLASS_SERIAL_SMBUS definition]
Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: NJason Baron <jbaron@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
standardized. PCI bridge swizzle is common logic, by introducing
this function duplicated swizzle logic will be avoided later.

[jbaron@redhat.com: drop opaque argument]
Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: NIsaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: NJason Baron <jbaron@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Adds pci id constants which will be used by q35.
Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: NIsaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: NJason Baron <jbaron@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

pci capability must be in PCI space.
It can't lay in PCIe extended config space.
Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: NIsaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: NJason Baron <jbaron@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

PCI spec (see e.g. 6.7 Capabilities List in spec rev 3.0)
requires that each capability is DWORD aligned.
Ensure this when allocating space by rounding size up to 4.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Enable KVM PV EOI by default. You can still disable it with
-kvm_pv_eoi cpu flag. To avoid breaking cross-version migration,
enable only for qemu 1.3 (or in the future, newer) machine type.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Rather than assert, simply return PCI_INTX_DISABLED when we don't
have a pci_route_irq_fn.  PIIX already returns DISABLED for an
invalid pin, so users already deal with this state.  Users of this
interface should only be acting on an ENABLED or INVERTED return
value (though we really have no support for INVERTED).  Also
complain loudly when we hit this so we don't forget it's missing.
Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
Acked-by: NJan Kiszka <jan.kiszka@siemens.com>

pci-assign only uses a subset of the flexibility msi_get_message()
provides, but it's still worthwhile to use it.
Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

vfio-pci and pci-assign both do this on their own for setting up
direct MSI injection through KVM.  Provide a helper function for
this in MSI code.
Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Replace open coded version
Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>

* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: (22 commits)
  PPC: pseries: Remove hack for PIO window
  PPC: e500: Map PIO space into core memory region
  xen_platform: convert PIO to new memory api read/write
  vmport: convert PIO to new memory api read/write
  serial: convert PIO to new memory api read/write
  rtl8139: convert PIO to new memory api read/write
  pckbd: convert PIO to new memory api read/write
  pc port92: convert PIO to new memory api read/write
  mc146818rtc: convert PIO to new memory api read/write
  m48t59: convert PIO to new memory api read/write
  i8254: convert PIO to new memory api read/write
  es1370: convert PIO to new memory api read/write
  virtio-pci: convert PIO to new memory api read/write
  ac97: convert PIO to new memory api read/write
  pseries: Implement qemu initiated shutdowns using EPOW events
  target-ppc: Rework storage of VPA registration state
  pseries: Don't allow duplicate registration of hcalls or RTAS calls
  Add USB option in machine options
  e500: Fix serial initialization
  PPC: 440: Emulate DCBR0
  ...

* 'queue/qmp' of git://repo.or.cz/qemu/qmp-unstable:
  migration: go to paused state after finishing incoming migration with -S
  qmp: handle stop/cont in INMIGRATE state
  hmp: fix info cpus for sparc targets

Now that all users of old_portio are gone, we can remove the hack
that enabled us to support them.
Signed-off-by: NAlexander Graf <agraf@suse.de>

On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is
accessible via MMIO. Do this mapping explicitly by mapping the PIO space
of our PCI bus into a memory region that lives in memory space.
Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NAlexander Graf <agraf@suse.de>