- 08 4月, 2010 1 次提交
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由 Richard Henderson 提交于
Delete inline functions from tcg-target.h that don't need to be there, move the others to tcg-target.c. Add 'Z', 'I', 'J' constraints for 0, signed 11-bit, and signed 5-bit respectively. Add GUEST_BASE support similar to ppc64, with the value stored in a register. Add missing registers to reg_alloc_order. Add support for 12-bit branch relocations. Add functions for synthetic operations: addi, mtctl, dep, shd, vshd, ori, andi, shifts, rotates, multiply, branches, setcond. Split out TLB reads from qemu_ld and qemu_st; fix argument loading for tlb external calls. Generate the prologue. Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 27 3月, 2010 3 次提交
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由 Richard Henderson 提交于
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Richard Henderson 提交于
Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 15 3月, 2010 1 次提交
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由 Aurelien Jarno 提交于
Some targets like ARM would benefit to use 32-bit helpers for div/rem/divu/remu. Create a #define for div2 so that targets can select between div, div2 and helper implementation. Use the helper version if none of the #define are present. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 23 2月, 2010 1 次提交
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由 Jay Foad 提交于
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64. Signed-off-by: NJay Foad <jay.foad@gmail.com> Signed-off-by: Nmalc <av1474@comtv.ru>
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- 25 9月, 2009 1 次提交
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由 Stefan Weil 提交于
Replace surpress, supress by suppress. Signed-off-by: NStefan Weil <weil@mail.berlios.de> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 13 3月, 2009 1 次提交
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由 aurel32 提交于
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
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- 08 3月, 2009 1 次提交
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由 blueswir1 提交于
Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: NStuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
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- 05 10月, 2008 1 次提交
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由 blueswir1 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
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- 30 8月, 2008 1 次提交
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由 blueswir1 提交于
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
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- 13 4月, 2008 1 次提交
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由 aurel32 提交于
(Stuart Brady) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4199 c046a42c-6fe2-441c-8c8c-71466251a162
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