- 02 11月, 2012 1 次提交
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由 Peter Maydell 提交于
To avoid continually having to bump the initrd load address to account for larger kernel images, put the initrd halfway through RAM. This allows large kernels on new boards with lots of RAM to work OK, without breaking existing usecases for boards with only 32MB of RAM. Note that this change fixes in passing a bug where we were passing an overly large max_size to load_image_targphys() for the initrd, which meant that we wouldn't correctly refuse to load an enormous initrd that didn't actually fit into RAM. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@samsung.com> Tested-by: NCole Robinson <crobinso@redhat.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 01 11月, 2012 39 次提交
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git://repo.or.cz/qemu/agraf由 Aurelien Jarno 提交于
* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: pseries: Cleanup duplications of ics_valid_irq() code pseries: Clean up inconsistent variable name in xics.c target-ppc: Extend FPU state for newer POWER CPUs target-ppc: Rework storage of VPA registration state Revert "PPC: pseries: Remove hack for PIO window"
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git://git.linaro.org/people/pmaydell/qemu-arm由 Aurelien Jarno 提交于
* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: (28 commits) hw/sd.c: add SD card save/load support vmstate: Add support for saving/loading bitmaps hw/sd.c: Fix erase for high capacity cards pflash_cfi01: Fix debug mode printfery pflash_cfi0x: QOMified pflash_cfi01: remove unused total_len field pflash_cfi0x: remove unused base field hw/versatile_i2c: Use LOG_GUEST_ERROR hw/arm_l2x0: Use LOG_GUEST_ERROR hw/arm_sysctl: Use LOG_GUEST_ERROR hw/armv7m_nvic: Use LOG_GUEST_ERROR and LOG_UNIMP hw/arm_timer: Use LOG_GUEST_ERROR and LOG_UNIMP hw/arm_gic: Use LOG_GUEST_ERROR hw/arm11mpcore: Use LOG_GUEST_ERROR rather than hw_error() hw/pl190: Use LOG_UNIMP rather than hw_error() hw/pl110: Use LOG_GUEST_ERROR rather than hw_error() hw/pl080: Use LOG_GUEST_ERROR and LOG_UNIMP hw/pl061: Use LOG_GUEST_ERROR hw/pl050: Use LOG_GUEST_ERROR hw/exynos4_boards: Don't prematurely explode QEMUMachineInitArgs ...
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由 David Gibson 提交于
A couple of places in xics.c open-coded the same logic as is already implemented in ics_valid_irq(). This patch fixes the code duplication. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
Throughout xics.c 'nr' is used to refer to a global interrupt number, and 'server' is used to refer to an interrupt server number (i.e. CPU number). Except in icp_set_mfrr(), where 'nr' is used as a server number. Fix this confusing inconsistency. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
This patch adds some extra FPU state to CPUPPCState. Specifically, fpscr is extended to a target_ulong bits, since some recent (64 bit) CPUs now have more status bits than fit inside 32 bits. Also, we add the 32 VSR registers present on CPUs with VSX (these extend the standard FP regs, which together with the Altivec/VMX registers form a 64 x 128bit register file for VSX). We don't actually support the instructions using these extra registers in TCG yet, but we still need a place to store the state so we can sync it with KVM and savevm/loadvm it. This patch updates the savevm code to not fail on the extended state, but also does not actually save it - that's a project for another patch. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
We change the storage of the VPA information to explicitly use fixed size integer types which will make life easier for syncing this data with KVM, which we will need in future. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> [agraf: fix commit message] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
This reverts commit a178274e. Contrary to that commit's message, the users of old_portio are not all gone. In particular VGA still uses it via portio_list_add(). Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Aurelien Jarno 提交于
If the guest uses a TLBWI instruction for upgrading permissions, we don't need to flush the extra TLBs. This improve boot time performance by about 10%. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask the address. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Use the deposit op instead of and hardcoded bit field insertion. It allows the host to emit the corresponding instruction if available. At the same time remove the (lsb > msb) test. The MIPS64R2 instruction set manual says "Because of the instruction format, lsb can never be greater than msb, so there is no UNPREDICATABLE case for this instruction." (Bug reported as LP:1071149.) Cc: Никита Канунников <n.kanunnikov@sbtcom.ru> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
The result of a division by 0, or a division of INT_MIN by -1 in the signed case, is unpredictable. Just replace 0 by 1 in that case so that it doesn't trigger a floating point exception on the host. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Avoid the branches in movn/movz implementation and replace them with movcond. Also update a wrong command. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Store conditional operations only need local temps in user mode. Fix the code to use temp local only in user mode, this spares two memory stores in system mode. At the same time remove a wrong a wrong copied & pasted comment, store operations don't have a register destination. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Load/store from helpers should be avoided as they are quite inefficient. Rewrite unaligned loads instructions using TCG and aligned loads. The number of actual loads operations to implement an unaligned load instruction is reduced from up to 8 to 1. Note: As we can't rely on shift by 32 or 64 undefined behaviour, the code loads already shift by one constants. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
load/store microMIPS helpers are reinventing the wheel. Call do_lw, do_ll, do_sw and do_sl instead of using a macro calling the cpu_* load/store functions. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Only allocate t1 when needed. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Load/store operations use macros for historical reasons. Now that there is no point in keeping them, replace them by direct calls to qemu_ld/st. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Rework *raise_exception*() functions so that they can be called from other helpers, passing the return address as an argument. Use do_raise_exception() function in update_fcr31() to correctly restore the CPU state after an FPU exception. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
softfloat already has a few constants defined, use them instead of redefining them in target-mips. Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and FP_TO_INT64_OVERFLOW as even if they have the same value, they are technically different (and defined differently in the MIPS ISA). Remove the unused constants. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Instead of accessing the flags from the floating point control register after updating it, read the softfloat flags. This is just code cleanup and should not change the behaviour. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
For each FPU instruction that can trigger an FPU exception, to call call update_fcr31() after. Remove the manual NaN assignment in case of float to float operation, as softfloat is already taking care of that. However for float to int operation, the value has to be changed to the MIPS one. In the cvtpw_ps case, the two registers have to be handled separately to guarantee a correct final value in both registers. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Instead of clearing the softfloat exception flags before each floating point instruction, reset them to 0 in update_fcr31() when an exception is detected. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Use the new softfloat floatXX_muladd() functions to implement the madd, msub, nmadd and nmsub instructions. At the same time replace the name of the helpers by the name of the instruction, as the only reason for the previous names was to keep the macros simple. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Add a pickNaNMulAdd function for MIPS, implementing NaN propagation rules for MIPS fused multiply-add instructions. Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
When the CPU state after a possible retranslation is going to be handled through code retranslation, we don't need to save the CPU state before. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
When the CPU state is restored through retranslation after an exception, btarget should also be restored. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Aurelien Jarno 提交于
Commit 9c43b68d do not correctly check for dead outputs when they need to be synced to memory in case of half-dead operations. Fix that by applying the same pattern than for the default case. Tested-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Richard Henderson 提交于
Mark helper functions that raise exceptions, but otherwise do not change TCG register state, with TCG_CALL_NO_WG. Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Jan Kiszka 提交于
As the block layer may decide to flush bottom-halfs while the machine is still initializing (e.g. to read geometry data from the disk), our postponed open event may be processed before the last frontend registered with a muxed chardev. Until the semantics of BHs have been clarified, use an expired timer to achieve the same effect (suggested by Paolo Bonzini). This requires to perform the alarm timer initialization earlier as otherwise timer subsystem can be used before being ready. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
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由 Aurelien Jarno 提交于
All switch() decoding instruction have a default entry, so it is possible to have unused enum entries. Remove conditional definitions of MIPS64 opcode enums, as it only makes the code less readable. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Jia Liu 提交于
Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file. Signed-off-by: NJia Liu <proljc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Jia Liu 提交于
Add MIPS ASE DSP testcases. Signed-off-by: NJia Liu <proljc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Jia Liu 提交于
Add 74kf and mips64dspr2-generic-cpu model for test. Signed-off-by: NJia Liu <proljc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Jia Liu 提交于
Add MIPS ASE DSP Accumulator and DSPControl Access instructions. Signed-off-by: NJia Liu <proljc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Jia Liu 提交于
Add MIPS ASE DSP Compare-Pick instructions. Signed-off-by: NJia Liu <proljc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Jia Liu 提交于
Add MIPS ASE DSP Bit/Manipulation instructions. Signed-off-by: NJia Liu <proljc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Jia Liu 提交于
Add MIPS ASE DSP Multiply instructions. Signed-off-by: NJia Liu <proljc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Jia Liu 提交于
Add MIPS ASE DSP GPR-Based Shift instructions. Signed-off-by: NJia Liu <proljc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Jia Liu 提交于
Add MIPS ASE DSP Arithmetic instructions. Signed-off-by: NJia Liu <proljc@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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