Load/store from helpers should be avoided as they are quite
inefficient. Rewrite unaligned loads instructions using TCG and
aligned loads. The number of actual loads operations to implement
an unaligned load instruction is reduced from up to 8 to 1.

Note: As we can't rely on shift by 32 or 64 undefined behaviour,
the code loads already shift by one constants.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Only allocate t1 when needed.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Use the new softfloat floatXX_muladd() functions to implement the madd,
msub, nmadd and nmsub instructions. At the same time replace the name of
the helpers by the name of the instruction, as the only reason for the
previous names was to keep the macros simple.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

When the CPU state after a possible retranslation is going to be handled
through code retranslation, we don't need to save the CPU state before.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

When the CPU state is restored through retranslation after an exception,
btarget should also be restored.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

All switch() decoding instruction have a default entry, so it is possible
to have unused enum entries. Remove conditional definitions of MIPS64
opcode enums, as it only makes the code less readable.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Compare-Pick instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Bit/Manipulation instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Multiply instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP GPR-Based Shift instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Arithmetic instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Load instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP Branch instructions.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add MIPS ASE DSP resources access check.
Signed-off-by: NJia Liu <proljc@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

With normal FP, this doesn't have much affect on the generated code,
because most of the FP operations are not CONST/PURE, and so we spill
registers in about the same frequency as the explicit load/stores.

But with Loongson multimedia instructions, which are all integral and
whose helpers are in fact CONST+PURE, this greatly improves the code.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.

This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Implements all of the COP2 instructions except for the S<cond>
family of comparisons.  The documentation is unclear for those.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

this will prevent some of the compilation errors with debugging
enabled from creeping back in.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The macro uses the DisasContext.  Pass it around as needed.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Acked-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Used by MIPS_DEBUG, when enabled.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Acked-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
Acked-by: NAurelien Jarno <aurelien@aurel32.net>

 This change updates the CPU reset sequence to use a common piece of code
that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X
not being set where applicable that causes floating-point MADD family
instructions (and other instructions from the MIPS IV FP subset) to trap.

 As compute_hflags is now shared between op_helper.c and translate.c, the
function is now moved to a common header.  There are no changes to this
function.

 The problem was seen with the 24Kf MIPS32r2 processor in user emulation.
The new approach prevents system and user emulation from diverging -- all
the hflags state is initialized in one place now.
Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The microMIPS SWP and SDP instructions do not modify GPRs.  So their
behavior is well defined when RD equals BASE.  The MIPS Architecture
Verification Programs (AVPs) check that they work as expected.  This
is required for AVPs to pass.
Signed-off-by: NEric Johnson <ericj@mips.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The MIPS Architecture Verification Programs (AVPs) check privileged
instructions for the required privilege level.  These changes are needed
to pass the AVP suite.
Signed-off-by: NEric Johnson <ericj@mips.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The kernel will emulate this instruction if it's not supported
natively.  This insn is used for TLS, among other things, and
so is required by modern glibc.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Cc: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

We've already eliminated both base and index being zero.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The FS input to CVT.PS.S is the high half and FT is the low half.
tcg_gen_concat_i32_i64 takes the low half first, so the operands
were in the wrong order.
Signed-off-by: NRichard Sandiford <rdsandiford@googlemail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Read the second input operand of RECIP2.S and RECIP2.PS from FT rather
than FD.  RECIP2.D is already correct.
Signed-off-by: NRichard Sandiford <rdsandiford@googlemail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

While running in the usermode emulator all of the required*
MIPS32r2 RDHWR hardware registers should be accessible (the
Linux kernel enables access to these same registers).  Note
that these registers are still enabled when the MIPS ISA is
not release 2.  This is OK since the Linux kernel emulates
access to them when they are not available in hardware.

* There is also the ULR register which is only recommended
  for full release 2 compliance.  Incidentally, accessing
  this register in the current implementation works fine
  without flipping its access bit.
Signed-off-by: NMeador Inge <meadori@codesourcery.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

 This change addresses a problem where QEMU incorrectly traps on
floating-point MADD group instructions with SIGILL, at least while
emulating MIPS32r2 processors.  These instructions use the COP1X major
opcode and include ones like:

	madd.d	$f2,$f4,$f2,$f6

 Here's Nathan's original analysis of the problem:

"QEMU essentially does:

  d = find_cpu (cpu_string)	// get CPU definition
  fpu_init (env, d)		// initialize fpu state (init FCR0, basically)
  cpu_reset (env)

...and the cpu_reset call clears all interesting state that fpu_init
setup, then proceeds to reinitialize all the CP0 registers...but not
FCR0."

 I have verified this change with system emulation running the GDB test
suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated),
there were 55 progressions and no regressions.
Signed-off-by: NMaciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Turn cpu_init macro into a static inline function returning CPUMIPSState
for backwards compatibility.
Signed-off-by: NAndreas Färber <afaerber@suse.de>

Commit 0f71a709 (target-mips: QOM'ify
CPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping the
introduction of subclasses for 1.1, due to mips_def_t the reset code
could not be QOM'ified yet, i.e. cpu_state_reset() will not forward to
CPUClass::reset().

Update cpu_mips_init() with cpu_reset() nontheless, indirectly calling
cpu_state_reset(), so that generic code can be converted to call
cpu_reset().
Signed-off-by: NAndreas Färber <afaerber@suse.de>

There's some dodgy application of De Morgan's law in the emulation
of the MIPS BC1ANY[24]F instructions: they end up branching only
if all CCs are false, rather than if one CC is.

Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests.
Signed-off-by: NRichard Sandiford <rdsandiford@googlemail.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Move code not dependent on mips_def_t from cpu_mips_init() into a
QOM initfn, as a start.
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Embed CPUMIPSState as first member of QOM MIPSCPU.

Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Scripted conversion:
  sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc]
  sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Acked-by: NAnthony Liguori <aliguori@us.ibm.com>

Frees the identifier cpu_reset for QOM CPUs (manual rename).

Don't hide the parameter type behind explicit casts, use static
functions with strongly typed argument to indirect.
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NAnthony Liguori <aliguori@us.ibm.com>