- 30 1月, 2016 39 次提交
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由 James Clarke 提交于
Signed-off-by: NJames Clarke <jrtc27@jrtc27.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
Now that the TCG and spapr code has been extended to allow (semi-) arbitrary page encodings in the CPU's 'sps' table, we can add the many page sizes supported by real POWER7 and POWER8 hardware that we previously didn't support in TCG. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
h_enter() in the spapr code needs to know the page size of the HPTE it's about to insert. Unlike other paths that do this, it doesn't have access to the SLB, so at the moment it determines this with some open-coded tests which assume POWER7 or POWER8 page size encodings. To make this more flexible add ppc_hash64_hpte_page_shift_noslb() to determine both the "base" page size per segment, and the individual effective page size from an HPTE alone. This means that the spapr code should now be able to handle any page size listed in the env->sps table. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
When HPTEs are removed or modified by hypercalls on spapr, we need to invalidate the relevant pages in the qemu TLB. Currently we do that by doing some complicated calculations to work out the right encoding for the tlbie instruction, then passing that to ppc_tlb_invalidate_one()... which totally ignores the argument and flushes the whole tlb. Avoid that by adding a new flush-by-hpte helper in mmu-hash64.c. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
Currently both the tlbiva instruction (used on 44x chips) and the tlbie instruction (used on hash MMU chips) are both handled via ppc_tlb_invalidate_one(). This is silly, because they're invoked from different places, and do different things. Clean this up by separating out the tlbiva instruction into its own handling. In fact the implementation is only a stub anyway. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NLaurent Vivier <lvivier@redhat.com> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
ppc_tlb_invalidate_one() has a big switch handling many different MMU types. However, most of those branches can never be reached: It is called from 3 places: from remove_hpte() and h_protect() in spapr_hcall.c (which always has a 64-bit hash MMU type), and from helper_tlbie() in mmu_helper.c. Calls to helper_tlbie() are generated from gen_tlbiel, gen_tlbiel and gen_tlbiva. The first two are only used with the PPC_MEM_TLBIE flag, set only with 32-bit or 64-bit hash MMU models, and gen_tlbiva() is used only on 440 and 460 models with the BookE mmu model. These means the exhaustive list of MMU types which may call ppc_tlb_invalidate_one() is: POWERPC_MMU_SOFT_6xx, POWERPC_MMU_601, POWERPC_MMU_32B, POWERPC_MMU_SOFT_74xx, POWERPC_MMU_64B, POWERPC_MMU_2_03, POWERPC_MMU_2_06, POWERPC_MMU_2_07 and POWERPC_MMU_BOOKE. Clean up by removing logic for all other MMU types from ppc_tlb_invalidate_one(). This means that ppc4xx_tlb_invalidate_virt() now has no callers, or rather, makes it obvious that it has no callers. So, we remove that function as well. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
At present the 64-bit hash MMU code uses information from the SLB to determine the page size of a translation. We do need that information to correctly look up the hash table. However the MMU also allows a possibly larger page size to be encoded into the HPTE itself, which is used to populate the TLB. At present qemu doesn't check that, and so doesn't support the MPSS "Multiple Page Size per Segment" feature. This makes a start on allowing this, by adding an hpte_page_shift() function which looks up the page size of an HPTE. We use this to validate page sizes encodings on faults, and populate the qemu TLB with larger page sizes when appropriate. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
Currently, the ppc_hash64_page_shift() function looks up a page size based on information in an SLB entry. It open codes the bit translation for existing CPUs, however different CPU models can have different SLB encodings. We already store those in the 'sps' table in CPUPPCState, but we don't currently enforce that that actually matches the logic in ppc_hash64_page_shift. This patch reworks lookup of page size from SLB in several ways: * ppc_store_slb() will now fail (triggering an illegal instruction exception) if given a bad SLB page size encoding * On success ppc_store_slb() stores a pointer to the relevant entry in the page size table in the SLB entry. This is looked up directly from the published table of page size encodings, so can't get out ot sync. * ppc_hash64_htab_lookup() and others now use this precached page size information rather than decoding the SLB values * Now that callers have easy access to the page_shift, ppc_hash64_pte_raddr() amounts to just a deposit64(), so remove it and have the callers use deposit64() directly. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
ppc_store_slb updates the SLB for PPC cpus with 64-bit hash MMUs. Currently it takes two parameters, which contain values encoded as the register arguments to the slbmte instruction, one register contains the ESID portion of the SLBE and also the slot number, the other contains the VSID portion of the SLBE. We're shortly going to want to do some SLB updates from other code where it is more convenient to supply the slot number and ESID separately, so rework this function and its callers to work this way. As a bonus, this slightly simplifies the emulation of segment registers for when running a 32-bit OS on a 64-bit CPU. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NLaurent Vivier <lvivier@redhat.com> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
Like a lot of places these files include a mixture of functions taking both the older CPUPPCState *env and newer PowerPCCPU *cpu. Move a step closer to cleaning this up by standardizing on PowerPCCPU, except for the helper_* functions which are called with the CPUPPCState * from tcg. Callers and some related functions are updated as well, the boundaries of what's changed here are a bit arbitrary. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NLaurent Vivier <lvivier@redhat.com> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
This stub function is in the !KVM ifdef in target-ppc/kvm_ppc.h. However no such function exists on the KVM side, or is ever used. I think this originally referenced a function which read host page size information from /proc, for we we now use the KVM GET_SMMU_INFO extension instead. In any case, it has no function now, so remove it. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NLaurent Vivier <lvivier@redhat.com> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 Programmingkid 提交于
Darwin/OS X use the undocumented kMacRISCPCIAddressSelect (0x48) to configure PCI memory space size for mac99 machines. Without this register, warnings similar to below are emitted to the console during boot: AppleMacRiscPCI: bad range 2(80000000:01000000) AppleMacRiscPCI: bad range 2(81000000:00001000) AppleMacRiscPCI: bad range 2(81080000:00080000) Based upon the algorithm in Darwin's AppleMacRiscPCI.cpp driver, set the kMacRISCPCIAddressSelect register so that Darwin considers the PCI memory space to be at 0x80000000 (size 0x10000000) which matches that currently used by QEMU and OpenBIOS. Signed-off-by: NJohn Arbuckle <programmingkidx@gmail.com> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> [commit message and comment revised as suggested by Mark Cave-Ayland] Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Alyssa Milburn 提交于
This avoids MacsBug hanging at startup in the absence of ADB mouse input, by replying with an error (which is also what MOL does) when it sends an unknown command (0x1c). Signed-off-by: NAlyssa Milburn <fuzzie@fuzzie.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
The implementation of the H_ENTER hypercall for PAPR guests needs to enforce correct access attributes on the inserted HPTE. This means determining if the HPTE's real address is a regular RAM address (which requires attributes for coherent access) or an IO address (which requires attributes for cache-inhibited access). At the moment this check is implemented with (raddr < machine->ram_size), but that only handles addresses in the base RAM area, not any hotplugged RAM. This patch corrects the problem with a new helper. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
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由 Anton Blanchard 提交于
Add the XML and functions to get and set VSX registers. Signed-off-by: NAnton Blanchard <anton@samba.org> (fixed little-endian guests) Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
Let's reuse the ppc_maybe_bswap_register() helper, like we already do with the general registers. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
Altivec registers are 128-bit wide. They are stored in memory as two 64-bit values that must be byteswapped when the guest is little-endian. Let's reuse the ppc_maybe_bswap_register() helper for this. We also need to fix the ordering of the 64-bit elements according to the target endianness, for both system and user mode. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
This helper will be used to support Altivec registers in little-endian guests. This patch does not change functionnality. Note: I had to put the helper some lines away from the gdb_*_avr_reg() routines to get a more readable patch. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
Let's reuse the ppc_maybe_bswap_register() helper, like we already do with the general registers. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
This helper will be used to support FP, Altivec and VSX registers when the guest is little-endian. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
On VSX capable CPUs, the 32 FP registers are mapped to the high-bits of the 32 first VSX registers. So if you have: VSR31 = (uint128) 0x0102030405060708090a0b0c0d0e0f00 then FPR31 = (uint64) 0x0102030405060708 The kernel stores the VSX registers in the fp_state struct following the host endian element ordering. On big-endian: fp_state.fpr[31][0] = 0x0102030405060708 fp_state.fpr[31][1] = 0x090a0b0c0d0e0f00 On little-endian: fp_state.fpr[31][0] = 0x090a0b0c0d0e0f00 fp_state.fpr[31][1] = 0x0102030405060708 The KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls preserve this ordering, but QEMU considers it as big-endian and always copies element [0] to the fpr[] array and element [1] to the vsr[] array. This does not work with little-endian hosts, and you will get: (qemu) p $f31 0x90a0b0c0d0e0f00 instead of: (qemu) p $f31 0x102030405060708 This patch fixes the element ordering for little-endian hosts. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
The functions for migrating the hash page table on pseries machine type (htab_save_setup() and htab_load()) can report some errors with an explicit fprintf() before returning an appropriate error code. Change some of these to use error_report() instead. htab_save_setup() is omitted for now to avoid conflicts with some other in-progress work. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
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由 David Gibson 提交于
This function includes a number of explicit fprintf()s for errors. Change these to use error_report() instead. Also replace the single exit(EXIT_FAILURE) with an explicit exit(1), since the latter is the more usual idiom in qemu by a large margin. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
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由 David Gibson 提交于
Use the error handling infrastructure to pass an error out from try_create_xics() instead of assuming &error_abort - the caller is in a better position to decide on error handling policy. Also change the error handling from an &error_abort to &error_fatal, since this occurs during the initial machine construction and could be triggered by bad configuration rather than a program error. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
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由 David Gibson 提交于
The errors detected in this function necessarily indicate bugs in the rest of the qemu code, rather than an external or configuration problem. So, a simple assert() is more appropriate than any more complex error reporting. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
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由 David Gibson 提交于
Use error_setg() to return an error rather than an explicit exit(). Previously it was an exit(0) instead of a non-zero exit code, which was simply a bug. Also improve the error message. While we're at it change the type of spapr_vga_init() to bool since that's how we're using it anyway. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
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由 David Gibson 提交于
Use error_setg() and return an error, rather than using an explicit exit(). Also improve messages, and be more explicit about which constraint failed. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
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由 David Gibson 提交于
Currently spapr_cpu_init() is hardcoded to handle any errors as fatal. That works for now, since it's only called from initial setup where an error here means we really can't proceed. However, we'll want to handle this more flexibly for cpu hotplug in future so generalize this using the error reporting infrastructure. While we're at it make a small cleanup in a related part of ppc_spapr_init() to use error_report() instead of an old-style explicit fprintf(). Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
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由 David Gibson 提交于
Current ppc_set_compat() returns -1 for errors, and also (unconditionally) reports an error message. The caller in h_client_architecture_support() may then report it again using an outdated fprintf(). Clean this up by using the modern error reporting mechanisms. Also add strerror(errno) to the error message. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NMarkus Armbruster <armbru@redhat.com>
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由 Bharata B Rao 提交于
If guest doesn't have any dynamically reconfigurable (DR) logical memory blocks (LMB), then we shouldn't create ibm,dynamic-reconfiguration-memory device tree node. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
h_client_architecture_support() uses rtas_ld() for general purpose memory access, despite the fact that it's not an RTAS routine at all and rtas_ld makes things more awkward. Clean this up by replacing rtas_ld() calls with appropriate ldXX_phys() calls. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
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由 David Gibson 提交于
rtas_st_buffer_direct() is a not particularly useful wrapper around cpu_physical_memory_write(). All the callers are in rtas_ibm_configure_connector, where it's better handled by local helper. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
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由 David Gibson 提交于
rtas_st_buffer() appears in spapr.h as though it were a widely used helper, but in fact it is only used for saving data in a format used by rtas_ibm_get_system_parameter(). This changes it to a local helper more specifically for that function. While we're there fix a couple of small defects in rtas_ibm_get_system_parameter: - For the string value SPLPAR_CHARACTERISTICS, it wasn't including the terminating \0 in the length which it should according to LoPAPR 7.3.16.1 - It now checks that the supplied buffer has at least enough space for the length of the returned data, and returns an error if it does not. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
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由 Mark Cave-Ayland 提交于
Include some fields missed from the previous VMState conversion to the migration stream, as well as the new SR_INT delay timer. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Mark Cave-Ayland 提交于
Make sure that we include the DBDMA controller state in the migration stream. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Mark Cave-Ayland 提交于
Make sure that we include the value of dma_active in the migration stream. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: NJohn Snow <jsnow@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Mark Cave-Ayland 提交于
Currently the aiocb is held within MACIOIDEState, however the IDE core code assumes that the current actvie DMA aiocb is held in aiocb in a few places, e.g. ide_bus_reset() and ide_reset(). Switch over to using IDEDMA aiocb to store the aiocb for the current active DMA request so that bus resets and restarts are handled correctly. As a consequence we can now use ide_set_inactive() rather than handling its functionality ourselves. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: NJohn Snow <jsnow@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Mark Cave-Ayland 提交于
Otherwise some internal xer variables fail to get set post-migration. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
We never released anything older than POWER8 DD2.0 and POWER8E DD2.1, so let's use these versions, without that some firmware or Linux code might fail to use some HW features that were non functional in earlier internal only spins of the chip. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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- 29 1月, 2016 1 次提交
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由 Peter Maydell 提交于
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-38-git-send-email-peter.maydell@linaro.org
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