- 12 3月, 2019 26 次提交
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由 Cédric Le Goater 提交于
The PowerNV machine can perform indirect loads and stores on the TIMA on behalf of another CPU. Give the controller the possibility to call the TIMA memory accessors with a XiveTCTX of its choice. Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-4-clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
We will use it to get the CPU interrupt presenter in XIVE when the TIMA is accessed from the indirect page. Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-3-clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
By default on P9, the HW CAM line (23bits) is hardwired to : 0x000||0b1||4Bit chip number||7Bit Thread number. When the block group mode is enabled at the controller level (PowerNV), the CAM line is changed for CAM compares to : 4Bit chip number||0x001||7Bit Thread number This will require changes in xive_presenter_tctx_match() possibly. This is a lowlevel functionality of the HW controller and it is not strictly needed. Leave it for later. Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-Id: <20190306085032.15744-2-clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Andrew Randrianasulu 提交于
Original commit message: This patch adds an emulation model for i2c controller found on most of the FSL SoCs. It also integrates the RTC (ds1338) that sits on the i2c Bus with e500 machine model. Patch was originally written by Amit Singh Tomar <amit.tomar@freescale.com> see http://patchwork.ozlabs.org/patch/431475/ I only fixed it enough for application on top of current qemu master 20b084c4, and hopefully fixed checkpatch errors Tested by booting Linux kernel 4.20.12. Now e500 machine doesn't need network time protocol daemon because it will have working RTC (before all timestamps on files were from 2016) Signed-off-by: NAmit Singh Tomar <amit.tomar@freescale.com> Signed-off-by: NAndrew Randrianasulu <randrianasulu@gmail.com> Message-Id: <20190306102812.28972-1-randrianasulu@gmail.com> [dwg: Add Kconfig stanza to define the new symbol, update MAINTAINERS] Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
The H_CALL H_PAGE_INIT can be used to zero or copy a page of guest memory. Enable the in-kernel H_PAGE_INIT handler. The in-kernel handler takes half the time to complete compared to handling the H_CALL in userspace. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190306060608.19935-1-sjitindarsingh@gmail.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
SPAPR_MEMORY_BLOCK_SIZE is logically a difference in memory addresses, and hence of type hwaddr which is 64-bit. Previously it wasn't marked as such which means that it could be treated as 32-bit. That will work in some circumstances but if multiplied by another 32-bit value it could lead to a 32-bit overflow and an incorrect result. One specific instance of this in spapr_lmb_dt_populate() was spotted by Coverity (CID 1399145). Reported-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
If we allocate a hash page table then we know that the guest won't be using process tables, so set the partition table entry maintained for the guest to zero. If this isn't done, then the guest radix bit will remain set in the entry. This means that when the guest calls H_REGISTER_PROCESS_TABLE there will be a mismatch between then flags and the value in spapr->patb_entry, and the call will fail. The guest will then panic: Failed to register process table (rc=-4) kernel BUG at arch/powerpc/platforms/pseries/lpar.c:959 The result being that it isn't possible to boot a hash guest on a P9 system. Also fix a bug in the flags parsing in h_register_process_table() which was introduced by the same patch, and simplify the handling to make it less likely that errors will be introduced in the future. The effect would have been setting the host radix bit LPCR_HR for a hash guest using process tables, which currently isn't supported and so couldn't have been triggered. Fixes: 00fd075e "target/ppc/spapr: Set LPCR:HR when using Radix mode" Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190305022102.17610-1-sjitindarsingh@gmail.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Alexander Graf 提交于
Quite a while has passed since we last updated U-Boot for e500. This patch bumps it to the last released version 2019.01 to make sure users don't feel like they're using out of date software. Signed-off-by: NAlexander Graf <agraf@csgraf.de> Message-Id: <20190304103930.16319-1-agraf@csgraf.de> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Fabiano Rosas 提交于
There are four scenarios being handled in this function: - single stepping - hardware breakpoints - software breakpoints - fallback (no debug supported) A future patch will add code to handle specific single step and software breakpoints cases so let's split each scenario into its own function now to avoid hurting readability. Signed-off-by: NFabiano Rosas <farosas@linux.ibm.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190228225759.21328-5-farosas@linux.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Fabiano Rosas 提交于
This is in preparation for a refactoring of the kvm_handle_debug function in the next patch. Signed-off-by: NFabiano Rosas <farosas@linux.ibm.com> Message-Id: <20190228225759.21328-4-farosas@linux.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Fabiano Rosas 提交于
Signed-off-by: NFabiano Rosas <farosas@linux.ibm.com> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190228225759.21328-2-farosas@linux.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
There are currently 3 mitigations the availability of which is controlled by the spapr-caps mechanism, cap-cfpc, cap-sbbc, and cap-ibs. Enable these mitigations by default for the pseries-4.0 machine type. By now machine firmware should have been upgraded to allow these settings. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301044609.9626-3-sjitindarsingh@gmail.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
The spapr_caps cap-cfpc, cap-sbbc and cap-ibs are used to control the availability of certain mitigations to the guest. These haven't been implemented under TCG, it is unlikely they ever will be, and it is unclear as to whether they even need to be. As such, make failure to apply these capabilities under TCG non-fatal. Instead we print a warning message to the user but still allow the guest to continue. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301044609.9626-2-sjitindarsingh@gmail.com> [dwg: Small style fix] Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate the requirement for a hw-assisted version of the count cache flush workaround. The count cache flush workaround is a software workaround which can be used to flush the count cache on context switch. Some revisions of hardware may have a hardware accelerated flush, in which case the software flush can be shortened. This cap is used to set the availability of such hardware acceleration for the count cache flush routine. The availability of such hardware acceleration is indicated by the H_CPU_CHAR_BCCTR_FLUSH_ASSIST flag being set in the characteristics returned from the KVM_PPC_GET_CPU_CHAR ioctl. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301031912.28809-2-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
The spapr_cap SPAPR_CAP_IBS is used to indicate the level of capability for mitigations for indirect branch speculation. Currently the available values are broken (default), fixed-ibs (fixed by serialising indirect branches) and fixed-ccd (fixed by diabling the count cache). Introduce a new value for this capability denoted workaround, meaning that software can work around the issue by flushing the count cache on context switch. This option is available if the hypervisor sets the H_CPU_BEHAV_FLUSH_COUNT_CACHE flag in the cpu behaviours returned from the KVM_PPC_GET_CPU_CHAR ioctl. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301031912.28809-1-sjitindarsingh@gmail.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
Enable the large decrementer by default for the pseries-4.0 machine type. It is disabled again by default_caps_with_cpu() for pre-POWER9 cpus since they don't support the large decrementer. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301024317.22137-4-sjitindarsingh@gmail.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
Implement support to allow KVM guests to take advantage of the large decrementer introduced on POWER9 cpus. To determine if the host can support the requested large decrementer size, we check it matches that specified in the ibm,dec-bits device-tree property. We also need to enable it in KVM by setting the LPCR_LD bit in the LPCR. Note that to do this we need to try and set the bit, then read it back to check the host allowed us to set it, if so we can use it but if we were unable to set it the host cannot support it and we must not use the large decrementer. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-Id: <20190301024317.22137-3-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
Prior to POWER9 the decrementer was a 32-bit register which decremented with each tick of the timebase. From POWER9 onwards the decrementer can be set to operate in a mode called large decrementer where it acts as a n-bit decrementing register which is visible as a 64-bit register, that is the value of the decrementer is sign extended to 64 bits (where n is implementation dependant). The mode in which the decrementer operates is controlled by the LPCR_LD bit in the logical paritition control register (LPCR). >From POWER9 onwards the HDEC (hypervisor decrementer) was enlarged to h-bits, also sign extended to 64 bits (where h is implementation dependant). Note this isn't configurable and is always enabled. On POWER9 the large decrementer and hdec are both 56 bits, as represented by the lrg_decr_bits cpu class property. Since they are the same size we only add one property for now, which could be extended in the case they ever differ in the future. We also add the lrg_decr_bits property for POWER5+/7/8 since it is used to determine the size of the hdec, which is only generated on the POWER5+ processor and later. On these processors it is 32 bits. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-Id: <20190301024317.22137-2-sjitindarsingh@gmail.com> [dwg: Small style fixes] Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Suraj Jitindar Singh 提交于
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the availability of the large decrementer for a guest. Signed-off-by: NSuraj Jitindar Singh <sjitindarsingh@gmail.com> Message-Id: <20190301024317.22137-1-sjitindarsingh@gmail.com> [dwg: Trivial style fix] Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
Commit b8165118 broke CPU hotplug tests for old machine types: $ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 ./tests/cpu-plug-test -m=slow /ppc64/cpu-plug/pseries-3.1/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.12-sxxm/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-3.0/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.10/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.11/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.12/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.9/device-add/2x3x1&maxcpus=6: OK /ppc64/cpu-plug/pseries-2.7/device-add/2x3x1&maxcpus=6: ** ERROR:/home/thuth/devel/qemu/hw/ppc/spapr_events.c:313:rtas_event_log_to_source: assertion failed: (source->enabled) Broken pipe /home/thuth/devel/qemu/tests/libqtest.c:143: kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped) Aborted (core dumped) The approach of faking the availability of OV5_HP_EVT causes the code to assume the hotplug event source is enabled, which is wrong for older machines. We've now fixed CAS under qtest with a different approach. Therefore, this reverts commit b8165118. A subsequent patch will address the problem of CAS under qtest from a different angle. Reported-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NGreg Kurz <groug@kaod.org> Message-Id: <155146875097.147873.1732264036668112686.stgit@bahia.lan> Tested-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
The RTAS event hotplug code for machine types 2.8 and newer depends on the CAS negotiated ov5 in order to work properly. However, there's no CAS when running under qtest. There has been a tentative to trick the code by faking the OV5_HP_EVT bit, but it turned out to break other assumptions in the code and the change got reverted. Go for a more general approach and simulate a CAS when running under qtest. For simplicity, this pseudo CAS simple simulates the case where the guest supports the same features as the machine. It is done at reset time, just before we reset the DRCs, which could potentially exercise the unplug code. This allows to test unplug on spapr with both older and newer machine types. Suggested-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NGreg Kurz <groug@kaod.org> Message-Id: <155146875704.147873.10563808578795890265.stgit@bahia.lan> Tested-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: NMichael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Alexey Kardashevskiy 提交于
The "systempagesize" name suggests that it is the host system page size while it is the smallest page size of memory backing the guest RAM so let's rename it to stop confusion. This should cause no behavioral change. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190227085149.38596-4-aik@ozlabs.ru> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Alexey Kardashevskiy 提交于
The current code assumes that we can address more bits on a PCI bus for DMA than we really can but there is no way knowing the actual limit. This makes a better guess for the number of levels and if the kernel fails to allocate that, this increases the level numbers till succeeded or reached the 64bit limit. This adds levels to the trace point. This may cause the kernel to warn about failed allocation: [65122.837458] Failed to allocate a TCE memory, level shift=28 which might happen if MAX_ORDER is not large enough as it can vary: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/Kconfig?h=v5.0-rc2#n727Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20190227085149.38596-3-aik@ozlabs.ru> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Peter Maydell 提交于
* allow building QEMU without TCG or KVM support (Anthony) * update AMD IOMMU copyright (David) * compilation fixes for GCC and BSDs (Alexey, David, Paolo, Philippe) * coalesced I/O bugfix (Jagannathan) * Processor Tracing cpuid fix (Luwei) * Kconfig fixes (Paolo, David) * Cleanups (Paolo, Wei) * PVH vs. multiboot fix (Stefano) * LSI bugfixes (Sven) * elf2dmp Coverity fix (Victor) * scsi-disk fix (Zhengui) * authorization support for chardev TLS (Daniel) # gpg: Signature made Mon 11 Mar 2019 16:12:00 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (31 commits) qemugdb: fix licensing chardev: add support for authorization for TLS clients qom: cpu: destroy work_mutex in cpu_common_finalize exec.c: refactor function flatview_add_to_dispatch() lsi: 810/895A are always little endian lsi: return dfifo value lsi: use SCSI phase names instead of numbers in trace lsi: use enum type for s->msg_action lsi: use enum type for s->waiting lsi: use ldn_le_p()/stn_le_p() scsi-disk: Fix crash if request is invaild or disk is no medium configure: Disable W^X on OpenBSD oslib-posix: Ignore fcntl("/dev/null", F_SETFL, O_NONBLOCK) failure accel: Allow to build QEMU without TCG or KVM support build: clean trace/generated-helpers.c build: remove unnecessary assignments from Makefile.target build: get rid of target-obj-y update copyright notice lsi: check if SIGP bit is already set in Wait reselect lsi: implement basic SBCL functionality ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
MIPS queue for March 11th, 2019 # gpg: Signature made Mon 11 Mar 2019 14:16:09 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-mar-11-2019: target/mips: Add tests for a variety of MSA integer subtract instructions target/mips: Add tests for a variety of MSA integer multiply instructions target/mips: Add tests for a variety of MSA integer dot product instructions target/mips: Add tests for a variety of MSA integer divide instructions target/mips: Add tests for a variety of MSA integer average instructions tests/tcg: target/mips: Rename two header files for consistency tests/tcg: target/mips: Correct preambles of test source files Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
s390x update: - clean up LowCore definition - first part of vector instruction support for tcg # gpg: Signature made Mon 11 Mar 2019 08:59:02 GMT # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20190311: (33 commits) s390x/tcg: Implement VECTOR UNPACK * s390x/tcg: Implement VECTOR STORE WITH LENGTH s390x/tcg: Implement VECTOR STORE MULTIPLE s390x/tcg: Implement VECTOR STORE ELEMENT s390x/tcg: Implement VECTOR STORE s390x/tcg: Provide probe_write_access helper s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORD s390x/tcg: Implement VECTOR SELECT s390x/tcg: Implement VECTOR SCATTER ELEMENT s390x/tcg: Implement VECTOR REPLICATE IMMEDIATE s390x/tcg: Implement VECTOR REPLICATE s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATE s390x/tcg: Implement VECTOR PERMUTE s390x/tcg: Implement VECTOR PACK * s390x/tcg: Implement VECTOR MERGE (HIGH|LOW) s390x/tcg: Implement VECTOR LOAD WITH LENGTH s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINT s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GR s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARY s390x/tcg: Implement VECTOR LOAD MULTIPLE ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 11 3月, 2019 14 次提交
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由 Paolo Bonzini 提交于
qemu-gdb.py was committed after 2012-01-13, so the notice about GPL v2-only contributions does not apply. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Daniel P. Berrange 提交于
Currently any client which can complete the TLS handshake is able to use a chardev server. The server admin can turn on the 'verify-peer' option for the x509 creds to require the client to provide a x509 certificate. This means the client will have to acquire a certificate from the CA before they are permitted to use the chardev server. This is still a fairly low bar. This adds a 'tls-authz=OBJECT-ID' option to the socket chardev backend which takes the ID of a previously added 'QAuthZ' object instance. This will be used to validate the client's x509 distinguished name. Clients failing the check will not be permitted to use the chardev server. For example to setup authorization that only allows connection from a client whose x509 certificate distinguished name contains 'CN=fred', you would use: $QEMU -object tls-creds-x509,id=tls0,dir=/home/berrange/qemutls,\ endpoint=server,verify-peer=yes \ -object authz-simple,id=authz0,identity=CN=laptop.example.com,,\ O=Example Org,,L=London,,ST=London,,C=GB \ -chardev socket,host=127.0.0.1,port=9000,server,\ tls-creds=tls0,tls-authz=authz0 \ ...other qemu args... Signed-off-by: NDaniel P. Berrange <berrange@redhat.com> Reviewed-by: NMarc-André Lureau <marcandre.lureau@redhat.com>
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由 Li Qiang 提交于
Commit 376692b9(cpus: protect work list with work_mutex) initialize a work_mutex in cpu_common_initfn, however forget to destroy it. This will cause resource leak when hotunplug cpu or hotplug cpu fails. Signed-off-by: NLi Qiang <liq3ea@163.com> Message-Id: <20190102074114.26988-1-liq3ea@163.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Wei Yang 提交于
flatview_add_to_dispatch() registers page based on the condition of *section*, which may looks like this: |s|PPPPPPP|s| where s stands for subpage and P for page. The procedure of this function could be described as: - register first subpage - register page - register last subpage This means the procedure could be simplified into these three steps instead of a loop iteration. This patch refactors the function into three corresponding steps and adds some comment to clarify it. Signed-off-by: NWei Yang <richardw.yang@linux.intel.com> Message-Id: <20190311054252.6094-1-richardw.yang@linux.intel.com> [Paolo: move exit before adjustment of remain.offset_within_*, otherwise int128_get64 fails when a region is 2^64 bytes long] Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Sven Schnelle 提交于
Signed-off-by: NSven Schnelle <svens@stackframe.org> Message-Id: <20190218175529.11237-1-svens@stackframe.org> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Sven Schnelle 提交于
Code was assigning DFIFO, but didn't return the value to users. Signed-off-by: NSven Schnelle <svens@stackframe.org> Message-Id: <20190305195519.24303-6-svens@stackframe.org>
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由 Sven Schnelle 提交于
This makes trace logs much easier to read, especially for people who are not fluent in SCSI. Signed-off-by: NSven Schnelle <svens@stackframe.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190305195519.24303-5-svens@stackframe.org>
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由 Sven Schnelle 提交于
This makes the code easier to read - no functional change. Signed-off-by: NSven Schnelle <svens@stackframe.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190305195519.24303-4-svens@stackframe.org>
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由 Sven Schnelle 提交于
This makes the code easier to read - no functional change. Signed-off-by: NSven Schnelle <svens@stackframe.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190305195519.24303-3-svens@stackframe.org>
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由 Sven Schnelle 提交于
Instead of using the open-coded versions, use the helper already present as this makes the code easier to read and less error-prone. Signed-off-by: NSven Schnelle <svens@stackframe.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190305195519.24303-2-svens@stackframe.org>
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由 Zhengui Li 提交于
Qemu will crash with the assertion error that "assert(r->req.aiocb != NULL)" in scsi_read_complete if request is invaild or disk is no medium. The error is below: qemu-kvm: hw/scsi/scsi_disk.c:299: scsi_read_complete: Assertion `r->req.aiocb != NULL' failed. This patch add a funtion scsi_read_complete_noio to fix it. Signed-off-by: NZhengui Li <lizhengui@huawei.com> Message-Id: <1551949966-20092-1-git-send-email-lizhengui@huawei.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Philippe Mathieu-Daudé 提交于
Since OpenBSD 6.0 [1], W^X is enforced by default [2]. TCG requires WX access. Disable W^X if it is available. This fixes: # lm32-softmmu/qemu-system-lm32 Could not allocate dynamic translator buffer # sysctl kern.wxabort=1 kern.wxabort: 0 -> 1 # lm32-softmmu/qemu-system-lm32 mmap: Not supported Abort trap (core dumped) # gdb -q lm32-softmmu/qemu-system-lm32 qemu-system-lm32.core (gdb) bt #0 0x000017e3c156c50a in _thread_sys___syscall () at {standard input}:5 #1 0x000017e3c15e5d7a in *_libc_mmap (addr=Variable "addr" is not available.) at /usr/src/lib/libc/sys/mmap.c:47 #2 0x000017e17d9abc8b in alloc_code_gen_buffer () at /usr/src/qemu/accel/tcg/translate-all.c:1064 #3 0x000017e17d9abd04 in code_gen_alloc (tb_size=0) at /usr/src/qemu/accel/tcg/translate-all.c:1112 #4 0x000017e17d9abe81 in tcg_exec_init (tb_size=0) at /usr/src/qemu/accel/tcg/translate-all.c:1149 #5 0x000017e17d9897e9 in tcg_init (ms=0x17e45e456800) at /usr/src/qemu/accel/tcg/tcg-all.c:66 #6 0x000017e17d9891b8 in accel_init_machine (acc=0x17e3c3f50800, ms=0x17e45e456800) at /usr/src/qemu/accel/accel.c:63 #7 0x000017e17d989312 in configure_accelerator (ms=0x17e45e456800, progname=0x7f7fffff07b0 "lm32-softmmu/qemu-system-lm32") at /usr/src/qemu/accel/accel.c:111 #8 0x000017e17d9d8616 in main (argc=1, argv=0x7f7fffff06b8, envp=0x7f7fffff06c8) at vl.c:4325 [1] https://www.openbsd.org/faq/upgrade60.html [2] https://undeadly.org/cgi?action=article&sid=20160527203200Signed-off-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190307142822.8531-3-philmd@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Philippe Mathieu-Daudé 提交于
Previous to OpenBSD 6.3 [1], fcntl(F_SETFL) is not permitted on memory devices. Trying this call sets errno to ENODEV ("not a memory device"): 19 ENODEV Operation not supported by device. An attempt was made to apply an inappropriate function to a device, for example, trying to read a write-only device such as a printer. Do not assert fcntl failures in this specific case (errno set to ENODEV) on OpenBSD. This fixes: $ lm32-softmmu/qemu-system-lm32 assertion "f != -1" failed: file "util/oslib-posix.c", line 247, function "qemu_set_nonblock" Abort trap (core dumped) [1] The fix seems https://github.com/openbsd/src/commit/c2a35b387f9d3c "fcntl(F_SETFL) invokes the FIONBIO and FIOASYNC ioctls internally, so the memory devices (/dev/null, /dev/zero, etc) need to permit them." Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190307142822.8531-2-philmd@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Anthony PERARD 提交于
Instead of deny build of QEMU without a default accelerator, simply report an error when the user haven't passed -accel or -machine accel= and TCG and KVM isn't builtin. ./configure already check that at least one accelerator is available. Signed-off-by: NAnthony PERARD <anthony.perard@citrix.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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