- 19 10月, 2016 1 次提交
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由 Gonglei 提交于
It can't guarantee all cipher modes are supported if one cipher algorithm is supported by a backend. Let's extend qcrypto_cipher_supports() to take both the algorithm and mode as parameters. Signed-off-by: NGonglei <arei.gonglei@huawei.com> Signed-off-by: NDaniel P. Berrange <berrange@redhat.com>
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- 18 10月, 2016 39 次提交
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由 Peter Maydell 提交于
x86 queue, 2016-10-17 # gpg: Signature made Mon 17 Oct 2016 18:51:07 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: (21 commits) target-i386: Don't use cpu->migratable when filtering features target-i386: Return runnability information on query-cpu-definitions target-i386: x86_cpu_load_features() function target-i386: Unset cannot_destroy_with_object_finalize_yet target-i386/kvm: cache the return value of kvm_enable_x2apic() intel_iommu: reject broken EIM intel_iommu: add OnOffAuto intr_eim as "eim" property intel_iommu: redo configuraton check in realize intel_iommu: pass whole remapped addresses to apic apic: add send_msi() to APICCommonClass apic: add global apic_get_class() target-i386: Move warning code outside x86_cpu_filter_features() qmp: Add runnability information to query-cpu-definitions target-i386: xsave: Add FP and SSE bits to x86_ext_save_areas target-i386: Register properties for feature aliases manually target-i386: Remove underscores from feat_names arrays target-i386: Make plus_features/minus_features QOM-based target-i386: Register aliases for feature names with underscores target-i386: Disable VME by default with TCG target-i386: List CPU models using subclass list ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
target-arm: * target-arm: kvm: use AddressSpace-specific listener * aspeed: add SMC controllers * hw/arm/boot: allow using a command line specified dtb without a kernel * hw/dma/pl080: Fix bad bit mask * hw/intc/arm_gic_kvm: Fix build on aarch64 with some compilers * hw/arm/virt: fix ACPI tables for ITS * tests: add a m25p80 test * tests: cleanup ptimer-test * pxa2xx: Auto-assign name for i2c bus in i2c_init_bus * target-arm: handle tagged addresses in A64 code * target-arm: Fix masking of PC lower bits when doing exception returns * target-arm: Implement dummy MDCCINT_EL1 * target-arm: Add trace events for the generic timers * hw/intc/arm_gicv3: Fix ICC register tracepoints * hw/char/pl011: Add trace events # gpg: Signature made Mon 17 Oct 2016 19:39:42 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20161017: (25 commits) hw/char/pl011: Add trace events hw/intc/arm_gicv3: Fix ICC register tracepoints target-arm: Add trace events for the generic timers target-arm: Implement dummy MDCCINT_EL1 Fix masking of PC lower bits when doing exception returns target-arm: Comments added to identify cases in a switch target-arm: Code changes to implement overwrite of tag field on PC load target-arm: Infrastucture changes to enable handling of tagged address loading into PC pxa2xx: Auto-assign name for i2c bus in i2c_init_bus. tests: cleanup ptimer-test tests: add a m25p80 test hw/arm/virt: no ITS on older machine types hw/arm/virt-acpi-build: fix MADT generation hw/intc/arm_gic_kvm: Fix build on aarch64 hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1) hw/arm/boot: allow using a command line specified dtb without a kernel aspeed: add support for the SMC segment registers aspeed: create mapping regions for the maximum number of slaves aspeed: add support for the AST2500 SoC SMC controllers aspeed: extend the number of host SPI controllers ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Add some trace events for the pl011 UART model. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1476294876-12340-5-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Fix some problems with the tracepoints for ICC register reads and writes: * tracepoints for ICC_BPR<n>, ICC_AP<n>R<x>, ICC_IGRPEN<n>, ICC_EIOR<n> were not printing the <n> that indicated whether the access was to the group 0 or 1 register * the ICC_IGREPEN1_EL3 read function was not actually calling the associated tracepoint * the ICC_BPR<n> write function was incorrectly calling the tracepoint for ICC_PMR writes Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1476294876-12340-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Add some useful trace events for the ARM generic timers (notably the various register writes and the resulting IRQ line state). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1476294876-12340-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
MDCCINT_EL1 is part of the DCC debugger communication channel between the CPU and an attached external debugger. QEMU doesn't implement this, but since Linux may try to access this register we need to provide at least a dummy implementation. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1476294876-12340-2-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In commit 9b6a3ea7 store_reg() was changed to mask both bits 0 and 1 of the new PC value when in ARM mode. Unfortunately this broke the exception return code paths when doing a return from ARM mode to Thumb mode: in some of these we write a new CPSR including new Thumb mode bit via gen_helper_cpsr_write_eret(), and then use store_reg() to write the new PC. In this case if the new CPSR specified Thumb mode then masking bit 1 of the PC is incorrect (these code paths correspond to the v8 ARM ARM pseudocode function AArch32.ExceptionReturn(), which always aligns the new PC appropriately for the new instruction set state). Instead of using store_reg() in exception-return code paths, call a new store_pc_exc_ret() which stores the raw new PC value to env->regs[15], and then mask it appropriately in the subsequent helper_cpsr_write_eret() where the new env->thumb state is available. This fixes a bug introduced by 9b6a3ea7 which caused crashes/hangs or otherwise bad behaviour for Linux when userspace was using Thumb. Reported-by: NJerome Forissier <jerome.forissier@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1476113163-24578-1-git-send-email-peter.maydell@linaro.org
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由 Thomas Hanson 提交于
3 cases in a switch in disas_exc() require reference to the ARM ARM spec in order to determine what case they're handling. Signed-off-by: NThomas Hanson <thomas.hanson@linaro.org> Message-id: 1476301853-15774-5-git-send-email-thomas.hanson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Thomas Hanson 提交于
For BR, BLR and RET instructions, if tagged addresses are enabled, the tag field in the address must be cleared out prior to loading the address into the PC. Depending on the current EL, it will be set to either all 0's or all 1's. Signed-off-by: NThomas Hanson <thomas.hanson@linaro.org> Message-id: 1476301853-15774-3-git-send-email-thomas.hanson@linaro.org [PMM: remove unnecessary gen_a64_set_pc_reg() wrapper, rename gen_a64_set_pc_var() to gen_a64_set_pc(), fix stray misindentation] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Thomas Hanson 提交于
When capturing the current CPU state for the TB, extract the TBI0 and TBI1 values from the correct TCR for the current EL and then add them to the TB flags field. Then, at the start of code generation for the block, copy the TBI fields into the DisasContext structure. Signed-off-by: NThomas Hanson <thomas.hanson@linaro.org> Message-id: 1476301853-15774-2-git-send-email-thomas.hanson@linaro.org [PMM: drop useless 'extern' keyword on function prototypes; provide CONFIG_USER_ONLY trivial versions of arm_regime_tbi[01]()] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Vijay Kumar B 提交于
If a name is provided, the same name is assigned to both the I2C controllers. Leaving it NULL, causes names to be automatically assigned with an ID suffix, giving unique names to each controller. This helps us to uniquely identify each controller in the device tree, for example when adding an I2C device. Signed-off-by: NVijay Kumar B. <vijaykumar@zilogic.com> Reviewed-by: NDeepak S. <deepak@zilogic.com> Message-id: 1476351885-8905-1-git-send-email-vijaykumar@zilogic.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Paolo Bonzini 提交于
1) ptimer-test is not a qtest---it runs the ptimer.c code directly in the ptimer-test process 2) ptimer-test has its own stubs file, so there is no need to add more stubs to stubs/vmstate.c Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Reviewed-by: NDmitry Osipenko <digetx@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
This test uses the palmetto platform and the Aspeed SPI controller to test the m25p80 flash module device model. The flash model is defined by the platform (n25q256a) and it would be nice to find way to control it, using a property probably. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1475787271-28794-1-git-send-email-clg@kaod.org Brainstormed-with: Greg Kurz <groug@kaod.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrew Jones 提交于
We should avoid exposing new hardware (through DT and ACPI) on older machine types. This patch keeps 2.7 and older from changing, despite the introduction of ITS support for 2.8. Signed-off-by: NAndrew Jones <drjones@redhat.com> Reviewed-by: NEric Auger <eric.auger@redhat.com> Message-id: 1476117341-32690-3-git-send-email-drjones@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrew Jones 提交于
We can't return early from build_* functions, as build_header is only called at the end. Signed-off-by: NAndrew Jones <drjones@redhat.com> Reviewed-by: NEric Auger <eric.auger@redhat.com> Message-id: 1476117341-32690-2-git-send-email-drjones@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christopher Covington 提交于
Remove unused debugging code to fix native building on aarch64. Without this change, the following -Werr output inhibits make from completing. qemu/hw/intc/arm_gic_kvm.c:38:18: error: debug_gic_kvm defined but not used [-Werror=unused-const-variable=] static const int debug_gic_kvm = 0; ^~~~~~~~~~~~~ cc1: all warnings being treated as errors qemu/rules.mak:60: recipe for target 'hw/intc/arm_gic_kvm.o' failed make[1]: *** [hw/intc/arm_gic_kvm.o] Error 1 Makefile:205: recipe for target 'subdir-aarch64-softmmu' failed Signed-off-by: NChristopher Covington <cov@codeaurora.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20161011163202.19720-1-cov@codeaurora.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Thomas Huth 提交于
The M1 and M2 bits are both used for configuring the endianness of the AHB master interfaces, so the second PL080_CONF_M1 should be PL080_CONF_M2 instead. Buglink: https://bugs.launchpad.net/qemu/+bug/1631773Signed-off-by: NThomas Huth <thuth@redhat.com> Message-id: 1476274451-26567-1-git-send-email-thuth@redhat.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Michael Olbrich 提交于
When kernel and device tree are specified in the QEMU commandline, then this device tree may be modified e.g. to add virtio_mmio devices. With a bootloader e.g. on a flash device these extra devices are not available. With this change, the device tree can be specified at the QEMU commandline. The modified device tree made available to the bootloader with the same mechanism already supported by device trees fully generated by QEMU. Signed-off-by: NMichael Olbrich <m.olbrich@pengutronix.de> Message-id: 1473520054-402-1-git-send-email-m.olbrich@pengutronix.de Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The SMC controller on the Aspeed SoC has a set of registers to configure the mapping of each flash module in the SoC address space. Writing to these registers triggers a remap of the memory region and the spec requires a certain number of checks before doing so. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-7-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The SMC controller on the Aspeed SoC has a set of registers to configure the mapping of each flash module in the SoC address space. These mapping windows are configurable even though no SPI slave is attached to the controller. Also rewrite a bit the comments in the code on this topic. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-6-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The SMC controllers on the Aspeed AST2500 SoC are very similar to the ones found on the AST2400. The differences are on the number of supported flash modules and their default mappings in the SoC address space. The Aspeed AST2500 has one SPI controller for the BMC firmware and two for the host firmware. All controllers have now the same set of registers compatible with the AST2400 FMC controller and the legacy 'SMC' controller is fully gone. We keep the FMC object to act as the BMC SPI controller and add a new SPI controller for the host. We also have to introduce new type names to handle the differences in the flash modules memory mappping. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-5-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The AST2500 SoC has two. Let's prepare ground for the next changes which will add the required definitions for the second host SPI controller. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-4-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
This will ease the definition of the new controllers for the AST2500 SoC and also ease the support of the segment registers, which provide a way to reconfigure the mapping window of each slave. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-3-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The Aspeed SoC has three different types of SMC (Static Memory Controller) controllers: the SMC (legacy), the FMC (the new one) and the SPI for the host PNOR. The FMC and the SPI models are now converging on the AST2500 SoC and the SMC, which was still available on the AST2400 SoC, was removed. The Aspeed SoC does not provide support for the legacy SMC controller. So, let's rename the 'smc' object to 'fmc' to clarify its nature. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-2-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Paolo Bonzini 提交于
The only address space where the GIC devices are added is address_space_memory. There is no need to use a global MemoryListener. This removes the only user of global MemoryListeners. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> [PMM: added missing #include "exec/address-spaces.h"] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1475219846-32609-1-git-send-email-pbonzini@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Rutuja Shah 提交于
This patch allocates memory for txbuf in struct Stream rather than the stack. As a result, the stack frame size is reduced of stream_process_mem2s(). Signed-off-by: NRutuja Shah <rutu.shah.26@gmail.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
This patch does three things: - It adds a list of restrictions and ToDos - It corrects the header --- lines to match the length of the header - It clarifies the force-raw option Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NMarkus Armbruster <armbru@redhat.com> Message-id: e75d1d285cf8f45037c41ebe1bc3f68120f09cb9.1475702918.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Eduardo Habkost 提交于
When explicitly enabling unmigratable flags using "-cpu host" (e.g. "-cpu host,+invtsc"), the requested feature won't be enabled because cpu->migratable is true by default. This is inconsistent with all other CPU models, which don't have the "migratable" option, making "+invtsc" work without the need for extra options. This happens because x86_cpu_filter_features() uses cpu->migratable as an argument for x86_cpu_get_supported_feature_word(). This is not useful because: 2) on "-cpu host" it only makes QEMU disable features that were explicitly enabled in the command-line; 1) on all the other CPU models, cpu->migratable is already false. The fix is to just use 'false' as an argument to x86_cpu_get_supported_feature_word() in x86_cpu_filter_features(). Note that: * This won't change anything for people using using "-cpu host" or "-cpu host,migratable=<on|off>" (with no extra features) because the x86_cpu_get_supported_feature_word() call on the cpu->host_features check uses cpu->migratable as argument. * This won't change anything for any CPU model except "host" because they all have cpu->migratable == false (and only "host" has the "migratable" property that allows it to be changed). * This will only change things for people using "-cpu host,+<feature>", where <feature> is a non-migratable feature. The only existing named non-migratable feature is "invtsc". In other words, this change will only affect people using "-cpu host,+invtsc" (that will now get what they asked for: the invtsc flag will be enabled). All other use cases are unaffected. Reviewed-by: NEric Blake <eblake@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Eduardo Habkost 提交于
Fill the "unavailable-features" field on the x86 implementation of query-cpu-definitions. Cc: Jiri Denemark <jdenemar@redhat.com> Cc: libvir-list@redhat.com Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Eduardo Habkost 提交于
When probing for CPU model information, we need to reuse the code that initializes CPUID fields, but not the remaining side-effects of x86_cpu_realizefn(). Move that code to a separate function that can be reused later. Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Eduardo Habkost 提交于
TYPE_X86_CPU now call cpu_exec_init() on realize, so we don't need to set cannot_destroy_with_object_finalize_yet anymore. Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Radim Krčmář 提交于
Assume that KVM would have returned the same on subsequent runs. Abstract the memoizaiton pattern into macros and call it memorize as adding the r makes it less obscure. Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Radim Krčmář 提交于
Cluster x2APIC cannot work without KVM's x2apic API when the maximal APIC ID is greater than 8 and only KVM's LAPIC can support x2APIC, so we forbid other APICs and also the old KVM case with less than 9, to simplify the code. There is no point in enabling EIM in forbidden APICs, so we keep it enabled only for the KVM APIC; unconditionally, because making the option depend on KVM version would be a maintanance burden. Old QEMUs would enable eim whenever intremap was on, which would trick guests into thinking that they can enable cluster x2APIC even if any interrupt destination would get clamped to 8 bits. Depending on your configuration, QEMU could notice that the destination LAPIC is not present and report it with a very non-obvious: KVM: injection failed, MSI lost (Operation not permitted) Or the guest could say something about unexpected interrupts, because clamping leads to aliasing so interrupts were being delivered to incorrect VCPUs. KVM_X2APIC_API is the feature that allows us to enable EIM for KVM. QEMU 2.7 allowed EIM whenever interrupt remapping was enabled. In order to keep backward compatibility, we again allow guests to misbehave in non-obvious ways, and make it the default for old machine types. A user can enable the buggy mode it with "x-buggy-eim=on". Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NPeter Xu <peterx@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Radim Krčmář 提交于
The default (auto) emulates the current behavior. A user can now control EIM like -device intel-iommu,intremap=on,eim=off Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NPeter Xu <peterx@redhat.com> Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Radim Krčmář 提交于
* there no point in configuring the device if realization is going to fail, so move the check to the beginning, * create a separate function for the check, * use error_setg() instead error_report(). Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NPeter Xu <peterx@redhat.com> Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Radim Krčmář 提交于
The MMIO interface to APIC only allowed 8 bit addresses, which is not enough for 32 bit addresses from EIM remapping. Intel stored upper 24 bits in the high MSI address, so use the same technique. The technique is also used in KVM MSI interface. Other APICs are unlikely to handle those upper bits. Reviewed-by: NPeter Xu <peterx@redhat.com> Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Radim Krčmář 提交于
The MMIO based interface to APIC doesn't work well with MSIs that have upper address bits set (remapped x2APIC MSIs). A specialized interface is a quick and dirty way to avoid the shortcoming. Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NPeter Xu <peterx@redhat.com> Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Radim Krčmář 提交于
Every configuration has only up to one APIC class and we'll be extending the class with a function that can be called without an instanced object, so a direct access to the class is convenient. This patch will break compilation if some code uses apic_get_class() with CONFIG_USER_ONLY. Suggested-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NPeter Xu <peterx@redhat.com> Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Eduardo Habkost 提交于
x86_cpu_filter_features() will be reused by code that shouldn't print any warning. Move the warning code to a new x86_cpu_report_filtered_features() function, and call it from x86_cpu_realizefn(). Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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