- 05 1月, 2014 1 次提交
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由 Peter Maydell 提交于
Update the generic cpreg support code to also handle AArch64: AArch64-visible registers coexist in the same hash table with AArch32-visible ones, with a bit in the hash key distinguishing them. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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- 18 12月, 2013 4 次提交
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由 Peter Maydell 提交于
The information which AArch32 holds in the FPSCR is split for AArch64 into two logically distinct registers, FPSR and FPCR. Since they are carefully arranged to use non-overlapping bits, we leave the underlying state in the same place, and provide accessor functions which just update the appropriate bits via vfp_get_fpscr() and vfp_set_fpscr(). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
The env->pstate field is a little odd since it doesn't strictly speaking represent an architectural register. However it's convenient for QEMU to use it to hold the various PSTATE architectural bits in the same format the architecture specifies for SPSR registers (since this is the same format the kernel uses for signal handlers and the KVM register). Add some structure to how we deal with it: * document what env->pstate is * add some #defines for various bits in it * add helpers for reading/writing it taking account of caching of NZCV, and use them where appropriate * reset it on startup Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-3-git-send-email-peter.maydell@linaro.org Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
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由 Peter Crosthwaite 提交于
Some processors (notably A9 within Highbank) define and use the CP15 configuration base address (CBAR). This is vendor specific so its best implemented as a CPU property (otherwise we would need vendor specific child classes for every ARM implementation). This patch prepares support for converting CBAR reset value to a CPU property by moving the CP registration out of the CPU init fn, as registration will need to happen at realize time to pick up any property updates. The easiest way to do this is via definition of a new ARM_FEATURE to flag the existence of the register. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 9f697ef1e2ee60a3b9ef971a7f3bc3fa6752a9b7.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Ard Biesheuvel 提交于
This adds support for the AESE/AESD/AESMC/AESIMC instructions that are available on some v8 implementations of Aarch32. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1386266078-6976-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 12月, 2013 1 次提交
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由 Peter Maydell 提交于
There are a number of places where it would be convenient for ARM code to have working definitions of KVM constants even in code which is compiled with CONFIG_KVM not set. In this situation we can't simply include the kernel KVM headers (which might conflict with host header definitions or not even compile on the compiler we're using) so we have to redefine equivalent constants. Provide a mechanism for doing this and checking that the values match, and use it for the constants we're currently exposing via an ad-hoc mechanism. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-2-git-send-email-peter.maydell@linaro.org
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- 31 10月, 2013 1 次提交
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由 Nathan Rossi 提交于
Added Vector Base Address remapping on ARM v7. Signed-off-by: NNathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> [PMM: removed spurious mask of value with 1<<31] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 11 9月, 2013 3 次提交
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由 Alexander Graf 提交于
This patch adds all the prerequisites for AArch64 support that didn't fit into split up patches. It extends important bits in the core cpu headers to also take AArch64 mode into account. Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org [PMM: * rearranged tbflags so AArch64? is bit 31 and if it is set then 30..0 are freely available for whatever makes most sense for that mode * added version bump since we change VFP migration state * added a comment about how VFP/Neon register state works * physical address space is 48 bits, not 64 * added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs ] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
Correct a few places that were using uint32_t or a 32 bit only format string to handle something that should be a target_ulong. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-6-git-send-email-peter.maydell@linaro.org [PMM: split out to separate patch; added gen_goto_tb() and gen_set_pc_im() dest params to list of things to change.] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Avoid the undefined behaviour of "1 << 31" by using 1U to make the shift be of an unsigned value rather than shifting into the sign bit of a signed integer. For consistency, we make all the CPSR_* constants unsigned, though the only one which triggers undefined behaviour is CPSR_N. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 1378391908-22137-3-git-send-email-peter.maydell@linaro.org
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- 20 8月, 2013 3 次提交
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由 Peter Maydell 提交于
The ARMv7 architecture specifies a 'generic timer' which is implemented via cp15 registers. Newer kernels will prefer to use this rather than a devboard-level timer. Implement the generic timer for TCG; for KVM we will already use the hardware's virtualized timer for this. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Tested-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1376065080-26661-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Add an ARM_CP_IO flag which an ARMCPRegInfo definition can use to indicate that the register's implementation does I/O and thus its accesses need to be surrounded by gen_io_start()/gen_io_end() in order for icount to work. Most notably, cp registers which implement clocks or timers need this. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Tested-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 1376065080-26661-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Now that ARMCPU is a subclass of DeviceState, we can make the CPU's inbound IRQ and FIQ lines be simply gpio lines, which means we can remove the odd arm_pic shim. We retain the arm_pic_init_cpu() function as a backwards compatibility shim layer so we can convert the board models to get the IRQ and FIQ lines directly from the ARMCPU object one at a time. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1375977856-25046-2-git-send-email-peter.maydell@linaro.org
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- 23 7月, 2013 1 次提交
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由 Andreas Färber 提交于
Where no extra implementation is needed, fall back to CPUClass::set_pc(). Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 15 7月, 2013 1 次提交
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由 Mans Rullgard 提交于
Signed-off-by: NMans Rullgard <mans@mansr.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 7月, 2013 1 次提交
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由 Peter Maydell 提交于
The functions cpu_clone_regs() and cpu_set_tls() are not purely CPU related -- they are specific to the TLS ABI for a a particular OS. Move them into the linux-user/ tree where they belong. target-lm32 had entirely unused implementations, since it has no linux-user target; just drop them. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 26 6月, 2013 3 次提交
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由 Peter Maydell 提交于
Convert the TCG ARM target to using an (index,value) list for migrating coprocessors. The primary benefit of the (index,value) list is for passing state between KVM and QEMU, but it works for TCG-to-TCG migration as well and is a useful self-contained first step. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
For reading and writing register values from the kernel for KVM, we need to provide accessor functions which are guaranteed to succeed and don't impose access checks, mask out unwritable bits, etc. Define new fields raw_readfn and raw_writefn for this purpose; these only need to be provided if there is a readfn or writefn already and it is not suitable. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Relax the "is this a valid ARMCPRegInfo type value?" check to permit "special" cpregs to have flags other than ARM_CP_SPECIAL set. At the moment none of the other flags are relevant for special regs, but the migration related flag we're about to introduce can apply here too. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 19 4月, 2013 1 次提交
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由 Juan Quintela 提交于
Port the ARM CPU save/load code to use VMState. Some state is saved in a slightly different order to simplify things -- for example arrays are saved one after the other rather than 'striped', and we always save all 32 VFP registers even if the CPU happens to only have 16. Use one subsection for each feature. This means that we don't need to bump the version field each time that a new feature gets introduced. Signed-off-by: NJuan Quintela <quintela@redhat.com> [PMM: fixed conflicts, updated to use cpu_class_set_vmsd(), updated with new/removed fields since original patch, changed to use custom VMStateInfo for cpsr rather than presave/postload hooks, corrected subsection names so vmload doesn't fail] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 12 3月, 2013 2 次提交
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由 Andreas Färber 提交于
This removes a global per-target function and thus takes us one step closer to compiling multiple targets into one executable. It will also allow to override the interrupt handling for certain CPU families. Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Andreas Färber 提交于
Both fields are used in VMState, thus need to be moved together. Explicitly zero them on reset since they were located before breakpoints. Pass PowerPCCPU to kvmppc_handle_halt(). Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 05 3月, 2013 1 次提交
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由 Christoffer Dall 提交于
Add basic support for KVM on ARM architecture. Signed-off-by: NChristoffer Dall <cdall@cs.columbia.edu> [PMM: Minor tweaks and code cleanup, switch to ONE_REG] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 16 2月, 2013 1 次提交
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由 Andreas Färber 提交于
Turn arm_cpu_realize() into a QOM realize function, no longer called via cpu.h prototype. To maintain the semantics of cpu_init(), set realized = true explicitly in cpu_arm_init(). Move GDB coprocessor registration, CPU reset and vCPU initialization into the realizefn. Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 19 12月, 2012 2 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 31 10月, 2012 1 次提交
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由 Andreas Färber 提交于
For target-mips also change the return type to bool. Make include paths for cpu-qom.h consistent for alpha and unicore32. Signed-off-by: NAndreas Färber <afaerber@suse.de> [AF: Updated new target-openrisc function accordingly] Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
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- 05 10月, 2012 1 次提交
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由 Peter Maydell 提交于
This macro snuck through code review despite being unused; drop it. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 16 9月, 2012 1 次提交
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由 Blue Swirl 提交于
Convert code load functions and switch to AREG0 free mode. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 8月, 2012 1 次提交
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由 Peter Maydell 提交于
Fix a variety of typos in comments in target-arm files. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>
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- 12 7月, 2012 4 次提交
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由 Peter Maydell 提交于
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extended to 64 bits, with a 64 bit (MRRC/MCRR) access path to read the full width of the register. Add the state fields for the top half and the 64 bit access path. Actual use of the top half of the register will come with the addition of the long-descriptor translation table format support. For the PAR we also need to correct the masking applied for 32 bit writes (there are no bits reserved if LPAE is implemented) and clear the high half when doing a 32 bit result VA-to-PA lookup. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Extend feature flags to 64 bits, as we've just run out of space in the 32 bit integer we were using for them. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Implement the privileged-execute-never (PXN) translation table bit. It is implementation-defined whether this is implemented, so we give it its own ARM_FEATURE_ flag. LPAE requires PXN, so add also an LPAE feature flag and the implication logic, as a placeholder for actually implementing LPAE at a later date. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Make target_phys_addr_t 64 bits for ARM targets, and set TARGET_PHYS_ADDR_SPACE_BITS to 40. This should have no effect for ARM boards where physical addresses really are 32 bits (except perhaps a slight performance hit on 32 bit hosts for system emulation) but allows us to implement the Large Physical Address Extensions for Cortex-A15, which mean 40 bit physical addresses. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 20 6月, 2012 6 次提交
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由 Peter Maydell 提交于
All the uses of ARM_CPUID() to vary behaviour have now been removed, so we can delete the ARM_CPUID_* macros now. The one exception is the TI915T/925T, because of its odd behaviour where the MIDR value can be changed at runtime. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the MPIDR to the new cp15 register scheme. This includes giving it its own feature bit rather than doing a CPUID value check. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 cache ID registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=0 crm={1,2} features registers to the new cp reg framework. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=7 registers to the new scheme. Note that to do this we have to distinguish some registers used on the ARM9 and ARM10 from some which are ARM1176 only. This is because the old code returned a value of 0 but always set the Z flag (by clearing env->ZF, since we store the Z flag in CPUState inverted). This is inconsistent with actual ARM CPU behaviour, which only sets flags for reads to r15 and sets them based on the top bits of the result. However it happened to work for the two common use cases for cp15 crn=7 reads: * On ARM9 and ARM10 the cache clean-and-test operations are typically done with a destination of r15 so that you can do a "loop: mrc ... ; bne loop" to keep cleaning until the cache is finally clean; always setting the Z flag means this loop terminates immediately * on ARM1176 the Cache Dirty Status Register reads as zero if the cache is dirty; returning 0 means this is correctly implemented for QEMU Since the new coprocessor register framework does the right thing of always setting flags based on the returned result for reads to r15, we need to split these up so that we can return (1<<30) for the ARM9/ARM10 registers but 0 for the ARM1176 one. This allows us to remove the nasty hack which always sets Z. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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