Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The bochs vbe interface got a new register a while back, which specifies
the linear framebuffer size in 64k units.  This patch adds support for
the new register to qemu.  With this patch applied vgabios 0.6c works
with qemu.
Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NNaphtali Sprei <nsprei@redhat.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Replaces direct phys_ram_dirty access with wrapper functions to prevent
direct access to the phys_ram_dirty bitmap.
Signed-off-by: NYoshiaki Tamura <tamura.yoshiaki@lab.ntt.co.jp>
Signed-off-by: NOHMURA Kei <ohmura.kei@lab.ntt.co.jp>
Reviewed-by: NAvi Kivity <avi@redhat.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Adds wrapper functions to prevent direct access to the phys_ram_dirty bitmap.
Signed-off-by: NYoshiaki Tamura <tamura.yoshiaki@lab.ntt.co.jp>
Signed-off-by: NOHMURA Kei <ohmura.kei@lab.ntt.co.jp>
Reviewed-by: NAvi Kivity <avi@redhat.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

This patch fixes few resource leaks in the iwmmxt disassemble.
Signed-off-by: NLars Munch <lars@segv.dk>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: Nmalc <av1474@comtv.ru>

> Hello,
>
> d6f4ade2 (disentangle tcg and deadline calculation, 2010-03-10)
> introduces following regression(s):
>
> 100% cpu utilization when QEMU is invoked like:
> qemu -S -s ...
>
> ditto when gdb takes control over the session via gdb-stub
> (i.e. the breakpoint is hit or C-c is pressed inside gdb to
>   interrupt the attached qemu instance)

The bug is that env->stopped is not really as comprehensive as it seems to
be (and cpu_has_work thinks); it is only valid with iothread basically,
and even then it is cleared by reset and it is not set when starting
qemu with -S.
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
Cc: malc <av1474@comtv.ru>
Signed-off-by: Nmalc <av1474@comtv.ru>

Signed-off-by: Nmalc <av1474@comtv.ru>

Signed-off-by: Nmalc <av1474@comtv.ru>

Convert remaining OHCI devices to QDEV interface.
Signed-off-by: NPaul Brook <paul@codesourcery.com>

Only include hw/loader.h from target-arm/helper.c when building for
system emulation.
Signed-off-by: NPaul Brook <paul@codesourcery.com>

Move ARMv7-M PC/SP initialization to the CPU reset routine.  Add a board
reset routine to call this.  Also load values directly from ROM as
images have not been copied yet.

Avoid clearing the NVIC pointer on cpu reset.
Signed-off-by: NPaul Brook <paul@codesourcery.com>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: Nmalc <av1474@comtv.ru>

Historically the qemu tlb "addend" field was used for both RAM and IO accesses,
so needed to be able to hold both host addresses (unsigned long) and guest
physical addresses (target_phys_addr_t).  However since the introduction of
the iotlb field it has only been used for RAM accesses.

This means we can change the type of addend to unsigned long, and remove
associated hacks in the big-endian TCG backends.

We can also remove the host dependence from target_phys_addr_t.
Signed-off-by: NPaul Brook <paul@codesourcery.com>

Only raise an interrupt if the TD has actually completed.
Signed-off-by: NPaul Brook <paul@codesourcery.com>

This reverts commit f1698408.

PCI is always little-endian. Having a user-visible "be" property is just
plain wrong.

Thanks to Alexander Graf for bug report and a good reproducible test
case.
Signed-off-by: Nmalc <av1474@comtv.ru>

PowerPC CPUs have had two ways to read the time base for quite some time now.
They provide it using the mfspr instruction or - if a special bit is set in
that opcode - using mftb. For timekeeping we're currently using mftb.

While trying to get Qemu up and running on an e500v2 system, I stumbled over
the CPU not supporting mftbu. It just throws an illegal instruction trap.

So let's read the SPR values instead. All PPC CPUs should support them anyways.

I tested this patch on an e500v2 system where it makes qemu work and on my 970MP
system with 32-bit user space where everything still works with this patch
applied.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: Nmalc <av1474@comtv.ru>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Timer with zero period (free-run) will never match.

Timer counting starts with tick value of 0x200, not from 0,
so the period must calculated from one tick less than the limit.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

The R2D board does not have a PS/2 port, and only support a keyboard on
the USB bus.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

After commit 702f3e0f, the params is
nerver NULL. It should check *params instead of params to determine
whether the params is empty.
Signed-off-by: NTeLeMan <geleman@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

u_int64_t raises compiler error messages:

  CC    libhw32/virtio.o
/qemu/ar7/hw/virtio.c: In function ‘virtio_queue_get_avail_size’:
/qemu/ar7/hw/virtio.c:776: error: ‘u_int64_t’ undeclared (first use in this function)
/qemu/ar7/hw/virtio.c:776: error: (Each undeclared identifier is reported only once
/qemu/ar7/hw/virtio.c:776: error: for each function it appears in.)

Replacing u_int64_t by uint64_t helps.

Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Commit c05c7a73
breaks cross compilation for mips (and other
compilations without CONFIG_INOTIFY1):

make[1]: Entering directory `/qemu/bin/mips'
  CC    i386-linux-user/syscall.o
cc1: warnings being treated as errors
/qemu/linux-user/syscall.c: In function ‘do_syscall’:
/qemu/linux-user/syscall.c:7067: error: implicit declaration of function ‘sys_inotify_init1’

Cc: Riku Voipio <riku.voipio@nokia.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The KVM kernel module on S390 refuses to create a VM when the switch_amode
kernel parameter is not used.

Since that is not exactly obvious, let's give the user a nice warning.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

We don't implement any virtual memory in the S390 target so far, so let's
add a stub for this now mandatory function.

Fixes building of S390 target.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

A few words about design choices:
* On IA64, instructions should be grouped by bundle, and dependencies
  between instructions declared. A first version of this code tried to
  schedule instructions automatically, but was very complex and too
  invasive for the current common TCG code (ops not ending at
  instruction boundaries, code retranslation breaking already generated
  code, etc.)  It was also not very efficient, as dependencies between
  TCG ops is not available.
  Instead the option taken by the current implementation does not try
  to fill the bundle by scheduling instructions, but by providing ops
  not available as an ia64 instruction, and by offering 22-bit constant
  loading for most of the instructions. With both options the bundle are
  filled at approximately the same level.

* Up to 128 registers can be affected to a function on IA64, but TCG
  limits this number to 64, which is actually more than enough. The
  register affectation is the following:
  - r0: used to map a constant argument with value 0
  - r1: global pointer
  - r2, r3: internal use
  - r4 to r6: not used to avoid saving them
  - r7: env structure
  - r8 to r11: free for TCG (call clobbered)
  - r12: stack pointer
  - r13: thread pointer
  - r14 to r31: free for TCG (call clobbered)
  - r32: reserved (return address)
  - r33: reserved (PFS)
  - r33 to r63: free for TCG

* The IA64 architecture has only 64-bit registers and no 32-bit
  instructions (the only exception being cmp4). Therefore 64-bit
  registers and instructions are used for 32-bit ops. The adopted
  strategy is the same as the ABI, that is the higher 32 bits are
  undefined. Most ops (and, or, add, shl, etc.) can directly use
  the 64-bit registers, while some others have to sign-extend (sar,
  div, etc.) or zero-extend (shr, divu, etc.) the register first.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

On ia64, the default memory alignement is not enough for a code
alignement. To fix that, force static_code_gen_buffer alignment
to CODE_GEN_ALIGN.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Taken from binutils SVN, using last GPLv2 version.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

When the host page size is bigger that the target one, unprotecting a
page should:
- mark all the target pages corresponding to the host page as writable
- invalidate all tb corresponding to the host page (and not the target
  page)
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

ia64 has some strangenesses that need to be workaround:
- it has a __clone2() syscall instead of the using clone() one, with
  different arguments, and which is not declared in the usual headers.
- ucontext.uc_sigmask is declared with type long int, while it is
  actually of type sigset_t.
- uc_mcontext, uc_sigmask, uc_stack, uc_link are declared using #define,
  which clashes with the target_ucontext fields. Change their names to
  tuc_*, as already done for some target architectures.