- 04 7月, 2016 22 次提交
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由 Peter Crosthwaite 提交于
Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 85f39c9a13569b1113dacac3b952b0af54fc1260.1467053537.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Add a minimal model for the devcfg device which is part of Zynq. This model supports DMA capabilities and interrupt generation. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 83df49d8fa2d203a421ca71620809e4b04754e65.1467053537.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add a helper that will scan a static RegisterAccessInfo Array and populate a container MemoryRegion with registers as defined. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 347b810b2799e413c98d5bbeca97bcb1557946c3.1467053537.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
QOMify registers as a child of TYPE_DEVICE. This allows registers to define GPIOs. Define an init helper that will do QOM initialisation. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NKONRAD Frederic <fred.konrad@greensocs.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 2545f71db26bf5586ca0c08a3e3cf1b217450552.1467053537.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Define some macros that can be used for defining registers and fields. The REG32 macro will define A_FOO, for the byte address of a register as well as R_FOO for the uint32_t[] register number (A_FOO / 4). The FIELD macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and FOO_BAR_LENGTH constants for field BAR in register FOO. Finally, there are some shorthand helpers for extracting/depositing fields from registers based on these naming schemes. Usage can greatly reduce the verbosity of device code. The deposit and extract macros (eg FIELD_EX32, FIELD_DP32 etc.) can be used to generate extract and deposits without any repetition of the name stems. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: bbd87a3c03b1f173b1ed73a6d502c0196c18a72f.1467053537.git.alistair.francis@xilinx.com [ EI Changes: * Add Deposit macros ] Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Add memory io handlers that glue the register API to the memory API. Just translation functions at this stage. Although it does allow for devices to be created without all-in-one mmio r/w handlers. This patch also adds the RegisterInfoArray struct, which allows all of the individual RegisterInfo structs to be grouped into a single memory region. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: f7704d8ac6ac0f469ed35401f8151a38bd01468b.1467053537.git.alistair.francis@xilinx.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
This API provides some encapsulation of registers and factors out some common functionality to common code. Bits of device state (usually MMIO registers) often have all sorts of access restrictions and semantics associated with them. This API allows you to define what those restrictions are on a bit-by-bit basis. Helper functions are then used to access the register which observe the semantics defined by the RegisterAccessInfo struct. Some features: Bits can be marked as read_only (ro field) Bits can be marked as write-1-clear (w1c field) Bits can be marked as reserved (rsvd field) Reset values can be defined (reset) Bits can be marked clear on read (cor) Pre and post action callbacks can be added to read and write ops Verbose debugging info can be enabled/disabled Useful for defining device register spaces in a data driven way. Cuts down on a lot of the verbosity and repetition in the switch-case blocks in the standard foo_mmio_read/write functions. Also useful for automated generation of device models from hardware design sources. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 40d62c7e1bf6e63bb4193ec46b15092a7d981e59.1467053537.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Add a macro that creates a 64bit value which has length number of ones shifted across by the value of shift. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 9773244aa1c8c26b8b82cb261d8f5dd4b7b9fcf9.1467053537.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Ard Biesheuvel 提交于
Since QEMU performs cacheable accesses to guest memory when doing DMA as part of the implementation of emulated PCI devices, guest drivers should use cacheable accesses as well when running under KVM. Since this essentially means that emulated PCI devices are DMA coherent, set the 'dma-coherent' DT property on the PCIe host controller DT node. This brings the DT description into line with the ACPI description, which already marks the PCI bridge as cache coherent (see commit bc64b96c). Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1467134090-5099-1-git-send-email-ard.biesheuvel@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrey Smirnov 提交于
Starting QEMU with -S results in current_cpu containing its initial value of NULL. It is however possible to connect to such QEMU instance and query various CPU registers, one example being CPUID, and doing that results in QEMU segfaulting. Using qemu_get_cpu(0) seem reasonable enough given that ARMv7M architecture is a single core architecture. Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
It doesn't make sense to pass a NULL ops argument to memory_region_init_rom_device(), because the effect will be that if the guest tries to write to the memory region then QEMU will segfault. Catch the bug earlier by sanity checking the arguments to this function, and remove the misleading documentation that suggests that passing NULL might be sensible. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1467122287-24974-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The imx boards were all incorrectly creating ROMs using memory_region_init_rom_device() with a NULL ops pointer. This will cause QEMU to abort if the guest tries to write to the ROM. Switch to the new memory_region_init_rom() instead. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1467122287-24974-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Provide a new helper function memory_region_init_rom() for memory regions which are read-only (and unlike those created by memory_region_init_rom_device() don't have special behaviour for writes). This has the same behaviour as calling memory_region_init_ram() and then memory_region_set_readonly() (which is what we do today in boards with pure ROMs) but is a more easily discoverable API for the purpose. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1467122287-24974-2-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
SYS_HEAPINFO is one of the few semihosting calls which has to write values back into a parameter block in memory. When we added support for 64-bit semihosting we updated the code which reads from the parameter block to read 64-bit words but forgot to change the code that writes back into the block. Update it to treat the block as a set of words of the appropriate width for the guest. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1466783381-29506-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The fields in the TaskState heap_base, heap_limit and stack_base are all guest addresses (representing the locations of the heap and stack for the guest binary), so they should be abi_ulong rather than uint32_t. (This only in practice affects ARM AArch64 since all the other semihosting implementations are 32-bit.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1466783381-29506-2-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
slirp updates # gpg: Signature made Sun 03 Jul 2016 23:03:04 BST # gpg: using RSA key 0xE3E51CE8FB6B2F1D # gpg: Good signature from "Samuel Thibault <samuel.thibault@gnu.org>" # gpg: aka "Samuel Thibault <sthibault@debian.org>" # gpg: aka "Samuel Thibault <samuel.thibault@inria.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@labri.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@ens-lyon.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 900C B024 B679 31D4 0F82 304B D017 8C76 7D06 9EE6 # Subkey fingerprint: F632 74CD C630 0873 CB3D 29D9 E3E5 1CE8 FB6B 2F1D * remotes/thibault/tags/samuel-thibault: slirp: Add support for stateless DHCPv6 slirp: Remove superfluous memset() calls from the TFTP code slirp: Add RDNSS advertisement slirp: Support link-local DNS addresses slirp: Add dns6 resolution slirp: Split get_dns_addr Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Thomas Huth 提交于
Provide basic support for stateless DHCPv6 (see RFC 3736) so that guests can also automatically boot via IPv6 with SLIRP (for IPv6 network booting, see RFC 5970 for details). Tested with: qemu-system-ppc64 -nographic -vga none -boot n -net nic \ -net user,ipv6=yes,ipv4=no,tftp=/path/to/tftp,bootfile=ppc64.img Signed-off-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NSamuel Thibault <samuel.thibault@ens-lyon.org>
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由 Thomas Huth 提交于
Commit fad7fb9c ("Add IPv6 support to the TFTP code") refactored some common code for preparing the mbuf into a new function called tftp_prep_mbuf_data(). One part of this common code is to do a "memset(m->m_data, 0, m->m_size);" for the related buffer first. However, at two spots, the memset() was not removed from the calling function, so it currently done twice in these code paths. Thus let's delete these superfluous memsets in the calling functions now. Signed-off-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NSamuel Thibault <samuel.thibault@ens-lyon.org>
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由 Samuel Thibault 提交于
This adds the RDNSS option to IPv6 router advertisements, so that the guest can autoconfigure the DNS server address. Signed-off-by: NSamuel Thibault <samuel.thibault@ens-lyon.org> Reviewed-by: NThomas Huth <thuth@redhat.com> --- Changes since last submission: - Disable on windows, until we have support for it
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由 Samuel Thibault 提交于
They look like fe80::%eth0 Signed-off-by: NSamuel Thibault <samuel.thibault@ens-lyon.org> Reviewed-by: NThomas Huth <thuth@redhat.com> --- Changes since last submission: - fix windows build
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由 Samuel Thibault 提交于
This makes get_dns_addr address family-agnostic, thus allowing to add the IPv6 case. Signed-off-by: NSamuel Thibault <samuel.thibault@ens-lyon.org> Reviewed-by: NThomas Huth <thuth@redhat.com>
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由 Samuel Thibault 提交于
Separate get_dns_addr into get_dns_addr_cached and get_dns_addr_resolv_conf to make conversion to IPv6 easier. Signed-off-by: NSamuel Thibault <samuel.thibault@ens-lyon.org> Reviewed-by: NThomas Huth <thuth@redhat.com>
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- 02 7月, 2016 1 次提交
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由 Peter Maydell 提交于
Only trivial fixes. # gpg: Signature made Fri 01 Jul 2016 13:39:06 BST # gpg: using DSA key 0x02FC3AEB0101DBC2 # gpg: Good signature from "Greg Kurz <gkurz@fr.ibm.com>" # gpg: aka "Greg Kurz <groug@free.fr>" # gpg: aka "Greg Kurz <gkurz@linux.vnet.ibm.com>" # gpg: aka "Gregory Kurz (Groug) <groug@free.fr>" # gpg: aka "Gregory Kurz (Cimai Technology) <gkurz@cimai.com>" # gpg: aka "Gregory Kurz (Meiosys Technology) <gkurz@meiosys.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2BD4 3B44 535E C0A7 9894 DBA2 02FC 3AEB 0101 DBC2 * remotes/gkurz/tags/for-upstream: 9p: synth: drop v9fs_ prefix 9p: don't include <sys/uio.h> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 01 7月, 2016 17 次提交
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由 Alexander Shopov 提交于
Signed-off-by: NAlexander Shopov <ash@kambanaria.org> Message-id: 20160626105922.40590-2-ash@kambanaria.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Greg Kurz 提交于
To have shorter lines and be consistent with other fs devices. Acked-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NGreg Kurz <groug@kaod.org>
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由 Greg Kurz 提交于
The <sys/uio.h> system header doesn't exist on all host platforms. Code should include "qemu/osdep.h" instead to avoid build breaks on plafforms that don't define CONFIG_IOVEC (like win32, if it is to support 9p one day). Acked-by: NCédric Le Goater <clg@kaod.org> Acked-by: NMichael Fritscher <michael@fritscher.net> Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com>
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由 Peter Maydell 提交于
ppc patch queue 2016-07-01 Here's the current ppc patch queue. This is a fairly large batch, containing: * A number of further preliminary patches towards full hypervisor mode emulation * Some further fixes / cleanups for the recently merged device_add based CPU hotplug * Preliminary patches towards supporting a native (rather than paravirtualized) XICS device. This will be needed to emulate a physical Power machine, including hypervisor capabilities * Assorted bug fixes # gpg: Signature made Fri 01 Jul 2016 06:56:35 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.7-20160701: (23 commits) qmp: fix spapr example of query-hotpluggable-cpus spapr: drop duplicate variable in spapr_core_release() spapr: do proper error propagation in spapr_cpu_core_realize_child() spapr: drop reference on child object during core realization spapr: Restore support for 970MP and POWER8NVL CPU cores target-ppc: gen_pause for instructions: yield, mdoio, mdoom, miso ppc/xics: Replace "icp" with "xics" in most places ppc/xics: Implement H_IPOLL using an accessor ppc/xics: Move SPAPR specific code to a separate file ppc/xics: Rename existing xics to xics_spapr ppc: Fix 64K pages support in full emulation target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb spapr: Restore support for older PowerPC CPU cores spapr: fix write-past-end-of-array error in cpu core device init code hw/ppc/spapr: Add some missing hcall function set strings ppc: Print HSRR0/HSRR1 in "info registers" ppc: LPCR is a HV resource ppc: Initial HDEC support ppc: Enforce setting MSR:EE,IR and DR when MSR:PR is set ppc: Fix conditions for delivering external interrupts to a guest ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
VFIO updates 2016-06-30 - Fix VGA quirks (stable 2.6) (Alex Williamson) - Registering PCIe extended capabilities (Chen Fan) - Hide read-only SR-IOV capability from VM (Alex Williamson) - MemoryRegionIOMMUOps.notify_started/stopped (Alexey Kardashevskiy) - hw_error on intel_iommu notify_started (Alex Williamson) # gpg: Signature made Thu 30 Jun 2016 20:45:55 BST # gpg: using RSA key 0x239B9B6E3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-update-20160630.0: intel_iommu: Throw hw_error on notify_started memory: Add MemoryRegionIOMMUOps.notify_started/stopped callbacks vfio/pci: Hide SR-IOV capability vfio: add pcie extended capability support vfio/pci: Fix VGA quirks Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
QAPI patches 2016-06-30 # gpg: Signature made Thu 30 Jun 2016 14:29:43 BST # gpg: using RSA key 0x3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2016-06-30: qapi: Fix memleak in string visitors on int lists qapi: Simplify use of range.h range: Create range.c for code that should not be inline qapi: Fix crash on missing alternate member of QAPI struct checkpatch: There is no qemu_strtod() qobject: Correct JSON lexer grammar comments json-streamer: Don't leak tokens on incomplete parse Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Igor Mammedov 提交于
27393c33 qapi: keep names in 'CpuInstanceProperties' in sync with struct CPUCore added -id suffix to property names but forgot to fix example in qmp-commands.hx Fix example to have 'core-id' instead of 'core' to match current code Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NPeter Krempa <pkrempa@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
Signed-off-by: NGreg Kurz <groug@kaod.org> Reviewed-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
This patch changes spapr_cpu_core_realize_child() to have a local error pointer and use error_propagate() as it is supposed to be done. Signed-off-by: NGreg Kurz <groug@kaod.org> Reviewed-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
When a core is being realized, we create a child object for each thread of the core. The child is first initialized with object_initialize() which sets its ref count to 1, and then added to the core with object_property_add_child() which bumps the ref count to 2. When the core gets released, object_unparent() decreases the ref count to 1, and we g_free() the object: we hence loose the reference on an unfinalized object. This is likely to cause random crashes. Let's drop the extra reference as soon as we don't need it, after the thread is added to the core. Signed-off-by: NGreg Kurz <groug@kaod.org> Reviewed-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Bharata B Rao 提交于
Introduction of core based CPU hotplug for PowerPC sPAPR didn't add support for 970MP and POWER8NVL based core types. Add support for the same. While we are here, add support for explicit specification of POWER5+_v2.1 core type. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Aaron Larson 提交于
Call gen_pause for all "or rx,rx,rx" encodings other nop. This provides a reasonable implementation for yield, and a better approximation for mdoio, mdoom, and miso. The choice to pause for all encodings !=0 leverages the PowerISA admonition that the reserved encodings might change program priority, providing a slight "future proofing". Signed-off-by: NAaron Larson <alarson@ddci.com> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
The "ICP" is a different object than the "XICS". For historical reasons, we have a number of places where we name a variable "icp" while it contains a XICSState pointer. There *is* an ICPState structure too so this makes the code really confusing. This is a mechanical replacement of all those instances to use the name "xics" instead. There should be no functional change. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> [spapr_cpu_init has been moved to spapr_cpu_core.c, change there] Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
None of the other presenter functions directly mucks with the internal state, so don't do it there either. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
Leave the core ICP/ICS logic in xics.c and move the top level class wrapper, hypercall and RTAS handlers to xics_spapr.c Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> [add cpu.h in xics_spapr.c, move set_nr_irqs and set_nr_servers to xics_spapr.c] Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
The common class doesn't change, the KVM one is sPAPR specific. Rename variables and functions to xics_spapr. Retain the type name as "xics" to preserve migration for existing sPAPR guests. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Benjamin Herrenschmidt 提交于
We were always advertising only 4K & 16M. Additionally the code wasn't properly matching the page size with the PTE content, which meant we could potentially hit an incorrect PTE if the guest used multiple sizes. Finally, honor the CPU capabilities when decoding the size from the SLB so we don't try to use 64K pages on 970. This still doesn't add support for MPSS (Multiple Page Sizes per Segment) Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors commits 61a36c9b and 1114e712 reworked the hpte code doing insertion/removal in hw/ppc/spapr_hcall.c. The hunks modifying these areas were removed. ] Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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