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  1. 27 6月, 2011 3 次提交
  3. 13 3月, 2011 1 次提交
  5. 03 7月, 2010 1 次提交
  7. 16 5月, 2010 1 次提交
  9. 07 5月, 2010 1 次提交
  11. 20 1月, 2010 1 次提交
  13. 09 1月, 2010 1 次提交
  15. 12 7月, 2009 1 次提交
    • I
      sparc64: trap handling corrections · 5210977a
      由 Igor Kovalenko 提交于 
      On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
> On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
>> Good trap handling is required to process interrupts.
>>  This patch fixes the following:
>>
>>  - sparc64 has no wim register
>>  - sparc64 has no psret register, use IE bit of pstate
>>   extract IE checking code to cpu_interrupts_enabled
>>  - alternate globals are not available if cpu has GL feature
>>   in this case bit AG of pstate is constant zero
>>  - write to pstate must actually write pstate
>>   even if cpu has GL feature
>>
>>  Also timer interrupt is handled using do_interrupt.
>
> A bit too much for one patch. Please also remove the code instead of
> commenting out.

I now excluded timer interrupt related part.
To my mind other changes are essentially tied together.

> PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32.

Fixed, please find attached the updated version.

--
Kind regards,
Igor V. Kovalenko
      5210977a
  17. 25 4月, 2009 1 次提交
  19. 01 12月, 2008 1 次提交
  21. 04 10月, 2008 1 次提交
  23. 20 9月, 2008 1 次提交
  25. 11 9月, 2008 1 次提交
  27. 30 8月, 2008 2 次提交
  29. 30 5月, 2008 1 次提交
  31. 28 5月, 2008 1 次提交
  33. 13 5月, 2008 1 次提交
  35. 10 5月, 2008 4 次提交
  37. 04 5月, 2008 1 次提交
  39. 22 3月, 2008 1 次提交
  41. 07 3月, 2008 1 次提交
  43. 05 3月, 2008 1 次提交
  45. 24 2月, 2008 1 次提交
  47. 29 11月, 2007 1 次提交
  49. 26 11月, 2007 1 次提交
  51. 14 10月, 2007 1 次提交
    • J
      Replace is_user variable with mmu_idx in softmmu core, · 6ebbf390
      由 j_mayer 提交于 
        allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
      6ebbf390
  53. 01 10月, 2007 1 次提交
  55. 22 9月, 2007 1 次提交
  57. 04 6月, 2007 1 次提交
  59. 07 4月, 2007 1 次提交
  61. 19 3月, 2007 1 次提交
  63. 02 2月, 2007 1 次提交
  65. 31 10月, 2005 2 次提交