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  1. 13 5月, 2014 1 次提交
  3. 08 4月, 2014 1 次提交
    • A
      PPC: Clean up DECR implementation · e81a982a
      由 Alexander Graf 提交于 
      There are 3 different variants of the decrementor for BookE and BookS.

The BookE variant sets TSR[DIS] to 1 when the DEC value becomes 1 or 0. TSR[DIS]
is then the indicator whether the decrementor interrupt line is asserted or not.

The old BookS variant treats DEC as an edge interrupt that gets triggered when
the DEC value's top bit turns 1 from 0.

The new BookS variant maintains the assertion bit inside DEC itself. Whenever
the DEC value becomes negative (top bit set) the DEC interrupt line is asserted.

So far we implemented mostly the old BookS variant. Let's do them all properly.

This fixes booting pseries ppc64 guest images in TCG mode for me.
Signed-off-by: NAlexander Graf <agraf@suse.de>
      e81a982a
  5. 20 3月, 2014 2 次提交
  7. 14 3月, 2014 3 次提交
  9. 05 3月, 2014 16 次提交
  11. 20 12月, 2013 2 次提交
  13. 26 10月, 2013 1 次提交
  15. 02 9月, 2013 1 次提交
  17. 29 7月, 2013 1 次提交
  19. 23 7月, 2013 1 次提交
  21. 10 7月, 2013 1 次提交
  23. 01 7月, 2013 1 次提交
  25. 06 5月, 2013 1 次提交
    • A
      PPC: Add MMU type for 2.06 with AMR but no TB pages · 126a7930
      由 Alexander Graf 提交于 
      When running -cpu on a POWER7 system with PR KVM, we mask out the 1TB
MMU capability from the MMU type mask, but not the AMR bit.

This leads to us having a new MMU type that we don't check for in our
MMU management functions.

Add the new type, so that we don't have to worry about breakage there.
We're not going to use the TCG MMU management in that case anyway.

The long term fix for this will be to move all these MMU management
functions to class callbacks.
Signed-off-by: NAlexander Graf <agraf@suse.de>
      126a7930
  27. 27 4月, 2013 3 次提交
  29. 22 3月, 2013 5 次提交
    • D
      target-ppc: Move ppc tlb_fill implementation into mmu_helper.c · eb20c1c6
      由 David Gibson 提交于 
      For softmmu builds the interface from the generic code to the target
specific MMU implementation is through the tlb_fill() function.  For ppc
this is currently in mem_helper.c, whereas it would make more sense in
mmu_helper.c.  This patch moves it, which also allows
cpu_ppc_handle_mmu_fault() to become a local function in mmu_helper.c
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      eb20c1c6
    • D
      target-ppc: Split user only code out of mmu_helper.c · cc8eae8a
      由 David Gibson 提交于 
      mmu_helper.c is, for obvious reasons, almost entirely concerned with
softmmu builds of qemu.  However, it does contain one stub function which
is used when CONFIG_USER_ONLY=y - the user only versoin of
cpu_ppc_handle_mmu_fault, which always triggers an exception.  The entire
rest of the file is surrounded by #if !defined(CONFIG_USER_ONLY).

We clean this up by moving the user only stub into its own new file,
removing the ifdefs and building mmu_helper.c only when CONFIG_SOFTMMU
is set.  This also lets us remove the #define of cpu_handle_mmu_fault to
cpu_ppc_handle_mmu_fault - that name is only used from generic code for
user only - so we just name our split user version by the generic name.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      cc8eae8a
    • D
      mmu-hash64: Implement Virtual Page Class Key Protection · f80872e2
      由 David Gibson 提交于 
      Version 2.06 of the Power architecture describes an additional page
protection mechanism.  Each virtual page has a "class" (0-31) recorded in
the PTE.  The AMR register contains bits which can prohibit reads and/or
writes on a class by class basis.  Interestingly, the AMR is userspace
readable and writable, however user mode writes are masked by the contents
of the UAMOR which is privileged.

This patch implements this protection mechanism, along with the AMR and
UAMOR SPRs.  The architecture also specifies a hypervisor-privileged AMOR
register which masks user and supervisor writes to the AMR and UAMOR.  We
leave this out for now, since we don't at present model hypervisor mode
correctly in any case.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
[agraf: fix 32-bit hosts]
Signed-off-by: NAlexander Graf <agraf@suse.de>
      f80872e2
    • D
      mmu-hash*: Add header file for definitions · d5aea6f3
      由 David Gibson 提交于 
      Currently cpu.h contains a number of definitions relating to the 64-bit
hash MMU.  Some are used in the MMU emulation code, but some are only used
in the spapr MMU management hcall implementations.

This patch moves these definitions (except for a few that are needed
more widely) into mmu-hash64.h header, shared between the MMU emulation
code and the spapr hcall code.  The MMU emulation code is also updated to
actually use a number of those definitions in place of hard coded
constants.

Similarly, we add new analogous definitions to mmu-hash32.h and use those
in place of many hard-coded constants in mmu-hash32.c
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
[agraf: fix 32-bit hosts]
Signed-off-by: NAlexander Graf <agraf@suse.de>
      d5aea6f3
    • D
      target-ppc: mmu_ctx_t should not be a global type · 5dc68eb0
      由 David Gibson 提交于 
      mmu_ctx_t is currently defined in cpu.h.  However it is used for temporary
information relating to mmu translation, and is only used in mmu_helper.c
and (now) mmu-hash{32,64}.c.  Furthermore it contains information which
should be specific to particular MMU types.  Therefore, move its definition
to mmu_helper.c.  mmu-hash{32,64}.c are converted to use new data types
private to the relevant MMUs (identical to mmu_ctx_t for now, but that will
change in future patches).
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      5dc68eb0