- 24 9月, 2015 1 次提交
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由 Pavel Fedin 提交于
Add gic_version to VirtMachineState, set it to value of the option and pass it around where necessary. Instantiate devices and fdt nodes according to the choice. max_cpus for virt machine increased to 123 (calculated from redistributor space available in the memory map). GICv2 compatibility check happens inside arm_gic_common_realize(). ITS region is added to the memory map too, however currently it not used, just reserved. Signed-off-by: NPavel Fedin <p.fedin@samsung.com> Tested-by: NAshok kumar <ashoks@broadcom.com> [PMM: Added missing cpu_to_le* calls, thanks to Shannon Zhao] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 19 9月, 2015 2 次提交
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由 Eduardo Habkost 提交于
Now all TYPE_MACHINE subclasses use MACHINE_TYPE_NAME to generate the class name. So instead of requiring each subclass to set MachineClass::name manually, we can now set it automatically at the TYPE_MACHINE class_base_init() function. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NMarcel Apfelbaum <marcel@redhat.com> [AF/ehabkost: Updated for s390-ccw machines] [AF: Cleanup of intermediate virt and vexpress name handling] Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Eduardo Habkost 提交于
Machine class names should use the "-machine" suffix to allow class-name-based machine class lookup to work. Rename the arm virt machine class using the MACHINE_TYPE_NAME macro. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 09 9月, 2015 2 次提交
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由 Peter Maydell 提交于
If we're creating a board with support for TrustZone, then enable it on the GIC model as well as on the CPUs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1441383782-24378-7-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Switch the default for the 'virt' board to not providing TrustZone support in either the CPU or the GIC. This is primarily for the benefit of UEFI, which currently assumes there is no TrustZone support, and does not set the GIC up correctly if it is TZ-aware. It also means the board is consistent about its behaviour whether we're using KVM or TCG (KVM never has TrustZone support). If TrustZone support is required (for instance for running test suites or TZ-aware firmware) it can be enabled with the "-machine secure=on" command line option. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1441383782-24378-6-git-send-email-peter.maydell@linaro.org
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- 07 9月, 2015 3 次提交
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由 Pavel Fedin 提交于
At least with KVM, currently there's no reason why QEMU would not be capable of handling Aff3 != 0. This commit fixes up FDT creation in such a case. Signed-off-by: NPavel Fedin <p.fedin@samsung.com> Message-id: eef5a86e6d9a313780dbc23b35fcb65df42a3e9e.1441366248.git.p.fedin@samsung.com [PMM: folded two overlong lines] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Pavel Fedin 提交于
This large region is necessary for some devices like ivshmem and video cards 32-bit kernels can be built without LPAE support. In this case such a kernel will not be able to use PCI controller which has windows in high addresses. In order to work around the problem, "highmem" option is introduced. It defaults to on on, but can be manually set to off in order to be able to run those old 32-bit guests. Signed-off-by: NPavel Fedin <p.fedin@samsung.com> Reviewed-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org> [PMM: Added missing ULL suffixes and a comment to the a15memmap[] entry] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Wei Huang 提交于
This patch generates smbios tables for ARM mach-virt. Also add CONFIG_SMBIOS=y for ARM default config. Acked-by: NGabriel Somlo <somlo@cmu.edu> Tested-by: NGabriel Somlo <somlo@cmu.edu> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org> Tested-by: NLeif Lindholm <leif.lindholm@linaro.org> Signed-off-by: NWei Huang <wei@redhat.com> Message-id: 1440615870-9518-3-git-send-email-wei@redhat.com [PMM: Added missing braces around an if().] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 13 8月, 2015 4 次提交
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由 Peter Maydell 提交于
Wire up the secure timer interrupt. Since we've defined that the plain old physical timer is the NS timer, we can drop the now-out-of-date comment about QEMU not having TZ. Use a data-driven loop to wire up the timer interrupts, since we now have four of them and the code is the same for each. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1437047249-2357-4-git-send-email-peter.maydell@linaro.org Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Pavel Fedin 提交于
This small inline returns correct GIC class name depending on whether we use KVM acceleration or not. Avoids duplicating the condition everywhere. Signed-off-by: NPavel Fedin <p.fedin@samsung.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 4f26901be9b844b563673ce3ad08eeedbb7a7132.1438758065.git.p.fedin@samsung.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1436791864-4582-8-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
Replace magic constants with macros from hw/arm/virt.h and hw/intc/arm_gic_common.h. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1436791864-4582-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 26 6月, 2015 1 次提交
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由 Peter Maydell 提交于
Now we have virtio-pci, we can make the virt board's default block device type be IF_VIRTIO. This allows users to use simplified command lines that don't have to explicitly create virtio-pci-blk devices; the -hda &c very short options now also work. This means we also need to set no_cdrom to avoid getting a default cdrom device -- this is needed because the virtio-blk device will fail if it is connected to a block backend with no media, which is what the default cdrom device typically is. Providing a cdrom with media via -cdrom will succeed, but silently create a device with non-removable medium. this is probably not really what the user wants, but is the best we can do now. Note that this change means that some command lines which used to work (by accident) will stop working. Where a drive was connected manually to a device but without 'if=none' being specified, we used to treat this as an IDE drive, which we would then not autoplug because the board doesn't support IDE. Now we will treat it as a virtio disk and autoplug it, which means the attempt to use the drive manually will fail: qemu-system-arm: -drive file=img.qcow2,id=foo: Drive 'foo' is already in use because it has been automatically connected to another device (did you need 'if=none' in the drive options?) The command line will have to be changed to include 'if=none', as the error message suggests. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com> Message-id: 1435068107-12594-4-git-send-email-peter.maydell@linaro.org
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- 19 6月, 2015 1 次提交
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由 Eric Auger 提交于
This patch allows the instantiation of the vfio-calxeda-xgmac device from the QEMU command line (-device vfio-calxeda-xgmac,host="<device>"). A specialized device tree node is created for the guest, containing compat, dma-coherent, reg and interrupts properties. Signed-off-by: NEric Auger <eric.auger@linaro.org> Acked-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1434455898-17895-1-git-send-email-eric.auger@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 16 6月, 2015 2 次提交
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由 Pavel Fedin 提交于
When we're using KVM, the kernel's internal idea of the MPIDR affinity fields must match the values we tell it for the guest vcpu cluster configuration in the device tree. Since at the moment the kernel doesn't support letting userspace tell it the correct affinity fields to use, we must read the kernel's view and reflect that back in the device tree. Signed-off-by: NShlomo Pongratz <shlomo.pongratz@huawei.com> Signed-off-by: NPavel Fedin <p.fedin@samsung.com> Message-id: 02f601d0a1e6$90c7d630$b2578290$@samsung.com [PMM: Use a local #define rather than a global variable for the TCG ARM_CPUS_PER_CLUSTER setting. Tweak a comment. Update the commit message.] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Add cortex-a53 cpu support in machine virt, so it can be used for TCG and KVM. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1433207452-4512-3-git-send-email-shannon.zhao@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 05 6月, 2015 1 次提交
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由 Paolo Bonzini 提交于
Make this consistent with the secure property, added in the next patch. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 02 6月, 2015 5 次提交
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由 Eric Auger 提交于
Re-indent in a15memmap after VIRT_PLATFORM_BUS introduction Signed-off-by: NEric Auger <eric.auger@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1433244554-12898-5-git-send-email-eric.auger@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Eric Auger 提交于
Allows sysbus devices to be instantiated from command line by using -device option. Machvirt creates a platform bus at init. The dynamic sysbus devices are attached to this platform bus device. The platform bus device registers a machine init done notifier whose role will be to bind the dynamic sysbus devices. Indeed dynamic sysbus devices are created after machine init. machvirt also registers a notifier that will build the device tree nodes for the platform bus and its children dynamic sysbus devices. Signed-off-by: NEric Auger <eric.auger@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-4-git-send-email-eric.auger@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
Add a GICv2m device to the virt board to enable MSIs on the generic PCI host controller. We allocate 64 SPIs in the IRQ space for now (this can be increased/decreased later) and map the GICv2m right after the GIC in the memory map. Reviewed-by: NEric Auger <eric.auger@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-5-git-send-email-christoffer.dall@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
In preparation for adding the GICv2m which requires address specifiers and is a subnode of the gic, we extend the gic DT definition to specify the #address-cells and #size-cells properties and add an empty ranges property properties of the DT node, since this is required to add the v2m node as a child of the gic node. Note that we must also expand the irq-map to reference the gic with the right address-cells as a consequence of this change. Reviewed-by: NEric Auger <eric.auger@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-4-git-send-email-christoffer.dall@linaro.org Suggested-by: NShanker Donthineni <shankerd@codeaurora.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
Instead of passing the GIC phandle around between functions, add it to the VirtBoardInfo just like we do for the clock_phandle. We are about to add the v2m phandle as well, and it's easier not having to pass around a bunch of phandles, return multiple values from functions, etc. Reviewed-by: NEric Auger <eric.auger@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 29 5月, 2015 4 次提交
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由 Shannon Zhao 提交于
Initialize VirtGuestInfoState and register a machine_init_done notify to call virt_acpi_build(). Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-25-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. The Arch Timer interrupts must be provided for GTDT. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-11-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
To generate ACPI table for PCIe controller, we need the base and size of the PCIe ranges. Record these ranges in MemMapEntry array, then we could share and use them for generating ACPI table. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Move some common definitions to virt.h. These will be used by generating ACPI tables. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 12 5月, 2015 1 次提交
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由 Greg Bellows 提交于
Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-16-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-4-git-send-email-greg.bellows@linaro.org [PMM: minor format tweak] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 09 4月, 2015 1 次提交
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由 Dirk Müller 提交于
Commit 0b183fc8:"memory: move mem_path handling to memory_region_allocate_system_memory" split memory_region_init_ram and memory_region_init_ram_from_file. Also it moved mem-path handling a step up from memory_region_init_ram to memory_region_allocate_system_memory. Therefore for any board that uses memory_region_init_ram directly, -mem-path is not supported. Fix this by replacing memory_region_init_ram with memory_region_allocate_system_memory. Signed-off-by: NDirk Mueller <dmueller@suse.com> Message-id: CAL5wTH4UHYKpJF=dLJfFzxpufjY189chnCow47-ySuLf8GLbug@mail.gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 02 4月, 2015 2 次提交
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由 Shannon Zhao 提交于
As 4de9a883(hw/arm/virt: Fix memory leak reported by Coverity) and 6e05a12f(arm: fix memory leak) both handle the memory leak reported by Coverity, this cause qemu corruption due to double free. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NStefan Weil <sw@weilnetz.de> Message-id: 1427944026-8968-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Stefan Weil 提交于
As the conditional statement had to be split anyway, we can also add a better error report message. Signed-off-by: NStefan Weil <sw@weilnetz.de> Message-id: 1426877982-3603-1-git-send-email-sw@weilnetz.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 19 3月, 2015 2 次提交
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由 zhanghailiang 提交于
This is a continuation of the work started in commit 565f65d2: "error: Use error_report_err() where appropriate" Signed-off-by: Nzhanghailiang <zhang.zhanghailiang@huawei.com> Reviewed-by: NEric Blake <eblake@redhat.com> Reviewed-by: NMarkus Armbruster <armbru@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Gonglei 提交于
Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: NGonglei <arei.gonglei@huawei.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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- 11 3月, 2015 1 次提交
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由 Ard Biesheuvel 提交于
The recently introduced feature that allows 32 bit guests to be executed under KVM on a 64-bit host incorrectly handles the case where more than 1 cpu is specified using '-smp N' For instance, this invocation of qemu qemu-system-aarch64 -M virt -cpu cortex-a57,aarch64=off -smp 2 produces the following error qemu-system-aarch64: Expected key=value format, found aarch64 which is caused by the destructive parsing performed by cpu_common_parse_features(), resulting in subsequent attempts to parse the CPU option string (for each additional CPU) to fail. So duplicate the string before parsing it, and free it directly afterwards. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: NGreg Bellows <greg.bellows@linaro.org> Message-id: 1425402380-10488-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 3月, 2015 1 次提交
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由 Markus Armbruster 提交于
Three kinds of callers: 1. On failure, report the error and abort Passing &error_abort does the job. No functional change. 2. On failure, report the error and exit() This is qdev_prop_set_drive_nofail(). Error reporting moves from qdev_prop_set_drive() to its caller. Because hiding away the error in the monitor right before exit() isn't helpful, replace qerror_report_err() by error_report_err(). Shouldn't make a difference, because qdev_prop_set_drive_nofail() should never be used in QMP context. 3. On failure, report the error and recover This is usb_msd_init() and scsi_bus_legacy_add_drive(). Error reporting and freeing the error object moves from qdev_prop_set_drive() to its callers. Because usb_msd_init() can't run in QMP context, replace qerror_report_err() by error_report_err() there. No functional change. scsi_bus_legacy_add_drive() calling qerror_report_err() is of course inappropriate, but this commit merely makes it more obvious. The next one will clean it up. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-Id: <1425925048-15482-3-git-send-email-armbru@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 13 2月, 2015 2 次提交
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由 Greg Bellows 提交于
Added machvirt parsing of feature keywords added to the -cpu command line option. Parsing occurs during machine initialization. Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1423736974-14254-3-git-send-email-greg.bellows@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
Now that we have a working "generic" PCIe host bridge driver, we can plug it into ARM's virt machine to always have PCIe available to normal ARM VMs. I've successfully managed to expose a Bochs VGA device, XHCI and an e1000 into an AArch64 VM with this and they all lived happily ever after. Signed-off-by: NAlexander Graf <agraf@suse.de> Tested-by: NClaudio Fontana <claudio.fontana@huawei.com> [PMM: Squashed in fix for off-by-one error in bus-range DT property from Laszlo Ersek <lersek@redhat.com>] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 05 2月, 2015 1 次提交
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由 Laszlo Ersek 提交于
Signed-off-by: NLaszlo Ersek <lersek@redhat.com> Message-id: 1422592273-4432-1-git-send-email-lersek@redhat.com [PMM: added note recommending UUIDs] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 23 12月, 2014 3 次提交
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由 Laszlo Ersek 提交于
The virt board already ensures mutual exclusion between -bios and -pflash unit#0; we only need to set "bootinfo.firmware_loaded", introduced in the previous patch, if either of those options was used to load the guest firmware. Signed-off-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Message-id: 1419250305-31062-12-git-send-email-pbonzini@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Laszlo Ersek 提交于
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c, ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt" board. Because MMIO access is slow on ARM KVM, we enable the guest, with fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access. This has been measured to speed up transfers up to 7.5-fold, relative to single byte data access, on both ARM KVM and x86_64 TCG. The MMIO register block of fw_cfg is advertized in the device tree. As base address we pick 0x09020000, which conforms to the comment preceding "a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB, and it is aligned at 64KB. The DTB properties follow the documentation in the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt". fw_cfg automatically exports a number of files to the guest; for example, "bootorder" (see fw_cfg_machine_reset()). Signed-off-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Greg Bellows 提交于
Adds setting of the CPU has_el3 property based on the virt machine secure state property during initialization. This enables/disables EL3 state during start-up. Changes include adding an additional secure state boolean during virt CPU initialization. Also disables the ARM secure boot by default. Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Message-id: 1418684992-8996-13-git-send-email-greg.bellows@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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