- 29 3月, 2018 1 次提交
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由 Michael Clark 提交于
- Model borrowed from target/sh4/cpu.c - Rewrote riscv_cpu_list to use object_class_get_list - Dropped 'struct RISCVCPUInfo' and used TypeInfo array - Replaced riscv_cpu_register_types with DEFINE_TYPES - Marked base class as abstract - Fixes -cpu list Cc: Igor Mammedov <imammedo@redhat.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: NMichael Clark <mjc@sifive.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: NIgor Mammedov <imammedo@redhat.com>
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- 20 3月, 2018 1 次提交
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由 Michael Clark 提交于
This version uses a constant size memory buffer sized for the maximum possible ISA string length. It also uses g_new instead of g_new0, uses more efficient logic to append extensions and adds manual zero termination of the string. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: NMichael Clark <mjc@sifive.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> [PMM: Use qemu_tolower() rather than tolower()] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 07 3月, 2018 1 次提交
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由 Michael Clark 提交于
Add CPU state header, CPU definitions and initialization routines Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NSagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: NMichael Clark <mjc@sifive.com>
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