- 23 9月, 2016 2 次提交
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由 Cédric Le Goater 提交于
We plan to add more Aspeed boards to this file. There are no changes in the code. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-5-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
Let's prepare for new Aspeed SoCs and rename the ast2400 file to a more generic one. There are no changes in the code apart from the header file include. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-2-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 12 5月, 2016 2 次提交
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由 Jean-Christophe DUBOIS 提交于
The sabrelite supports one SPI FLASH memory on SPI1 Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe DUBOIS 提交于
For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 17 3月, 2016 2 次提交
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由 Andrew Jeffery 提交于
The new machine is a thin layer over the AST2400 ARM926-based SoC[1]. Between the minimal machine and the current SoC implementation there is enough functionality to boot an aspeed_defconfig Linux kernel to userspace. Nothing yet is specific to the Palmetto's BMC (other than using an AST2400 SoC), but creating specific machine types is preferable to a generic machine that doesn't match any particular hardware. [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-5-git-send-email-andrew@aj.id.au Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrew Jeffery 提交于
While the ASPEED AST2400 SoC[1] has a broad range of capabilities this implementation is minimal, comprising an ARM926 processor, ASPEED VIC and timer devices, and a 8250 UART. [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-4-git-send-email-andrew@aj.id.au Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 03 2月, 2016 3 次提交
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由 Andrew Baumann 提交于
Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: NAndrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrew Baumann 提交于
This is the SoC for Raspberry Pi 2. Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: NAndrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrew Baumann 提交于
This device maintains all the non-CPU peripherals on bcm2835 (Pi1) which are also present on bcm2836 (Pi2). It also implements the private address spaces used for DMA and mailboxes. Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: NAndrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 07 9月, 2015 3 次提交
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由 Jean-Christophe Dubois 提交于
Tested by booting a minimal Linux system on the emulated platform Tested by booting the Xvisor hypervisor on the emulated platform Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: d27347300d253509d921bc27a6d0a14db877478b.1441057361.git.jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe Dubois 提交于
For now we support the following devices: * CPU: ARM926 * Interrupt Controller: AVIC * CCM * UART x 5 * EPIT x 2 * GPT x 4 * FEC * I2C x 3 Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 62218bfa90f9101f79098e768c3d58bd92dcb7f3.1441057361.git.jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe Dubois 提交于
For now we support the following devices: * CPU: ARM1136 * Interrupt Controller: AVIC * CCM * UART x 2 * EPIT x 2 * GPT Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: f146d819594e41568daec42a1d0f440cdfe3df76.1441057361.git.jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 02 6月, 2015 1 次提交
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由 Eric Auger 提交于
This new C module will be used by ARM machine files to generate platform bus node and their dynamic sysbus device tree nodes. Dynamic sysbus device node addition is done in a machine init done notifier. arm_register_platform_bus_fdt_creator does the registration of this latter and is supposed to be called by ARM machine files that support platform bus and their dynamic sysbus. Addition of dynamic sysbus nodes is done only if the user did not provide any dtb. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NEric Auger <eric.auger@linaro.org> Reviewed-by: NShannon Zhao <zhaoshenglong@huawei.com> Reviewed-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-2-git-send-email-eric.auger@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 29 5月, 2015 1 次提交
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由 Shannon Zhao 提交于
Introduce a preliminary framework in virt-acpi-build.c with the main ACPI build functions. It exposes the generated ACPI contents to guest over fw_cfg. The required ACPI v5.1 tables for ARM are: - RSDP: Initial table that points to XSDT - RSDT: Points to FADT GTDT MADT tables - FADT: Generic information about the machine - GTDT: Generic timer description table - MADT: Multiple APIC description table - DSDT: Holds all information about system devices/peripherals, pointed by FADT Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-5-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 18 5月, 2015 2 次提交
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由 Peter Crosthwaite 提交于
Add a machine model for the Xilinx ZynqMP SoC EP108 board. Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3896b34c862f370dc0679e4428bf3848d1f9f83c.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 11 3月, 2015 2 次提交
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由 Alistair Francis 提交于
This patch adds the Netduino 2 Machine. This is a Cortex-M3 based machine. Information can be found at: http://www.netduino.com/netduino2/specs.htmSigned-off-by: NAlistair Francis <alistair@alistair23.me> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5bd999824f14252c122c4501cc973cee986eadd7.1424175342.git.alistair@alistair23.me Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
This patch adds the stm32f205 SoC. This will be used by the Netduino 2 to create a machine. Signed-off-by: NAlistair Francis <alistair@alistair23.me> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 48d509747a1ea0d8a7d5480560495e679990f9d2.1424175342.git.alistair@alistair23.me Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 18 12月, 2013 4 次提交
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-6-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-5-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Antony Pavlov 提交于
Also this patch adds initial support for Canon PowerShot A1100 IS compact camera. Signed-off-by: NAntony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-3-git-send-email-antonynpavlov@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Antony Pavlov 提交于
DIGIC is Canon Inc.'s name for a family of SoC for digital cameras and camcorders. There is no publicly available specification for DIGIC chips. All information about DIGIC chip internals is based on reverse engineering efforts made by CHDK (http://chdk.wikia.com) and Magic Lantern (http://www.magiclantern.fm) projects contributors. Signed-off-by: NAntony Pavlov <antonynpavlov@gmail.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-2-git-send-email-antonynpavlov@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 12月, 2013 1 次提交
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由 Peter Maydell 提交于
Add 'virt' platform support corresponding to arch/arm/mach-virt in the Linux kernel tree. This has no platform-specific code but can use any device whose kernel driver is is able to work purely from a device tree node. We use this to instantiate a minimal set of devices: a GIC and some virtio-mmio transports. Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-8-git-send-email-peter.maydell@linaro.org [PMM: Significantly overhauled: * renamed user-facing machine to just "virt" * removed the A9 support (it can't work since the A9 has no generic timers) * added virtio-mmio transports instead of random set of 'soc' devices (though we retain a pl011 UART) * instead of updating io_base as we step through adding devices, define a memory map with an array (similar to vexpress) * similarly, define irqmap with an array * folded in some minor fixes from John's aarch64-support patch * rather than explicitly doing endian-swapping on FDT cells, use fdt APIs that let us just pass in host-endian values and let the fdt layer take care of the swapping * miscellaneous minor code cleanups and style fixes ] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 20 8月, 2013 1 次提交
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由 Peter Maydell 提交于
Now all the boards have been converted arm_pic_init_cpu() is unused and can just be deleted. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1375977856-25046-15-git-send-email-peter.maydell@linaro.org
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- 09 4月, 2013 16 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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