1. 16 3月, 2016 10 次提交
    • D
      target-ppc: Add helpers for updating a CPU's SDR1 and external HPT · e5c0d3ce
      David Gibson 提交于
      When a Power cpu with 64-bit hash MMU has it's hash page table (HPT)
      pointer updated by a write to the SDR1 register we need to update some
      derived variables.  Likewise, when the cpu is configured for an external
      HPT (one not in the guest memory space) some derived variables need to be
      updated.
      
      Currently the logic for this is (partially) duplicated in ppc_store_sdr1()
      and in spapr_cpu_reset().  In future we're going to need it in some other
      places, so make some common helpers for this update.
      
      In addition the new ppc_hash64_set_external_hpt() helper also updates
      SDR1 in KVM - it's not updated by the normal runtime KVM <-> qemu CPU
      synchronization.  In a sense this belongs logically in the
      ppc_hash64_set_sdr1() helper, but that is called from
      kvm_arch_get_registers() so can't itself call cpu_synchronize_state()
      without infinite recursion.  In practice this doesn't matter because
      the only other caller is TCG specific.
      
      Currently there aren't situations where updating SDR1 at runtime in KVM
      matters, but there are going to be in future.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Reviewed-by: NGreg Kurz <gkurz@linux.vnet.ibm.com>
      Reviewed-by: NThomas Huth <thuth@redhat.com>
      e5c0d3ce
    • D
      target-ppc: Split out SREGS get/put functions · a7a00a72
      David Gibson 提交于
      Currently the getting and setting of Power MMU registers (sregs) take up
      large inline chunks of the kvm_arch_get_registers() and
      kvm_arch_put_registers() functions.  Especially since there are two
      variants (for Book-E and Book-S CPUs), only one of which will be used in
      practice, this is pretty hard to read.
      
      This patch splits these out into helper functions for clarity.  No
      functional change is expected.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Reviewed-by: NThomas Huth <thuth@redhat.com>
      Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Reviewed-by: NGreg Kurz <gkurz@linux.vnet.ibm.com>
      a7a00a72
    • M
      spapr_pci: fix multifunction hotplug · 788d2599
      Michael Roth 提交于
      Since 3f1e1478, QEMU has adopted a convention of supporting function
      hotplug by deferring hotplug events until func 0 is hotplugged.
      This is likely how management tools like libvirt would expose
      such support going forward.
      
      Since sPAPR guests rely on per-func events rather than
      slot-based, our protocol has been to hotplug func 0 *first* to
      avoid cases where devices appear within guests without func 0
      present to avoid undefined behavior.
      
      To remain compatible with new convention, defer hotplug in a
      similar manner, but then generate events in 0-first order as we
      did in the past. Once func 0 present, fail any attempts to plug
      additional functions (as we do with PCIe).
      
      For unplug, defer unplug operations in a similar manner, but
      generate unplug events such that function 0 is removed last in guest.
      Signed-off-by: NMichael Roth <mdroth@linux.vnet.ibm.com>
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      788d2599
    • A
      target-ppc: Add PVR for POWER8NVL processor · a88dced8
      Alexey Kardashevskiy 提交于
      This adds a new POWER8+NVLink CPU PVR which core is identical to POWER8
      but has a different PVR. The only available machine now has PVR
      pvr 004c 0100 so this defines "POWER8NVL" alias as v1.0.
      
      The corresponding kernel commit is
      https://github.com/torvalds/linux/commit/ddee09c099c3
      "powerpc: Add PVR for POWER8NVL processor"
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      a88dced8
    • B
    • T
      ppc: Fix migration of the TAR SPR · 1e440cbc
      Thomas Huth 提交于
      The TAR special purpose register currently does not get migrated
      under KVM because it does not get synchronized with the kernel.
      Use spr_register_kvm() instead of spr_register() to fix this issue.
      Signed-off-by: NThomas Huth <thuth@redhat.com>
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      1e440cbc
    • T
      ppc: Define the PSPB register on POWER8 · d6f1445f
      Thomas Huth 提交于
      POWER8 / PowerISA 2.07 has a new special purpose register called PSPB
      ("Problem State Priority Boost Register"). The contents of this register
      are currently lost during migration. To be able to migrate this register,
      too, we've got to define this SPR along with the other SPRs of POWER8.
      Signed-off-by: NThomas Huth <thuth@redhat.com>
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      d6f1445f
    • P
      Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into staging · a6cdb77f
      Peter Maydell 提交于
      slirp: Adding IPv6 support to Qemu -net user mode
      
      # gpg: Signature made Tue 15 Mar 2016 16:06:03 GMT using RSA key ID FB6B2F1D
      # gpg: Good signature from "Samuel Thibault <samuel.thibault@gnu.org>"
      # gpg:                 aka "Samuel Thibault <sthibault@debian.org>"
      # gpg:                 aka "Samuel Thibault <samuel.thibault@inria.fr>"
      # gpg:                 aka "Samuel Thibault <samuel.thibault@labri.fr>"
      # gpg:                 aka "Samuel Thibault <samuel.thibault@ens-lyon.org>"
      # gpg: WARNING: This key is not certified with sufficiently trusted signatures!
      # gpg:          It is not certain that the signature belongs to the owner.
      # Primary key fingerprint: 900C B024 B679 31D4 0F82  304B D017 8C76 7D06 9EE6
      #      Subkey fingerprint: F632 74CD C630 0873 CB3D  29D9 E3E5 1CE8 FB6B 2F1D
      
      * remotes/thibault/tags/samuel-thibault:
        slirp: Add IPv6 support to the TFTP code
        qapi-schema, qemu-options & slirp: Adding Qemu options for IPv6 addresses
        slirp: Adding IPv6 address for DNS relay
        slirp: Handle IPv6 in TCP functions
        slirp: Reindent after refactoring
        slirp: Generalizing and neutralizing various TCP functions before adding IPv6 stuff
        slirp: Factorizing tcpiphdr structure with an union
        slirp: Adding IPv6 UDP support
        slirp: Adding ICMPv6 error sending
        slirp: Fix ICMP error sending
        slirp: Adding IPv6, ICMPv6 Echo and NDP autoconfiguration
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      a6cdb77f
    • P
      Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging · a58a4cb1
      Peter Maydell 提交于
      vhost, virtio, pci, pc, acpi
      
      nvdimm work
      sparse cpu id rework
      ipmi enhancements
      fixes all over the place
      pxb option to tweak chassis number
      Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
      
      # gpg: Signature made Tue 15 Mar 2016 14:33:10 GMT using RSA key ID D28D5469
      # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
      # gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"
      
      * remotes/mst/tags/for_upstream: (51 commits)
        hw/acpi: fix GSI links UID
        ipmi: add some local variables in ipmi_sdr_init
        ipmi: remove the need of an ending record in the SDR table
        ipmi: use a function to initialize the SDR table
        ipmi: add a realize function to the device class
        ipmi: add rsp_buffer_set_error() helper
        ipmi: remove IPMI_CHECK_RESERVATION() macro
        ipmi: replace IPMI_ADD_RSP_DATA() macro with inline helpers
        ipmi: remove IPMI_CHECK_CMD_LEN() macro
        MAINTAINERS: machine core
        MAINTAINERS: Add an entry for virtio header files
        pc: acpi: clarify why possible LAPIC entries must be present in MADT
        pc: acpi: drop cpu->found_cpus bitmap
        pc: acpi: create Processor and Notify objects only for valid lapics
        pc: acpi: create MADT.lapic entries only for valid lapics
        pc: acpi: SRAT: create only valid processor lapic entries
        pc: acpi: cleanup qdev_get_machine() calls
        machine: introduce MachineClass.possible_cpu_arch_ids() hook
        pc: init pcms->apic_id_limit once and use it throughout pc.c
        pc: acpi: remove NOP assignment
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      a58a4cb1
    • T
      slirp: Add IPv6 support to the TFTP code · fad7fb9c
      Thomas Huth 提交于
      Add the handler code for incoming TFTP packets to udp6_input(),
      and make sure that the TFTP code can send packets with both,
      udp_output() and udp6_output() by introducing a wrapper function
      called tftp_udp_output().
      Signed-off-by: NThomas Huth <thuth@redhat.com>
      Signed-off-by: NSamuel Thibault <samuel.thibault@ens-lyon.org>
      fad7fb9c
  2. 15 3月, 2016 30 次提交