1. 12 9月, 2014 3 次提交
  2. 11 9月, 2014 2 次提交
    • P
      Merge remote-tracking branch 'remotes/kraxel/tags/pull-console-20140905-2' into staging · 0dfa7e30
      Peter Maydell 提交于
      console: pixman switchover continued, add some infrastructure to make it
               easier using pixman in display device emulation.
      
      # gpg: Signature made Fri 05 Sep 2014 14:38:57 BST using RSA key ID D3E87138
      # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
      # gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
      # gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
      
      * remotes/kraxel/tags/pull-console-20140905-2:
        console: Remove unused QEMU_BIG_ENDIAN_FLAG
        console: add qemu_pixman_linebuf_copy
        console: add dpy_gfx_update_dirty
        console: add qemu_create_displaysurface_guestmem
        console: stop using PixelFormat
        console: reimplement qemu_default_pixelformat
        console: add qemu_default_pixman_format
        console: add qemu_pixelformat_from_pixman
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      0dfa7e30
    • P
      Merge remote-tracking branch 'remotes/kraxel/tags/pull-usb-20140910-1' into staging · fc3b9aa8
      Peter Maydell 提交于
      xhci PCIe endpoint migration compatibility fix
      
      # gpg: Signature made Wed 10 Sep 2014 06:35:20 BST using RSA key ID D3E87138
      # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
      # gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
      # gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
      
      * remotes/kraxel/tags/pull-usb-20140910-1:
        xhci PCIe endpoint migration compatibility fix
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      fc3b9aa8
  3. 10 9月, 2014 1 次提交
    • D
      xhci PCIe endpoint migration compatibility fix · e6043e92
      Dr. David Alan Gilbert 提交于
      Add back the PCIe config capabilities on XHCI cards in non-PCIe slots,
      but only for machine types before 2.1.
      
      This fixes a migration incompatibility in the XHCI PCI devices
      caused by:
         058fdcf5 - xhci: add endpoint cap on express bus only
      
      Note that in fixing it for compatibility with older QEMUs, it breaks
      compatibility with existing QEMU 2.1's on older machine types.
      
      The status before this patch was (if it used an XHCI adapter):
         machine type | source qemu
           any           pre-2.1     - FAIL
           any           2.1...      - PASS
      
      With this patch:
         machine type | source qemu
           any           pre-2.1    - PASS
           pre-2.1       2.1...     - FAIL
           2.1           2.1...     - PASS
      
      A test to trigger it is to add '-device nec-usb-xhci,id=xhci,addr=0x12'
      to the command line.
      
      Cc: qemu-stable@nongnu.org
      Signed-off-by: NDr. David Alan Gilbert <dgilbert@redhat.com>
      Acked-by: NMichael S. Tsirkin <mst@redhat.com>
      Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
      e6043e92
  4. 09 9月, 2014 2 次提交
  5. 08 9月, 2014 32 次提交
    • P
      Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging · 1bc0e405
      Peter Maydell 提交于
      Block pull request
      
      # gpg: Signature made Mon 08 Sep 2014 11:49:31 BST using RSA key ID 81AB73C8
      # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
      # gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>"
      
      * remotes/stefanha/tags/block-pull-request: (24 commits)
        ide: Add resize callback to ide/core
        IDE: Fill the IDENTIFY request consistently
        vmdk: fix buf leak in vmdk_parse_extents()
        vmdk: fix vmdk_parse_extents() extent_file leaks
        ide: Add wwn support to IDE-ATAPI drive
        qtest/ide: Uninitialize PC allocator
        libqos: add a simple first-fit memory allocator
        MAINTAINERS: update sheepdog maintainer
        qemu-nbd: fix indentation and coding style
        qemu-nbd: add option to set detect-zeroes mode
        rename parse_enum_option to qapi_enum_parse and make it public
        block/archipelago: Use QEMU atomic builtins
        qemu-img: fix rebase src_cache option documentation
        qemu-img: clarify src_cache option documentation
        libqos: Added EVENT_IDX support
        libqos: Added MSI-X support
        libqos: Added test case for configuration changes in virtio-blk test
        libqos: Added indirect descriptor support to virtio implementation
        libqos: Added basic virtqueue support to virtio implementation
        tests: Add virtio device initialization
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      1bc0e405
    • P
      Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging · 2d6838e8
      Peter Maydell 提交于
      Patch queue for ppc - 2014-09-08
      
      Alexander Graf (11):
            PPC: KVM: Fix g3beige and mac99 when HV is loaded
            PPC: mac99: Move NVRAM to page boundary when necessary
            KVM: Add helper to run KVM_CHECK_EXTENSION on vm fd
            PPC: KVM: Use vm check_extension for pv hcall
            PPC: mac99: Fix core99 timer frequency
            PPC: mac_nvram: Remove unused functions
            PPC: mac_nvram: Allow 2 and 4 byte accesses
            PPC: mac_nvram: Split NVRAM into OF and OSX parts
            PPC: Mac: Move tbfreq into local variable
            PPC: Cuda: Use cuda timer to expose tbfreq to guest
            PPC: Fix default config ordering and add eTSEC for ppc64
      
      Alexey Kardashevskiy (7):
            spapr: Move DT memory node rendering to a helper
            spapr: Use DT memory node rendering helper for other nodes
            spapr: Refactor spapr_populate_memory() to allow memoryless nodes
            spapr: Split memory nodes to power-of-two blocks
            spapr: Add a helper for node0_size calculation
            spapr: Fix ibm, associativity for memory nodes
            spapr_pci: Fix config space corruption
      
      Anton Blanchard (2):
            spapr-vlan: Don't touch last entry in buffer list
            hypervisor property clashes with hypervisor node
      
      Benjamin Herrenschmidt (2):
            loader: Add load_image_size() to replace load_image()
            spapr: Locate RTAS and device-tree based on real RMA
      
      Bharat Bhushan (4):
            ppc: debug stub: Get trap instruction opcode from KVM
            ppc: synchronize excp_vectors for injecting exception
            ppc: Add software breakpoint support
            ppc: Add hw breakpoint watchpoint support
      
      Gonglei (1):
            spapr: fix possible memory leak
      
      Greg Kurz (1):
            spapr_pci: map the MSI window in each PHB
      
      Nikunj A Dadhania (3):
            ppc: spapr-rtas - implement os-term rtas call
            spapr: add uuid/host details to device tree
            ppc/spapr: Fix MAX_CPUS to 255
      
      Peter Maydell (1):
            hw/ppc/spapr_hcall.c: Fix typo in function names
      
      Tom Musta (20):
            linux-user: Fix Stack Pointer Bug in PPC setup_rt_frame
            linux-user: Split PPC Trampoline Encoding from Register Save
            linux-user: Enable Signal Handlers on PPC64
            linux-user: Properly Dereference PPC64 ELFv1 Signal Handler Pointer
            linux-user: Implement do_setcontext for PPC64
            linux-user: Handle PPC64 ELFv2 Function Pointers
            target-ppc: Bug Fix: rlwinm
            target-ppc: Bug Fix: rlwnm
            target-ppc: Bug Fix: rlwimi
            target-ppc: Bug Fix: mullwo
            target-ppc: Bug Fix: mullw
            target-ppc: Bug Fix: mulldo OV Detection
            target-ppc: Bug Fix: srawi
            target-ppc: Bug Fix: srad
            target-ppc: Special Case of rlwimi Should Use Deposit
            target-ppc: Optimize rlwinm MB=0 ME=31
            target-ppc: Optimize rlwnm MB=0 ME=31
            target-ppc: Clean Up mullw
            target-ppc: Clean up mullwo
            target-ppc: Implement mulldo with TCG
      
      # gpg: Signature made Mon 08 Sep 2014 11:51:15 BST using RSA key ID 03FEDC60
      # gpg: Can't check signature: public key not found
      
      * remotes/agraf/tags/signed-ppc-for-upstream: (52 commits)
        hypervisor property clashes with hypervisor node
        PPC: Fix default config ordering and add eTSEC for ppc64
        spapr_pci: map the MSI window in each PHB
        target-ppc: Implement mulldo with TCG
        target-ppc: Clean up mullwo
        target-ppc: Clean Up mullw
        target-ppc: Optimize rlwnm MB=0 ME=31
        target-ppc: Optimize rlwinm MB=0 ME=31
        target-ppc: Special Case of rlwimi Should Use Deposit
        spapr-vlan: Don't touch last entry in buffer list
        spapr_pci: Fix config space corruption
        PPC: Cuda: Use cuda timer to expose tbfreq to guest
        PPC: Mac: Move tbfreq into local variable
        PPC: mac_nvram: Split NVRAM into OF and OSX parts
        PPC: mac_nvram: Allow 2 and 4 byte accesses
        PPC: mac_nvram: Remove unused functions
        PPC: mac99: Fix core99 timer frequency
        PPC: KVM: Use vm check_extension for pv hcall
        KVM: Add helper to run KVM_CHECK_EXTENSION on vm fd
        target-ppc: Bug Fix: srad
        ...
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      2d6838e8
    • A
      hypervisor property clashes with hypervisor node · 85423d90
      Anton Blanchard 提交于
      dtc fails on a recent QEMU snapshot:
      
      ERROR (name_properties): "name" property in /hypervisor#1 is incorrect ("hypervisor" instead of base node name)
      
      Looking at the device tree we have a hypervisor property:
      
      # lsprop hypervisor
      hypervisor       "kvm"
      
      But we also have a hypervisor node, with a name that doesn't match:
      
      # lsprop hypervisor#1/
      name             "hypervisor"
      compatible       "linux,kvm"
      linux,phandle    7e5eb5d8 (2120136152)
      
      Commit c08ce91d309c (spapr: add uuid/host details to device tree)
      looks to have collided with an earlier patch. Remove the hypervisor
      property.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      85423d90
    • A
      PPC: Fix default config ordering and add eTSEC for ppc64 · 4a761ffa
      Alexander Graf 提交于
      We messed up the ordering in our default configs for PPC. The top entries
      are generic entries, then come sections that indicate that features are only
      in because of a special feature (such as PReP).
      
      Fix the ordering again and while at it add eTSEC support to the ppc64 target
      so that we can spawn eTSEC adapters with qemu-system-ppc64.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      4a761ffa
    • G
      spapr_pci: map the MSI window in each PHB · 8c46f7ec
      Greg Kurz 提交于
      On sPAPR, virtio devices are connected to the PCI bus and use MSI-X.
      Commit cc943c36 has modified MSI-X
      so that writes are made using the bus master address space and follow
      the IOMMU path.
      
      Unfortunately, the IOMMU address space address space does not have an
      MSI window: the notification is silently dropped in unassigned_mem_write
      instead of reaching the guest... The most visible effect is that all
      virtio devices are non-functional on sPAPR since then. :(
      
      This patch does the following:
      1) map the MSI window into the IOMMU address space for each PHB
         - since each PHB instantiates its own IOMMU address space, we
           can safely map the window at a fixed address (SPAPR_PCI_MSI_WINDOW)
         - no real need to keep the MSI window setup in a separate function,
           the spapr_pci_msi_init() code moves to spapr_phb_realize().
      
      2) kill the global MSI window as it is not needed in the end
      Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      8c46f7ec
    • T
      target-ppc: Implement mulldo with TCG · 22ffad31
      Tom Musta 提交于
      Optimize mulldo by using the muls2_i64 operation rather than a helper.  Eliminate
      the obsolete helper code.
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Suggested-by: NRichard Henderson <rth@twiddle.net>
      Reviewed-by: NRichard Henderson <rth@twiddle.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      22ffad31
    • T
      target-ppc: Clean up mullwo · 26977876
      Tom Musta 提交于
      Simplify the implementation of mullwo.  For 64 bit CPUs, the result is
      the concatenation of the upper and lower parts of the muls2_i32 operation,
      which may be slightly better than deposit.  For 32 bit CPUs, the lower part
      of the muls_i32 operation is moved into the target GPR.
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Suggested-by: NRichard Henderson <rth@twiddle.net>
      Reviewed-by: NRichard Henderson <rth@twiddle.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      26977876
    • T
      target-ppc: Clean Up mullw · 03039e5e
      Tom Musta 提交于
      Eliminate the unecessary ext32s TCG operation and make the multiplication
      operation explicitly 32 bit.
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Suggested-by: NRichard Henderson <rth@twiddle.net>
      Reviewed-by: NRichard Henderson <rth@twiddle.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      03039e5e
    • T
      target-ppc: Optimize rlwnm MB=0 ME=31 · 57fca134
      Tom Musta 提交于
      Optimize the special case of rlwnm where MB=0 and ME=31.  This can
      be implemented using a ROTL.
      Suggested-by: NRichard Henderson <rth@twiddle.net>
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Reviewed-by: NRichard Henderson <rth@twiddle.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      57fca134
    • T
      target-ppc: Optimize rlwinm MB=0 ME=31 · 8979c2f6
      Tom Musta 提交于
      Optimize the special case of rlwinm where MB=0 and ME=31.  This can
      be implemented as a 32-bit ROTL.
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Suggested-by: NRichard Henderson <rth@twiddle.net>
      Reviewed-by: NRichard Henderson <rth@twiddle.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      8979c2f6
    • T
      target-ppc: Special Case of rlwimi Should Use Deposit · ab92678d
      Tom Musta 提交于
      The special case of rlwimi where MB <= ME and SH = 31-ME can be implemented
      with a single TCG deposit operation.  This replaces the less general case
      of SH = MB = 0 and ME = 31.
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Suggested-by: NRichard Henderson <rth@twiddle.net>
      Reviewed-by: NRichard Henderson <rth@twiddle.net>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      ab92678d
    • A
      spapr-vlan: Don't touch last entry in buffer list · 439ce140
      Anton Blanchard 提交于
      The last 8 bytes of the buffer list is defined to contain the number
      of dropped frames. At the moment we use it to store rx entries,
      which trips up ethtool -S:
      
      rx_no_buffer: 9223380832981355136
      
      Fix this by skipping the last buffer list entry.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      439ce140
    • A
      spapr_pci: Fix config space corruption · 32420522
      Alexey Kardashevskiy 提交于
      When disabling MSI/MSIX via "ibm,change-msi" RTAS call, no check was made
      if MSI or MSIX is actually supported and the MSI message was reset
      unconditionally. If this happened on a device which does not support MSI
      (but does support MSIX, otherwise "ibm,change-msi" would not be called),
      this device would have PCIDevice::msi_cap field (MSI capability offset)
      set to zero and writing a vector would actually clear PCI status.
      
      This clears MSI message only if MSI or MSIX is present on a device.
      Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      32420522
    • A
      PPC: Cuda: Use cuda timer to expose tbfreq to guest · b981289c
      Alexander Graf 提交于
      Mac OS X calibrates a number of frequencies on bootup based on reading
      tb values on bootup and comparing them to via cuda timer values.
      
      The only variable we can really steer well (thanks to KVM) is the cuda
      frequency. So let's use that one to fake Mac OS X into believing the
      bus frequency is tbfreq * 4. That way Mac OS X will automatically
      calculate the correct timebase frequency.
      
      With this patch and the patch set I posted earlier I can successfully
      run Mac OS X 10.2, 10.3 and 10.4 guests with -M mac99 on TCG and KVM.
      Suggested-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      b981289c
    • A
      PPC: Mac: Move tbfreq into local variable · caae6c96
      Alexander Graf 提交于
      We already expose the real CPU's tb frequency to the guest via fw_cfg. Soon
      we will need to also expose it to the MacIO, so let's move it to a variable
      that we can leverage every time we need the frequency.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      caae6c96
    • A
      PPC: mac_nvram: Split NVRAM into OF and OSX parts · 2d9907a3
      Alexander Graf 提交于
      Mac OS X (at least with -M mac99) searches for a valid NVRAM partition
      of a special Apple type. If it can't find that partition in the first
      half of NVRAM, it will look at the second half.
      
      There are a few implications from this. The first is that we need to
      split NVRAM into 2 halves - one for Open Firmware use, the other one for
      Mac OS X. Without this split Mac OS X will just loop endlessly over the
      second half trying to find a partition.
      
      The other implication is that we should provide a specially crafted Mac
      OS X compatible NVRAM partition on the second half that Mac OS X can
      happily use as it sees fit.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      2d9907a3
    • A
      PPC: mac_nvram: Allow 2 and 4 byte accesses · b19eae18
      Alexander Graf 提交于
      The NVRAM in our Core99 machine really supports 2byte and 4byte accesses
      just as well as 1byte accesses. In fact, Mac OS X uses those.
      
      Add support for higher register size granularities.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      b19eae18
    • A
      PPC: mac_nvram: Remove unused functions · a8b05037
      Alexander Graf 提交于
      The macio_nvram_read and macio_nvram_write functions are never called,
      just remove them.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      a8b05037
    • A
      PPC: mac99: Fix core99 timer frequency · d696760b
      Alexander Graf 提交于
      There is a special timer in the mac99 machine that we recently started
      to emulate. Unfortunately we emulated it in the wrong frequency.
      
      This patch adapts the frequency Mac OS X uses to evaluate results from
      this timer, making calculations it bases off of it work.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      d696760b
    • A
      PPC: KVM: Use vm check_extension for pv hcall · 6fd33a75
      Alexander Graf 提交于
      To find out whether we support the KVM hypercall interface we need to ask KVM
      on the VM level rather than the global KVM level, because Book3S HV KVM does
      not support it and we play conservative when both HV and PR are loaded.
      
      So instead, use the VM helper that falls back to global KVM enumeration. That
      should cover all cases.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      6fd33a75
    • A
      KVM: Add helper to run KVM_CHECK_EXTENSION on vm fd · 7d0a07fa
      Alexander Graf 提交于
      We now can call KVM_CHECK_EXTENSION on the kvm fd or on the vm fd, whereas
      the vm version is more accurate when it comes to PPC KVM.
      
      Add a helper to make the vm version available that falls back to the non-vm
      variant if the vm one is not available yet to stay compatible.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      7d0a07fa
    • T
      target-ppc: Bug Fix: srad · 4bc02e23
      Tom Musta 提交于
      Fix the check for carry in the srad helper to properly construct
      the mask -- a "1ULL" must be used (instead of "1") in order to
      get the desired result.
      
      Example:
      
      R3 8000000000000000
      R4 F3511AD4A2CD4C38
      srad 3,3,4
      
      Should *not* set XER[CA] but does without this patch.
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      4bc02e23
    • T
      target-ppc: Bug Fix: srawi · 34a0fad1
      Tom Musta 提交于
      For 64 bit implementations, the special case of a shift by zero
      should result in the sign extension of the least significant 32 bits
      of the source GPR (not a direct copy of the 64 bit source GPR).
      
      Example:
      
      R3 A6212433228F41DC
      srawi 3,3,0
      R3 expected : 00000000228F41DC
      R3 actual   : A6212433228F41DC (without this patch)
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      34a0fad1
    • T
      target-ppc: Bug Fix: mulldo OV Detection · 9824d01d
      Tom Musta 提交于
      Fix the code to properly detect overflow; the 128 bit signed
      product must have all zeroes or all ones in the first 65 bits
      otherwise OV should be set.
      
      Example:
      
      R3 45F086A5D5887509
      R4 0000000000000002
      mulldo 3,3,4
      
      Should set XER[OV].
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      9824d01d
    • T
      target-ppc: Bug Fix: mullw · 1fa74845
      Tom Musta 提交于
      For 64-bit implementations, the mullw result is the 64 bit product
      of the sign-extended least significant 32 bits of the source
      registers.
      
      Fix the code to properly sign extend the source operands and produce
      a 64 bit product.
      
      Example:
      R3 00000000002F37A0
      R4 41C33D242F816715
      mullw 3,3,4
      R3 expected : 0008C3146AE0F020
      R3 actual   : 000000006AE0F020 (without this patch)
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      1fa74845
    • T
      target-ppc: Bug Fix: mullwo · f11ebbf8
      Tom Musta 提交于
      On 64-bit implementations, the mullwo result is the 64 bit product of
      the signed 32 bit operands.  Fix the implementation to properly deposit
      the upper 32 bits into the target register.
      
      Example:
      
      R3 0407DED115077586
      R4 53778DF3CA992E09
      mullwo 3,3,4
      R3 expected : FB9D02730D7735B6
      R3 actual   : 000000000D7735B6 (without this patch)
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      f11ebbf8
    • T
      target-ppc: Bug Fix: rlwimi · 6ea7b35c
      Tom Musta 提交于
      The rlwimi specification includes the ROTL32 operation, which is defined
      to be a left rotation of two copies of the least significant 32 bits of
      the source GPR.
      
      The current implementation is incorrect on 64-bit implementations in that
      it rotates a single copy of the least significant 32 bits, padding with
      zeroes in the most significant bits.
      
      Fix the code to properly implement this ROTL32 operation.
      
      Also fix the special case of MB=31 and ME=0 to copy the entire contents
      of the source GPR.
      
      Examples:
      
      R3 FFFFFFFFFFFFFFF0
      rlwimi 3,3,29,14,1
      R3 expected : 1FFFFFFE3FFFFFFE
      R3 actual   : 000000003FFFFFFE (without this patch)
      
      R3 ED7EB4DD824F0853
      rlwimi 3,3,10,31,0
      R3 expected : 3C214E09024F0853
      R3 actual   : 00000000024F0853 (without this patch)
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      6ea7b35c
    • T
      target-ppc: Bug Fix: rlwnm · 1c0a150f
      Tom Musta 提交于
      The rlwnm specification includes the ROTL32 operation, which is defined
      to be a left rotation of two copies of the least significant 32 bits of
      the source GPR.
      
      The current implementation is incorrect on 64-bit implementations in that
      it rotates a single copy of the least significant 32 bits, padding with
      zeroes in the most significant bits.
      
      Fix the code to properly implement this ROTL32 operation.
      
      Example:
      
      R3 = 0000000000000002
      R4 = 7FFFFFFFFFFFFFFF
      rlwnm 3,3,4,31,16
      R3 expected : 0000000100000001
      R3 actual   : 0000000000000001 (without this patch)
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      1c0a150f
    • T
      target-ppc: Bug Fix: rlwinm · a7f23d0f
      Tom Musta 提交于
      The rlwinm specification includes the ROTL32 operation, which is defined
      to be a left rotation of two copies of the least significant 32 bits of
      the source GPR.
      
      The current implementation is incorrect on 64-bit implementations in that
      it rotates a single copy of the least significant 32 bits, padding with
      zeroes in the most significant bits.
      
      Fix the code to properly implement this ROTL32 operation.
      
      Example:
      R3 = F7487D82EC6F75DF
      rlwinm 3,3,5,12,4
      
      R3 expected : 8DEEBBFD880EBBFD
      R3 actual   : 00000000880EBBFD (without this fix)
      Signed-off-by: NTom Musta <tommusta@gmail.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      a7f23d0f
    • N
      ppc/spapr: Fix MAX_CPUS to 255 · 9674a356
      Nikunj A Dadhania 提交于
      MAX_CPUS 256 is inconsistent with qemu supporting upto 255 cpus. This
      MAX_CPUS number was percolated back to "virsh capabilities" with wrong
      max_cpus.
      Signed-off-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      9674a356
    • B
      ppc: Add hw breakpoint watchpoint support · 88365d17
      Bharat Bhushan 提交于
      This patch adds hardware breakpoint and hardware watchpoint support
      for ppc.
      
      On BOOKE architecture we cannot share debug resources between QEMU
      and guest because:
          When QEMU is using debug resources then debug exception must
          be always enabled. To achieve this we set MSR_DE and also set
          MSRP_DEP so guest cannot change MSR_DE.
      
          When emulating debug resource for guest we want guest
          to control MSR_DE (enable/disable debug interrupt on need).
      
          So above mentioned two configuration cannot be supported
          at the same time. So the result is that we cannot share
          debug resources between QEMU and Guest on BOOKE architecture.
      
      In the current design QEMU gets priority over guest,
      this means that if QEMU is using debug resources then guest
      cannot use them and if guest is using debug resource then
      qemu can overwrite them.
      
      When QEMU is not able to handle debug exception then we inject program
      exception to guest. Yes program exception NOT debug exception and the
      reason is:
       1) QEMU and guest not sharing debug resources
       2) For software breakpoint QEMU uses a ehpriv-1 instruction;
      
       So there cannot be any reason that we are in qemu with exit reason
       KVM_EXIT_DEBUG  for guest set debug exception, only possibility is
       guest executed ehpriv-1 privilege instruction and that's why we are
       injecting program exception.
      Signed-off-by: NBharat Bhushan <Bharat.Bhushan@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      88365d17
    • B
      ppc: Add software breakpoint support · 8a0548f9
      Bharat Bhushan 提交于
      This patch allow insert/remove software breakpoint.
      
      When QEMU is not able to handle debug exception then we inject
      program exception to guest because for software breakpoint QEMU
      uses a ehpriv-1 instruction;
      So there cannot be any reason that we are in qemu with exit reason
      KVM_EXIT_DEBUG  for guest set debug exception, only possibility is
      guest executed ehpriv-1 privilege instruction and that's why we are
      injecting program exception.
      Signed-off-by: NBharat Bhushan <Bharat.Bhushan@freescale.com>
      [agraf: make deflect comment booke/book3s agnostic]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      8a0548f9