1. 05 11月, 2018 21 次提交
  2. 04 11月, 2018 1 次提交
  3. 03 11月, 2018 1 次提交
    • P
      Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181102' into staging · 7d56239f
      Peter Maydell 提交于
      target-arm queue:
       * microbit: Add the UART to our nRF51 SoC model
       * Add a virtual Xilinx Versal board "xlnx-versal-virt"
       * hw/arm/virt: Set VIRT_COMPAT_3_0 compat
       * MAINTAINERS: Remove bouncing email in ARM ACPI
       * strongarm: mask off high[31:28] bits from dir and state registers
       * target/arm: Conditionalize some asserts on aarch32 support
       * hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro
      
      # gpg: Signature made Fri 02 Nov 2018 17:14:43 GMT
      # gpg:                using RSA key 3C2525ED14360CDE
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
      # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
      
      * remotes/pmaydell/tags/pull-target-arm-20181102:
        hw/arm: versal: Add a virtual Xilinx Versal board
        hw/arm: versal: Add a model of Xilinx Versal SoC
        target/arm: Conditionalize some asserts on aarch32 support
        hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro
        strongarm: mask off high[31:28] bits from dir and state registers
        MAINTAINERS: Remove bouncing email in ARM ACPI
        tests/boot-serial-test: Add microbit board testcase
        hw/arm/nrf51_soc: Connect UART to nRF51 SoC
        hw/char: Implement nRF51 SoC UART
        hw/arm/virt: Set VIRT_COMPAT_3_0 compat
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      7d56239f
  4. 02 11月, 2018 17 次提交