adress -> address
managment -> management

Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NStefan Weil <sw@weilnetz.de>
Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>

Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: NPavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>

Add instructions of RR1 opcode format, that have 0xb3 as first opcode.
Add helper functions mulh, mulmh and mulrh, that compute multiplication,
with multiprecision (mulmh) or rounding (mulrh) of 4 halfwords, being either low or high parts
of two 32 bit regs.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Fix gen_mtcr using wrong register.
Fix gen_mtcr/mfcr using sign extended offsets.
Fix B format insn using not sign extendend offsets.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Some of the 1.6 ISA instructions were still missing. So let's add them.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of RR opcode format, that have 0x4b as the first opcode.
Add helper functions:
    * parity: Calculates the parity bits for every byte of a 32 int.
    * bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two bitwise.
    * unpack: unpack a IEEE 754 single precision floating point number as exponent and mantissa.
    * dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
                       where the quotient result is guaranteed to fit into 8 bit.
    * dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
                       where the quotient result is guaranteed to fit into 16 bit.
OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of RR opcode format, that have 0x1 as the first opcode.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of RR opcode format, that have 0xf as the first opcode.
Add helper functions:
    * clo/z/s: Counts leading ones/zeros/signs.
    * clo/z/s_h: Count leading ones/zeros/signs in two haflwords.
    * sh/_h: Shifts one/two word/hwords.
    * sha/_h: Shifts one/two word/hwords arithmeticly.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of RR opcode format, that have 0xb as the first opcode.
Add helper functions, for hword and byte arithmetics:
    * add_h_ssov/suov: Add two halfword and saturate on overflow.
    * sub_h_ssov/suov: Sub two halfword and saturate on overflow.
    * absdif_h_ssov: Compute absolute difference for halfwords and saturate on overflow.
    * abs_h_ssov/suov: Compute absolute value for two halfwords and saturate on overflow.
    * abs_b/h: Compute absolute value for four/two bytes/halfwords
    * absdif_b/h: Compute absolute difference for four/two bytes/halfwords
    * add_b/h: Add four/two bytes/halfwords.
    * sub_b/h: Sub four/two bytes/halfwords.
    * eq_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on
              equality and set all bits of to either one ore zero.
    * eqany_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality.
    * lt_b/bu/h/hu: Compare four/two bytes/halfwords with four/two bytes/halfwords
                    on less than signed and unsigned.
    * max_b/bu/h/hu: Calculate max for four/two bytes/halfwords signed and unsigned.
    * min_b/bu/h/hu: Calculate min for four/two bytes/halfwords signed and unsigned.
Add helper function abs_ssov, that computes the absolute value for a 32 bit integer and saturates on overflow.
Add microcode generator functions:
    * gen_sub_CC: Caluclates sub and sets the carry bit.
    * gen_subc_CC: Caluclates sub and carry and sets the carry bit
    * gen_abs: Compute absolute value for a 32 bit integer.
    * gen_cond_w: Compares two 32 bit values on cond and sets result either zero or all bits one.

OPC2_32_RR_MIN switched with OPC2_32_RR_MIN_U.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

The mask is actually 7 bit long, instead of 6, so the expression checking
for JNZ.T is always false. Let's make the mask 1 bit wider.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>

Now using psw_read() to retrieve the status bits correctly.
Signed-off-by: NAlex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>

Signed-off-by: NAlex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>

Signed-off-by: NAlex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>

Add instructions of RCR opcode format.
Add helper for madd32/64_ssov and madd32/64_suov.
Add helper for msub32/64_ssov and msub32/64_suov.
Add microcode generator function madd/msub for 32bit and 64bit, which calculate a mul and a add/sub.
OPC2_32_RCR_MSUB_U_32 -> OPC2_32_RCR_MSUB_U_32.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core special function register, which are defined in csfr.def
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of RCPW, RCRR and RCRW opcode format.
Add microcode generator function gen_insert.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C 1.6),
make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way
we only need to check our features for the instructionset, where a instruction was first introduced.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of RC opcode format.
Add helper for mul, sha, absdif with signed saturation on overflow.
Add helper for add, sub, mul with unsigned saturation on overflow.
Add microcode generator functions:
    * gen_add_CC, which calculates the carry bit.
    * gen_addc_CC, which adds the carry bit to the add and calculates the carry bit.
    * gen_absdif, which calculates the absolute difference.
    * gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
    * gen_sh_hi, which shifts two 16bit words in one reg.
    * gen_sha_hi, which does a arithmetic shift on two 16bit words.
    * gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb.
    * gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
      with the lsb of the result.
    * gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of BRR opcode format.
Add MASK_OP_BRR_DISP15_SEXT.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of BRN opcode format.
Add MASK_OP_BRN_DISP15_SEXT.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of BRC opcode format.
Fixed OP2_BRC_JGE -> OP2_32_BRC_JGE
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of BOL opcode format.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of BO opcode format.
Add microcode generator functions gen_swap, gen_ldmst.
Add microcode generator functions gen_st/ld_preincr, which write back the address after the memory access.
Add helper for circular and bit reverse addr mode calculation.
Add sign extended bitmask for BO_OFF10 field.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of BIT opcode format.
Add microcode generator functions gen_bit_1/2op to do 1/2 bit operations on the last bit.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of B opcode format.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of ABS, ABSB opcode format.
Add microcode generator functions for ld/st of two 32bit reg as one 64bit value.
Add microcode generator functions for ldmst and swap.
Add helper ldlcx, lducx, stlcx and stucx.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>

Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-16-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-15-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-14-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-13-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add instructions of SBC and SBRN opcode format.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-12-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-11-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-10-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add instructions of SSR opcode format.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-9-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-8-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-7-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 1409572800-4116-6-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-5-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add TriCore target stubs, and QOM cpu, and Maintainer
Signed-off-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-id: 1409572800-4116-2-git-send-email-kbastian@mail.uni-paderborn.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>