- 20 12月, 2013 40 次提交
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由 Stefan Hajnoczi 提交于
Commit 75884afd ("virtio-blk: Convert to QOM realize") dropped a duplicate error_report() call. Now we no longer get the following error message twice: QEMU_PROG: -drive if=virtio: Device initialization failed. Update qemu-iotests 051. Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Fam Zheng 提交于
This improves vmdk_create to use bdrv_* functions to replace qemu_open and other fd functions. The error handling are improved as well. One difference is that bdrv_pwrite will round up buffer to sectors, so for description file, an extra bdrv_truncate is used in the end to drop inding zeros. Notes: - A bonus bug fix is correct endian is used in initializing GD entries. - ROUND_UP and DIV_ROUND_UP are used where possible. I tested that new code produces exactly the same file as previously. Signed-off-by: NFam Zheng <famz@redhat.com> Tested-by: NPeter Lieven <pl@kamp.de> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Fam Zheng 提交于
VMFS extent line in description file should be with 4 fields: RW <size> VMFS "file-name.vmdk" Check the number explicitly and report error if offset is appended as FLAT, which should be invalid format. Reported-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NFam Zheng <famz@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Jeff Cody 提交于
The man page for qemu-img, and the qemu-doc, did not mention VHDX as a supported format. This adds in reference to VHDX in those documents. [Stefan Weil <sw@weilnetz.de> suggested s/Block Size/Block size/ for consistency. I have made this change. --Stefan] Signed-off-by: NJeff Cody <jcody@redhat.com> Reviewed-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Jeff Cody 提交于
If there is a dirty log file to be replayed in a VHDX image, it is replayed in .vhdx_open(). However, if the file is opened read-only, then a somewhat cryptic error message results. This adds a more helpful error message for the user. If an image file contains a log to be replayed, and is opened read-only, the user is instructed to run 'qemu-img check -r all' on the image file. Running qemu-img check -r all will cause the image file to be opened r/w, which will replay the log file. If a log file replay is detected, this is flagged, and bdrv_check will increase the corruptions_fixed count for the image. [Fixed typo in error message that was pointed out by Eric Blake <eblake@redhat.com>. --Stefan] Signed-off-by: NJeff Cody <jcody@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Stefan Weil 提交于
Function iscsi_read10_task got additional parameters starting with version libiscsi 1.5.0. libiscsi 1.4.0 is still widely used (Debian wheezy, jessie and other Linux distributions currently provide packages for QEMU which use it), so we still need support for this older API. Reviewed-by: NPeter Lieven <pl@kamp.de> Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Stefan Hajnoczi 提交于
We are moving boldly on to QEMU 2.0 in the next release. Some patches written at a time where we assumed 1.8 would be the next version number managed to sneak in. s/1.8/2.0/ in qapi-schema.json Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com> Reviewed-by: NFam Zheng <famz@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Liu Yuan 提交于
When running qcow2 over sheepdog, we might meet following problem qemu-system-x86_64: shrinking is not supported And cause IO errors to Guest. This is because we abuse bs->total_sectors, which is manipulated by generic block layer and race with sheepdog code. We should directly check if offset > vdi_size to dynamically enlarge the volume instead of 'offset > bs->total_sectors', which will cause problem when following case happens: vdi_size > offset > bs->total_sectors # then trigger sd_truncate() to shrink the volume wrongly. Cc: qemu-devel@nongnu.org Cc: Kevin Wolf <kwolf@redhat.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Reported-by: NHadrien KOHL <hadrien.kohl@gmail.com> Signed-off-by: NLiu Yuan <namei.unix@gmail.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Anthony Liguori 提交于
Patch queue for ppc - 2013-12-20 Alexander Graf (3): PPC: Use default pci bus name for grackle and heathrow roms: Flush icache when writing roms to guest memory PPC: Add VSX to hflags Alexey Kardashevskiy (5): powerpc: add PVR mask support target-ppc: move POWER7+ to a separate family spapr-rtas: replace return code constants with macros spapr-rtas: add ibm, (get|set)-system-parameter spapr: make sure RMA is in first mode of first memory node Greg Kurz (1): target-ppc: add stubs for KVM breakpoints Paolo Bonzini (1): spapr: tie spapr-nvram to -pflash Paul Mackerras (1): spapr: limit numa memory regions by ram size Peter Crosthwaite (2): device_tree: s/qemu_devtree/qemu_fdt globally device_tree: qemu_fdt_setprop: Rename val_array arg Tom Musta (19): Declare and Enable VSX Add MSR VSX and Associated Exception Add VSX Instruction Decoders Add VSR to Global Registers Add lxvd2x Add stxvd2x Add xxpermdi Add lxsdx Add lxvdsx Add lxvw4x Add stxsdx Add stxvw4x Add VSX Scalar Move Instructions Add VSX Vector Move Instructions Add Power7 VSX Logical Instructions Add xxmrgh/xxmrgl Add xxsel Add xxspltw Add xxsldwi * agraf/tags/signed-ppc-for-upstream: (32 commits) spapr: limit numa memory regions by ram size spapr: make sure RMA is in first mode of first memory node device_tree: qemu_fdt_setprop: Rename val_array arg device_tree: s/qemu_devtree/qemu_fdt globally PPC: Add VSX to hflags Add xxsldwi Add xxspltw Add xxsel Add xxmrgh/xxmrgl Add Power7 VSX Logical Instructions Add VSX Vector Move Instructions Add VSX Scalar Move Instructions roms: Flush icache when writing roms to guest memory spapr: tie spapr-nvram to -pflash PPC: Use default pci bus name for grackle and heathrow spapr-rtas: add ibm, (get|set)-system-parameter spapr-rtas: replace return code constants with macros target-ppc: move POWER7+ to a separate family Add stxvw4x Add stxsdx ...
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由 Paul Mackerras 提交于
This makes sure that all NUMA memory blocks reside within RAM or have zero length. Reviewed-by: NThomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
The SPAPR specification says that the RMA starts at the LPAR's logical address 0 and is the first logical memory block reported in the LPAR’s device tree. So SLOF only maps the first block and that block needs to span the full RMA. This makes sure that the RMA area is where SLOF expects it. Reviewed-by: NThomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Peter Crosthwaite 提交于
Looking at the implementation, this doesn't really have a lot to do with arrays. Its just a pointer to a buffer and is passed through to the wrapped fn (qemu_fdt_setprop) unchanged. So rename to make it consistent with libfdt, which in the wrapped function just calls it "val". Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Peter Crosthwaite 提交于
The qemu_devtree API is a wrapper around the fdt_ set of APIs. Rename accordingly. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> [agraf: also convert hw/arm/virt.c] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We generate different code depending on whether MSR_VSX is set or clear, so it needs to be part of our hflags too which indicate whether we're still in the same translation block cache bucket. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Shift Left Double by Word Immediate (xxsldwi) instruction. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Splat Word (xxsplatw) instruction. This is the first instruction to use the UIM immediate field and consequently a decoder is also added. V2: reworked implementation per Richard Henderson's comments. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Select (xxsel) instruction. The xxsel instruction has four VSR operands. Thus the xC instruction decoder is added. The xxsel instruction is massively overloaded in the opcode table since only bits 26 and 27 are opcode bits. This overloading is done in matrix fashion with two macros (GEN_XXSEL_ROW and GEN_XX_SEL). V2: (1) eliminated unecessary XXSEL macro (2) tighter implementation using tcg_gen_andc_i64. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX Merge High Word and VSX Merge Low Word instructions. V2: Now implemented using deposit (per Richard Henderson's comment) Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX logical instructions that are defined by the Version 2.06 Power ISA (aka Power7): - xxland - xxlandc - xxlor - xxlxor - xxlnor Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the vector move instructions: - xvabsdp - Vector Absolute Value Double-Precision - xvnabsdp - Vector Negative Absolute Value Double-Precision - xvnegdp - Vector Negate Double-Precision - xvcpsgndp - Vector Copy Sign Double-Precision - xvabssp - Vector Absolute Value Single-Precision - xvnabssp - Vector Negative Absolute Value Single-Precision - xvnegsp - Vector Negate Single-Precision - xvcpsgnsp - Vector Copy Sign Single-Precision V3: Per Paolo Bonzini's suggestion, used a temporary for the sign mask and andc. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the VSX scalar move instructions: - xsabsdp (Scalar Absolute Value Double-Precision) - xsnabspd (Scalar Negative Absolute Value Double-Precision) - xsnegdp (Scalar Negate Double-Precision) - xscpsgndp (Scalar Copy Sign Double-Precision) A common generator macro (VSX_SCALAR_MOVE) is added since these instructions vary only slightly from each other. Macros to support VSX XX2 and XX3 form opcodes are also added. These macros handle the overloading of "opcode 2" space (instruction bits 26:30) caused by AX and BX bits (29 and 30, respectively). V3: Per feedback from Paolo Bonzini, moved the sign mask into a temporary and used andc. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We use the rom infrastructure to write firmware and/or initial kernel blobs into guest address space. So we're basically emulating the cache off phase on very early system bootup. That phase is usually responsible for clearing the instruction cache for anything it writes into cachable memory, to ensure that after reboot we don't happen to execute stale bits from the instruction cache. So we need to invalidate the icache every time we write a rom into guest address space. We do not need to do this for every DMA since the guest expects it has to flush the icache manually in that case. This fixes random reboot issues on e5500 (booke ppc) for me. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Paolo Bonzini 提交于
spapr-nvram's drive property is currently connected to a non-existent "-machine nvram=<drivename>" option. Instead, tie it to -pflash like other non-volatile RAM devices. This provides the following possibilities for adding a backend for the sPAPR non-volatile RAM: * -pflash filename * -drive if=pflash,file=filename,format=raw,... * -drive if=none,file=filename,format=raw,id=foo,... -global spapr-nvram.drive=foo Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
There's no good reason to call our bus "pci" rather than let the default bus name take over ("pci.0"). The big downside to calling it different from anyone else is that tools that pass -device get confused. They are looking for a bus "pci.0" rather than "pci". To make life easier for everyone, let's just drop the name override. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
This adds very basic handlers for ibm,get-system-parameter and ibm,set-system-parameter RTAS calls. The only parameter handled at the moment is "platform-processor-diagnostics-run-mode" which is always disabled and does not support changing. This is expected to make "ppc64_cpu --run-mode=1" happy. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> [agraf: s/papameter/parameter/g] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexey Kardashevskiy 提交于
So far POWER7+ was a part of POWER7 family. However it has a different PVR base value so in order to support PVR masks, it needs a separate family class. This adds a new family class, PVR base and mask values and moves Power7+ v2.1 CPU to a new family. The class init function is copied from the POWER7 family. This defines a firmware name for the new family as "PowerPC,POWER7+" instead of previously used "PowerPC,POWER7" from the POWER7 family. The reason for that is that the Sapphire firmware (a h0st firmware) uses "PowerPC,POWER7+" already and since no specification defines exactly the CPU nodes naming in the device tree, we better stay in sync with the host firmware. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x) instruction. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx) instruction. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x) instruction. V2: changed to use deposit_i64 per Richard Henderson's review. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Load VSX Vector Doubleword & Splat Indexed (lxvdsx) instruction. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx) instruction. The lower 8 bytes of the target register are undefined; this implementation leaves those bytes unaltered. Signed-off-by: NTom Musta <tommusta@gmail.com> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the xxpermdi instruction. The instruction uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX and BX). This results in overloading of the opcode table with aliases, which can be seen in the GEN_XX3FORM_DM macro. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAnton Blanchard <anton@samba.org> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the stxvd2x instruction. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAnton Blanchard <anton@samba.org> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds the lxvd2x instruction. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAnton Blanchard <anton@samba.org> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Tom Musta 提交于
This patch adds VSX VSRs to the the list of global register indices. More specifically, it adds the lower halves of the first 32 VSRs to the list of global register indices. The upper halves of the first 32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs are already defined via the cpu_avrh[] and cpu_avrl[] arrays. Signed-off-by: NTom Musta <tommusta@gmail.com> Signed-off-by: NAnton Blanchard <anton@samba.org> Signed-off-by: NAlexander Graf <agraf@suse.de>
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