- 01 2月, 2019 15 次提交
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由 Peter Maydell 提交于
The SYS_VERSION and SYS_CONFIG register values differ between the IoTKit and SSE-200. Make them configurable via QOM properties rather than hard-coded, and set them appropriately in the ARMSSE code that instantiates the IOTKIT_SYSINFO device. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-15-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Create a cluster object to hold each CPU in the SSE. They are logically distinct and may be configured differently (for instance one may not have an FPU where the other does). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-14-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Give each CPU its own container memory region. This is necessary for two reasons: * some devices are instantiated one per CPU and the CPU sees only its own device * since a memory region can only be put into one container, we must give each armv7m object a different MemoryRegion as its 'memory' property, or a dual-CPU configuration will assert on realize when the second armv7m object tries to put the MR into a container when it is already in the first armv7m object's container Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-13-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SSE-200 has two Cortex-M33 CPUs. These see the same view of memory, with the exception of the "private CPU region" which has per-CPU devices. Internal device interrupts for SSE-200 devices are mostly wired up to both CPUs, with the exception of a few per-CPU devices. External GPIO inputs on the SSE-200 device are provided for the second CPU's interrupts above 32, as is already the case for the first CPU. Refactor the code to support creation of multiple CPUs. For the moment we leave all CPUs with the same view of memory: this will not work in the multiple-CPU case, but we will fix this in the following commit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-12-peter.maydell@linaro.org
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由 Peter Maydell 提交于
For the IoTKit the SRAM bank size is always 32K (15 bits); for the SSE-200 this is a configurable parameter, which defaults to 32K but can be changed when it is built into a particular SoC. For instance the Musca-B1 board sets it to 128K (17 bits). Make the bank size a QOM property. We follow the SSE-200 hardware in naming the parameter SRAM_ADDR_WIDTH, which specifies the number of address bits of a single SRAM bank. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-11-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SSE-200 has four banks of SRAM, each with its own Memory Protection Controller, where the IoTKit has only one. Make the number of SRAM banks a field in ARMSSEInfo. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-10-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SSE-200 has 4 banks of SRAM, each with its own internal Memory Protection Controller. The interrupt status for these extra MPCs appears in the same security controller SECMPCINTSTATUS register as the MPC for the IoTKit's single SRAM bank. Enhance the iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE variant in use does not have all 4 MPCs then the unused inputs will simply result in the SECMPCINTSTATUS bits being zero as required.) The hardcoded constant "1"s in armsse.c indicate the actual number of SRAM MPCs the IoTKit has, and will be replaced in the following commit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-9-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Rename the files that used to be iotkit.[ch] to armsse.[ch] to reflect the fact they new cover multiple Arm subsystems for embedded. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-8-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Rename various internal uses of 'iotkit' in hw/arm/iotkit.c to 'armsse', for consistency. The remaining occurences are: * related to the devices TYPE_IOTKIT_SYSCTL, TYPE_IOTKIT_SYSINFO, etc, which this refactor is not touching * references that apply specifically to the IoTKit (like the lack of a private CPU region) * the vmstate, which keeps its old "iotkit" name for migration compatibility reasons Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-7-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The Arm SSE-200 Subsystem for Embedded is a revised and extended version of the older IoTKit SoC. Prepare for adding a model of it by refactoring the IoTKit code into an abstract base class which contains the functionality, driven by a class data block specific to each subclass. (This is the same approach used by the existing bcm283x SoC family implementation.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-6-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The Arm IoTKit was effectively the forerunner of a series of subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200: https://developer.arm.com/products/system-design/subsystems These are generally quite similar, though later iterations have extra devices that earlier ones do not. We want to add a model of the SSE-200, which means refactoring the IoTKit code into an abstract base class and subclasses (using the same design that the bcm283x SoC and Aspeed SoC family implementations do). As a first step, rename the IoTKit struct and QOM macros to ARMSSE, which is what we're going to name the base class. We temporarily retain TYPE_IOTKIT to avoid changing the code that instantiates a TYPE_IOTKIT device here and then changing it back again when it is re-introduced as a subclass. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-5-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Expose "start-powered-off" as a property of the ARMv7M container, which we just pass through to the CPU object in the same way that we do for "init-svtor" and "idau". (We want this for the SSE-200, which powers up only the first CPU at reset and leaves the second powered down.) As with the other CPU properties here, we can't just use alias properties, because the CPU QOM object is not created until armv7m realize time. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-4-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Rather than just creating the CPUs with object_new, make them child objects of the armv7m container. This will allow the cluster code to find the CPUs if an armv7m object is made a child of a cluster object. object_new_with_props() will do the parenting for us. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-3-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Currently the ARMv7M NVIC object's realize method assumes that the CPU the NVIC is attached to is CPU 0, because it thinks there can only ever be one CPU in the system. To allow a dual-Cortex-M33 setup we need to remove this assumption; instead the armv7m wrapper object tells the NVIC its CPU, in the same way that it already tells the CPU what the NVIC is. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-2-peter.maydell@linaro.org
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由 kumar sourav 提交于
set object owner in memory_region_init_ram() instead of NULL. Signed-off-by: Nkumar sourav <sourav.jb1988@gmail.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NStefan Hajnoczi <stefanha@redhat.com> Message-id: 20190125155630.17430-1-sourav.jb1988@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 31 1月, 2019 3 次提交
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由 Li Qiang 提交于
There is no need to make another reference. Signed-off-by: NLi Qiang <liq3ea@163.com> Reviewed-by: NMax Reitz <mreitz@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190120055558.32984-4-liq3ea@163.com Signed-off-by: NMax Reitz <mreitz@redhat.com>
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由 Li Qiang 提交于
When it is zero, it causes segv. Using following command: "-drive file=//home/test/test1.img,if=none,id=id0 -device nvme,drive=id0,serial=test,num_queues=0" causes following Backtrack: Thread 4 "qemu-system-x86" received signal SIGSEGV, Segmentation fault. [Switching to Thread 0x7fffe9735700 (LWP 30952)] 0x0000555555a7a77c in nvme_start_ctrl (n=0x5555577473f0) at hw/block/nvme.c:825 825 if (unlikely(n->cq[0])) { (gdb) bt 0 0x0000555555a7a77c in nvme_start_ctrl (n=0x5555577473f0) at hw/block/nvme.c:825 1 0x0000555555a7af7f in nvme_write_bar (n=0x5555577473f0, offset=20, data=4587521, size=4) at hw/block/nvme.c:969 2 0x0000555555a7b81a in nvme_mmio_write (opaque=0x5555577473f0, addr=20, data=4587521, size=4) at hw/block/nvme.c:1163 3 0x0000555555869236 in memory_region_write_accessor (mr=0x555557747cd0, addr=20, value=0x7fffe97320f8, size=4, shift=0, mask=4294967295, attrs=...) at /home/test/qemu1/qemu/memory.c:502 4 0x0000555555869446 in access_with_adjusted_size (addr=20, value=0x7fffe97320f8, size=4, access_size_min=2, access_size_max=8, access_fn=0x55555586914d <memory_region_write_accessor>, mr=0x555557747cd0, attrs=...) at /home/test/qemu1/qemu/memory.c:568 5 0x000055555586c479 in memory_region_dispatch_write (mr=0x555557747cd0, addr=20, data=4587521, size=4, attrs=...) at /home/test/qemu1/qemu/memory.c:1499 6 0x00005555558030af in flatview_write_continue (fv=0x7fffe0061130, addr=4273930260, attrs=..., buf=0x7ffff7ff0028 "\001", len=4, addr1=20, l=4, mr=0x555557747cd0) at /home/test/qemu1/qemu/exec.c:3234 7 0x00005555558031f9 in flatview_write (fv=0x7fffe0061130, addr=4273930260, attrs=..., buf=0x7ffff7ff0028 "\001", len=4) at /home/test/qemu1/qemu/exec.c:3273 8 0x00005555558034ff in address_space_write ( ---Type <return> to continue, or q <return> to quit--- as=0x555556758480 <address_space_memory>, addr=4273930260, attrs=..., buf=0x7ffff7ff0028 "\001", len=4) at /home/test/qemu1/qemu/exec.c:3363 9 0x0000555555803550 in address_space_rw ( as=0x555556758480 <address_space_memory>, addr=4273930260, attrs=..., buf=0x7ffff7ff0028 "\001", len=4, is_write=true) at /home/test/qemu1/qemu/exec.c:3374 10 0x00005555558884a1 in kvm_cpu_exec (cpu=0x555556920e40) at /home/test/qemu1/qemu/accel/kvm/kvm-all.c:2031 11 0x000055555584cd9d in qemu_kvm_cpu_thread_fn (arg=0x555556920e40) at /home/test/qemu1/qemu/cpus.c:1281 12 0x0000555555dbaf6d in qemu_thread_start (args=0x5555569438a0) at util/qemu-thread-posix.c:502 13 0x00007ffff5dc86db in start_thread (arg=0x7fffe9735700) at pthread_create.c:463 14 0x00007ffff5af188f in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:95 Signed-off-by: NLi Qiang <liq3ea@163.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190120055558.32984-3-liq3ea@163.com Signed-off-by: NMax Reitz <mreitz@redhat.com>
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由 Li Qiang 提交于
Signed-off-by: NLi Qiang <liq3ea@163.com> Reviewed-by: NMax Reitz <mreitz@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190120055558.32984-2-liq3ea@163.com Signed-off-by: NMax Reitz <mreitz@redhat.com>
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- 30 1月, 2019 14 次提交
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由 Stefano Garzarella 提交于
VirtIOBlock *s is already defined and initialized with req->dev on top of virtio_blk_handle_request(), so we can remove it from the code block of VIRTIO_BLK_T_GET_ID case. Signed-off-by: NStefano Garzarella <sgarzare@redhat.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Message-Id: <20190130095231.42081-1-sgarzare@redhat.com> Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
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由 Paul Durrant 提交于
This should have been removed then xen_disk.c was removed but I missed them. Fixes: 19f87870 xen: remove the legacy 'xen_disk' backend Signed-off-by: NPaul Durrant <paul.durrant@citrix.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190122145132.12571-1-paul.durrant@citrix.com> [lv: s/stake/stale/ and add "Fixes" tag] Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
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由 kumar sourav 提交于
Sets the category of the sd memory card as DEVICE_CATEGORY_STORAGE. Devices should be assigned to one of DEVICE_CATEGORY_XXXX. Signed-off-by: Nkumar sourav <sourav.jb1988@gmail.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Message-Id: <20190124162045.10474-1-sourav.jb1988@gmail.com> Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
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由 kumar sourav 提交于
Sets the category of i8042 device as DEVICE_CATEGORY_INPUT Devices should be assigned to one of DEVICE_CATEGORY_XXXX. Signed-off-by: Nkumar sourav <sourav.jb1988@gmail.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Message-Id: <20190125151440.13794-1-sourav.jb1988@gmail.com> Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
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由 Dr. David Alan Gilbert 提交于
apci_1_compatible should be acpi_1_compatible. Signed-off-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190125094047.22276-1-dgilbert@redhat.com> Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
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由 kumar sourav 提交于
Sets the category of edu device as DEVICE_CATEGORY_MISC. Devices should be assigned to one of DEVICE_CATEGORY_XXXX. Signed-off-by: Nkumar sourav <sourav.jb1988@gmail.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Message-Id: <20190124144606.4352-1-sourav.jb1988@gmail.com> Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
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由 Bandan Das 提交于
qemu_write_full takes care of partial blocking writes, as in cases of larger file sizes Suggested-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NBandan Das <bsd@redhat.com> Message-id: 20190129131908.27924-4-bsd@redhat.com Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Bandan Das 提交于
For every MTP_WRITE_BUF_SZ copied, this patch writes it to file before getting the next block of data. The file is kept opened for the duration of the operation but the sanity checks on the write operation are performed only once when the write operation starts. Additionally, we also update the file size in the object metadata once the file has completely been written. Suggested-by: NGerd Hoffman <kraxel@redhat.com> Signed-off-by: NBandan Das <bsd@redhat.com> Message-id: 20190129131908.27924-3-bsd@redhat.com Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Bandan Das 提交于
This is a "pre-patch" to breaking up the write buffer for MTP writes. Instead of allocating a mtp buffer equal to size sent by the initiator, we start with a small size and reallocate multiples (of that small size) as needed. Signed-off-by: NBandan Das <bsd@redhat.com> Message-id: 20190129131908.27924-2-bsd@redhat.com Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Yuri Benditovich 提交于
Implement underrun/overrun events of isochronous endpoints according to XHCI spec (4.10.3.1) Guest software restarts data streaming when receives these events. The XHCI reports these events using interrupter assigned to the slot (as these events do not have TRB), so current commit adds the field of assigned interrupter to the XHCISlot structure. Guest software assigns interrupter to the slot on 'Address Device' and 'Evaluate Context' commands. Signed-off-by: NYuri Benditovich <yuri.benditovich@janustech.com> Message-id: 20190128200444.5128-3-yuri.benditovich@janustech.com Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Yuri Benditovich 提交于
According to the XHCI spec (4.10.2) the controller never halts isochronous endpoints. This commit prevent stop of isochronous streaming when sporadic errors status received from backends. Signed-off-by: NYuri Benditovich <yuri.benditovich@janustech.com> Message-id: 20190128200444.5128-2-yuri.benditovich@janustech.com Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Thomas Huth 提交于
It's either "GNU *Library* General Public version 2" or "GNU Lesser General Public version *2.1*", but there was no "version 2.0" of the "Lesser" library. So assume that version 2.1 is meant here. Additionally, suggest that the user should have received a copy of the LGPL, and not the GPL here. Signed-off-by: NThomas Huth <thuth@redhat.com> Message-id: 1548254454-7659-1-git-send-email-thuth@redhat.com Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Li Qiang 提交于
Spotted by Coverity: CID 1397070 Signed-off-by: NLi Qiang <liq3ea@163.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190103133113.49599-1-liq3ea@163.com [ kraxel: dropped chunk which adds close() after successful fdopendir() call, that is not needed according to POSIX even though Coverity flags it as bug ] Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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由 Gerd Hoffmann 提交于
Windows guests have trouble dealing with usb devices having identical serial numbers. So, assign unique serial numbers to usb hid devices. All other usb devices have this already. In the past the fixed serial number has been used to indicate working remote setup to linux guests. Here is a bit of history: * First there was nothing. * Then I added a rule to udev checking for serial == 42. (this is in rhel-6). * Then systemd + udev merged. * Then I changed the rule to check for serial != 1 instead, so we can use any serial but "1" which is the one the old broken devices had (this is in rhel-7). March 2014 in upstream systemd. * Then all usb power management rules where dropped from systemd (June 2015). Which I figured today (Sept 2018), after wondering that the rules are gone in fedora 28. So, three years ago the serial number check was dropped upstream, yet I hav't seen a single report about autosuspend issues (or cpu usage for usb emulation going up, which is the typical symtom). So I figured I can stop worring that changing the serial number will break things and just do it. And even if it turns out autosuspend is still an issue: I think meanwhile we can really stop worrying about guests running in old qemu versions with broken usb suspend (fixed in 0.13 !). If needed we can enable autosuspend unconditionally in guests. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com> Message-id: 20190110125108.22834-1-kraxel@redhat.com
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- 29 1月, 2019 8 次提交
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由 Peter Maydell 提交于
For TCG we want to distinguish which cluster a CPU is in, and we need to do it quickly. Cache the cluster index in the CPUState struct, by having the cluster object set cpu->cluster_index for each CPU child when it is realized. This means that board/SoC code must add all CPUs to the cluster before realizing the cluster object. Regrettably QOM provides no way to prevent adding children to a realized object and no way for the parent to be notified when a new child is added to it, so we don't have any way to enforce/assert this constraint; all we can do is document it in a comment. We can at least put in a check that the cluster contains at least one CPU, which should catch the typical cases of "realized cluster too early" or "forgot to parent the CPUs into it". The restriction on how many clusters can exist in the system is imposed by TCG code which will be added in a subsequent commit, but the check to enforce it in cluster.c fits better in this one. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Message-id: 20190121152218.9592-3-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Currently the cluster implementation doesn't have any constraints on the ordering of realizing the TYPE_CPU_CLUSTER and populating it with child objects. We want to impose a constraint that realize must happen only after all the child objects are added, so move the realize of rpu_cluster. (The apu_cluster is already realized after child population.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NLuc Michel <luc.michel@greensocs.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20190121152218.9592-2-peter.maydell@linaro.org
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由 Cédric Le Goater 提交于
The m25p80 models dummy cycles using byte transfers. This works well when the transfers are initiated by the QEMU model of a SPI controller but when these are initiated by the OS, it breaks emulation. Snoop the SPI transfer to catch commands requiring dummy cycles and replace them with byte transfers compatible with the m25p80 model. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NFrancisco Iglesias <frasse.iglesias@gmail.com> Message-id: 20190124140519.13838-5-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The SMC controllers have a register containing the byte that will be used as dummy output. It can be modified by software. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NJoel Stanley <joel@jms.id.au> Message-id: 20190124140519.13838-4-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The model should expose one control register per possible CS. When testing the validity of the register number in the read operation, replace 's->num_cs' by 'ctrl->max_slaves' which represents the maximum number of flash devices a controller can handle. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Message-id: 20190124140519.13838-3-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
0xFFFFFFFF should be returned for non implemented registers. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Message-id: 20190124140519.13838-2-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
If we aren't going to create any RPUs, then don't create the rpu-cluster unit. This allows us to add an assertion to the cluster object that it contains at least one CPU, which helps to avoid bugs in creating clusters and putting CPUs in them. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Tested-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190121184314.14311-1-peter.maydell@linaro.org
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由 Steffen Görtz 提交于
Recent microbit firmwares panic if the TWI magnetometer/accelerometer devices are not detected during startup. We don't implement TWI (I2C) so let's stub out these devices just to let the firmware boot. Signed-off by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com> Message-id: 20190110094020.18354-2-stefanha@redhat.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> [PMM: fixed comment style] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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