1. 16 6月, 2014 3 次提交
  2. 08 5月, 2014 1 次提交
  3. 05 3月, 2014 1 次提交
  4. 02 9月, 2013 1 次提交
  5. 29 7月, 2013 1 次提交
  6. 04 7月, 2013 2 次提交
  7. 20 6月, 2013 5 次提交
  8. 06 5月, 2013 2 次提交
  9. 09 4月, 2013 1 次提交
    • P
      hw: move headers to include/ · 0d09e41a
      Paolo Bonzini 提交于
      Many of these should be cleaned up with proper qdev-/QOM-ification.
      Right now there are many catch-all headers in include/hw/ARCH depending
      on cpu.h, and this makes it necessary to compile these files per-target.
      However, fixing this does not belong in these patches.
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      0d09e41a
  10. 01 3月, 2013 2 次提交
  11. 19 12月, 2012 2 次提交
  12. 14 12月, 2012 1 次提交
  13. 31 10月, 2012 1 次提交
  14. 23 10月, 2012 1 次提交
    • A
      Rename target_phys_addr_t to hwaddr · a8170e5e
      Avi Kivity 提交于
      target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
      reserved) and its purpose doesn't match the name (most target_phys_addr_t
      addresses are not target specific).  Replace it with a finger-friendly,
      standards conformant hwaddr.
      
      Outstanding patchsets can be fixed up with the command
      
        git rebase -i --exec 'find -name "*.[ch]"
                              | xargs s/target_phys_addr_t/hwaddr/g' origin
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      a8170e5e
  15. 22 10月, 2012 1 次提交
  16. 04 10月, 2012 2 次提交
    • D
      pseries: Rework implementation of TCE bypass · 53724ee5
      David Gibson 提交于
      On the pseries machine the IOMMU (aka TCE tables) is always active for all
      PCI and VIO devices.  Mostly to simplify the SLOF firmware, we implement an
      extension which allows the IOMMU to be temporarily disabled for certain
      devices.
      
      Currently this is implemented by setting the device's DMAContext pointer to
      NULL (thus reverting to qemu's default no-IOMMU DMA behaviour), then
      replacing it when bypass mode is disabled.
      
      This approach causes a bunch of complications though.  It complexifies the
      management of the DMAContext lifetimes, it's problematic for savevm/loadvm,
      and it means that while bypass is active we have nowhere to store the
      device's LIOBN (Logical IO Bus Number, used to identify DMA address
      spaces).  At present we regenerate the LIOBN from other address information
      but this restricts how we can allocate LIOBNs.
      
      This patch gives up on this approach, replacing it with the much simpler
      one of having a 'bypass' boolean flag in the TCE state structure.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      53724ee5
    • D
      pseries: Reset emulated PCI TCE tables on system reset · eddeed26
      David Gibson 提交于
      The emulated PCI host bridge on the pseries machine incorporates an IOMMU
      (PAPR TCE table).  Currently the mappings in this IOMMU are not cleared
      when we reset the system.  This patch fixes this bug.  To do this it adds
      a new reset function to the IOMMU emulation code.  The VIO devices already
      reset their TCE tables, but they do so by destroying and re-creating their
      DMA context.  This doesn't work for the PCI host bridge, because the
      infrastructure for PCI IOMMUs has already copied/cached the DMA pointer
      context into the subordinate PCI device structures.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      eddeed26
  17. 16 8月, 2012 1 次提交
  18. 28 6月, 2012 2 次提交