Skip to content

Q
qemu

openeuler / qemu

通知 10
Star 0
Fork 0
Q
qemu

体验新版 GitCode，发现更多精彩内容 >>

切换分支/标签
  1. 29 8月, 2008 13 次提交
  3. 28 8月, 2008 2 次提交
  5. 27 8月, 2008 1 次提交
  7. 26 8月, 2008 4 次提交
  9. 25 8月, 2008 3 次提交
  11. 24 8月, 2008 7 次提交
  13. 23 8月, 2008 2 次提交
  15. 22 8月, 2008 8 次提交
    • A
      uhci: improved TD matching, working ISOC transfers · e8ee3c72
      由 aurel32 提交于 
      While trying to make VX-3000 camera work on XP under KVM I realized that
we do not necessarily have to find original TD address. All we care about
is the token which identifies the transfer rather well (direction, endpoint,
size, etc).
This is especially important for the isochronous transfers because otherwise
they are being canceled left and right and we do not make much progress.

With this patch all devices that used bulk transfers that I've tried so
far continue to work just as well. And now my USB web cammera (isoc transfers)
is working well tool. It's not as smooth as native Windows but it's pretty
darn smooth.

The cool thing is that new USB code (both usb-uhci and usb-linux) is totaly
generic and does not need any special logic for ISOC.
Signed-off-by: NMax Krasnyansky <maxk@kernel.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5072 c046a42c-6fe2-441c-8c8c-71466251a162
      e8ee3c72
    • A
      add comment for DisplayState->idle · 472a397f
      由 aurel32 提交于 
      Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5071 c046a42c-6fe2-441c-8c8c-71466251a162
      472a397f
    • A
      uhci: Fixed length handling for SETUP and OUT tokens · 5d808245
      由 aurel32 提交于 
      Fixes regression reported agains Linux 2.6.18.
Looks like XP and newer Linux kernels are less sensitive
to length returned for control transfers.
Signed-off-by: NMax Krasnyansky <maxk@kernel.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5070 c046a42c-6fe2-441c-8c8c-71466251a162
      5d808245
    • A
      [sh4] code translation bug fix · 7da76bce
      由 aurel32 提交于 
      When a TLB miss occurs while pre-decrement store instruction such as
"mov.l Rm, @-Rn" is executed, re-execution of such instruction cause
status confusion. Because pre Rn decrement is executed before TLB miss,
re-execution decrements Rn again.
In other words, in a translated instruction array, register status
should not modified before memory access instruction.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5069 c046a42c-6fe2-441c-8c8c-71466251a162
      7da76bce
    • A
      [sh4] MMU bug fix · 06afe2c8
      由 aurel32 提交于 
      Some bugs on SH4 MMU are fixed.

- When a TLB entry is overwritten or invalidated, tlb_flush_page() should be
  invoked to invalidate old entry.
- When a ASID is changed, tlb_flush() should be invoke to invalidate entries
  which have old ASID.
- The check for shared bit in TLB entry causes multiple TLB hit exception.
  As SH3's MMU, shared bit is ignored.
- ASID is used when MMUCR's SV bit or SR's MD bit is zero.
  No need to check both bits are zero.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5068 c046a42c-6fe2-441c-8c8c-71466251a162
      06afe2c8
    • A
      [sh4] memory mapped TLB entries · 29e179bc
      由 aurel32 提交于 
      SH4 MMU's memory mapped TLB feature is implemented.
SH-Linux seems to write to memory mapped TLB to invalidate a TLB entry,
but does not to read it. So only memory write feature is implemented.
Work on memory read feature is left.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5067 c046a42c-6fe2-441c-8c8c-71466251a162
      29e179bc
    • A
      [sh4] delay slot bug fix · 274a9e70
      由 aurel32 提交于 
      Two bugs about delay slot handlings are fixed.

- After an exception occurred in delay slot, the branch instruction
  before delay slot should be executed again. To judge such re-execution
  is necessery or not, delay slot status is kept in SH4 CPU data structure.
- When a branch instruction is placed at the end of memory segment,
  the delay slot is placed at the start of next memory segment.
  It means delay slot comes to the start of a translation block.
  In such occasion, DELAY_SLOT_CLAREME flag is used to transmit status
  between translation blocks. When an exception occurs on this kind of
  delay slot, DELAY_SLOT_CLEARME flag cause a status confusion in exception
  handling. DELAY_SLOT_CLEARME flag should be cleared on exceptions.

And some items are added to CPU status dump.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5066 c046a42c-6fe2-441c-8c8c-71466251a162
      274a9e70
    • A
      [sh4] sleep instruction · 833ed386
      由 aurel32 提交于 
      This patch adds sleep instruction.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5065 c046a42c-6fe2-441c-8c8c-71466251a162
      833ed386