- 22 7月, 2016 9 次提交
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由 Peter Xu 提交于
Changing the original MSIMessage parameter in kvm_irqchip_add_msi_route into the vector number. Vector index provides more information than the MSIMessage, we can retrieve the MSIMessage using the vector easily. This will avoid fetching MSIMessage every time before adding MSI routes. Meanwhile, the vector info will be used in the coming patches to further enable gsi route update notifications. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
This patch enables SID validation. Invalid interrupts will be dropped. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Jan Kiszka 提交于
As neither QEMU nor KVM support more than 255 CPUs so far, this is simple: we only need to switch the destination ID translation in vtd_remap_irq_get if EIME is set. Once CFI support is there, it will have to take EIM into account as well. So far, nothing to do for this. This patch allows to use x2APIC in split irqchip mode of KVM. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> [use le32_to_cpu() to retrieve dest_id] Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Let IOAPIC the first consumer of x86 IOMMU IEC invalidation notifiers. This is only used for split irqchip case, when vIOMMU receives IR invalidation requests, IOAPIC will be notified to update kernel irq routes. For simplicity, we just update all IOAPIC routes, even if the invalidated entries are not IOAPIC ones. Since now we are creating IOMMUs using "-device" parameter, IOMMU device will be created after IOAPIC. We need to do the registration after machine done by leveraging machine_done notifier. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
This patch introduces x86 IOMMU IEC (Interrupt Entry Cache) invalidation notifier list. When vIOMMU receives IEC invalidate request, all the registered units will be notified with specific invalidation requests. Intel IOMMU is the first provider that generates such a event. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
In split irqchip mode, IOAPIC is working in user space, only update kernel irq routes when entry changed. When IR is enabled, we directly update the kernel with translated messages. It works just like a kernel cache for the remapping entries. Since KVM irqfd is using kernel gsi routes to deliver interrupts, as long as we can support split irqchip, we will support irqfd as well. Also, since kernel gsi routes will cache translated interrupts, irqfd delivery will not suffer from any performance impact due to IR. And, since we supported irqfd, vhost devices will be able to work seamlessly with IR now. Logically this should contain both vhost-net and vhost-user case. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> [move trace-events lines into target-i386/trace-events] Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Abstract IOAPIC entry parsing logic into a helper function. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
This patch translates all IOAPIC interrupts into MSI ones. One pseudo ioapic address space is added to transfer the MSI message. By default, it will be system memory address space. When IR is enabled, it will be IOMMU address space. Currently, only emulated IOAPIC is supported. Idea suggested by Jan Kiszka and Rita Sinha in the following patch: https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.htmlSigned-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Michael S. Tsirkin 提交于
Correct and portable in theory, but triggers warnings with older gcc versions when -Wmissing-braces is enabled. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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- 21 7月, 2016 19 次提交
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由 Peter Xu 提交于
This patch enables interrupt remapping for PCI devices. To play the trick, one memory region "iommu_ir" is added as child region of the original iommu memory region, covering range 0xfeeXXXXX (which is the address range for APIC). All the writes to this range will be taken as MSI, and translation is carried out only when IR is enabled. Idea suggested by Paolo Bonzini. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Adding translation fault definitions for interrupt remapping. Please refer to VT-d spec section 7.1. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Handle writting to IRE bit in global command register. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Defined Interrupt Remap Table Address register to store IR table pointer. Also, do proper handling on global command register writes to store table pointer and its size. One more debug flag "DEBUG_IR" is added for interrupt remapping. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
To enable interrupt remapping for intel IOMMU device, each IOAPIC device in the system reported via ACPI MADT must be explicitly enumerated under one specific remapping hardware unit. This patch adds the root-complex IOAPIC into the default DMAR device. Please refer to VT-d spec 8.3.1.1 for more information. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Enable IR in IOMMU Extended Capability register. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Queued invalidation is required for IR. This patch add basic support for interrupt cache invalidate requests. Since we currently have no IR cache implemented yet, we can just skip all interrupt cache invalidation requests for now. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
In ACPI DMA remapping report structure, enable INTR flag when specified. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Adding one property for intel-iommu devices to specify whether we should support interrupt remapping. By default, IR is disabled. To enable it, we should use (take Intel IOMMU as example): -device intel_iommu,intremap=on This property can be shared by Intel and future AMD IOMMUs. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Instead of searching the device tree every time, one static variable is declared for the default system x86 IOMMU device. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Peter Xu 提交于
Introducing parent class for intel-iommu devices named "x86-iommu". This is preparation work to abstract shared functionalities out from Intel and AMD IOMMUs. Currently, only the parent class is introduced. It does nothing yet. Signed-off-by: NPeter Xu <peterx@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Marcel Apfelbaum 提交于
'Realize' the PCI root bus manually since the 'realize' mechanism does not propagate to child devices yet. Signed-off-by: NMarcel Apfelbaum <marcel@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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由 Marcel Apfelbaum 提交于
'Realize' the PCI root bus manually since the 'realize' mechanism does not propagate to child devices yet. Signed-off-by: NMarcel Apfelbaum <marcel@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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由 Marcel Apfelbaum 提交于
Delay the host-bridge 'realization' until the PCI root bus is attached. Signed-off-by: NMarcel Apfelbaum <marcel@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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由 Marcel Apfelbaum 提交于
Create and connect the PCI root bus to the host bridge before the later is 'realized'. Signed-off-by: NMarcel Apfelbaum <marcel@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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由 Marcel Apfelbaum 提交于
Delay the host-bridge 'realization' until the PCI root bus is attached. Signed-off-by: NMarcel Apfelbaum <marcel@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: NLeon Alrae <leon.alrae@imgtec.com> Tested-by: NLeon Alrae <leon.alrae@imgtec.com>
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由 Marcel Apfelbaum 提交于
Delay the host-bridge 'realization' until the PCI root bus is attached. Signed-off-by: NMarcel Apfelbaum <marcel@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Tested-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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由 Stefan Hajnoczi 提交于
object_get_canonical_path_component() returns a heap-allocated string that must be freed using g_free(). Reported-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NXiao Guangrong <guangrong.xiao@linux.intel.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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- 19 7月, 2016 3 次提交
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由 Evgeny Yakovlev 提交于
The following sequence of tests discovered a problem in IDE emulation: 1. Send DMA write to IDE device 0 2. Send CMD_FLUSH_CACHE to same IDE device which will be failed by block layer using blkdebug script in tests/ide-test:test_retry_flush When doing DMA request ide/core.c will set s->retry_unit to s->unit in ide_start_dma. When dma completes ide_set_inactive sets retry_unit to -1. After that ide_flush_cache runs and fails thanks to blkdebug. ide_flush_cb calls ide_handle_rw_error which asserts that s->retry_unit == s->unit. But s->retry_unit is still -1 after previous DMA completion and flush does not use anything related to retry. This patch restricts retry unit assertion only to ops that actually use retry logic. Signed-off-by: NEvgeny Yakovlev <eyakovlev@virtuozzo.com> Signed-off-by: NDenis V. Lunev <den@openvz.org> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Message-id: 1468870792-7411-3-git-send-email-den@openvz.org CC: Kevin Wolf <kwolf@redhat.com> CC: Max Reitz <mreitz@redhat.com> CC: Stefan Hajnoczi <stefanha@redhat.com> CC: Fam Zheng <famz@redhat.com> CC: John Snow <jsnow@redhat.com> Signed-off-by: NJohn Snow <jsnow@redhat.com>
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由 Evgeny Yakovlev 提交于
Code to set and clear state associated with retry in moved into ide_set_retry and ide_clear_retry to make adding retry setups easier. Signed-off-by: NEvgeny Yakovlev <eyakovlev@virtuozzo.com> Signed-off-by: NDenis V. Lunev <den@openvz.org> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Message-id: 1468870792-7411-2-git-send-email-den@openvz.org CC: Kevin Wolf <kwolf@redhat.com> CC: Max Reitz <mreitz@redhat.com> CC: Stefan Hajnoczi <stefanha@redhat.com> CC: Fam Zheng <famz@redhat.com> CC: John Snow <jsnow@redhat.com> Signed-off-by: NJohn Snow <jsnow@redhat.com>
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由 Alex Williamson 提交于
QEMU supports ARI on downstream ports and assigned devices may support ARI in their extended capabilities. The endpoint ARI capability specifies the next function, such that the OS doesn't need to walk each possible function, however this next function is relative to the host, not the guest. This leads to device discovery issues when we combine separate functions into virtual multi-function packages in a guest. For example, SR-IOV VFs are not enumerated by simply probing the function address space, therefore the ARI next-function field is zero. When we combine multiple VFs together as a multi-function device in the guest, the guest OS identifies ARI is enabled, relies on this next-function field, and stops looking for additional function after the first is found. Long term we should expose the ARI capability to the guest to enable configurations with more than 8 functions per slot, but this requires additional QEMU PCI infrastructure to manage the next-function field for multiple, otherwise independent devices. In the short term, hiding this capability allows equivalent functionality to what we currently have on non-express chipsets. Signed-off-by: NAlex Williamson <alex.williamson@redhat.com> Reviewed-by: NMarcel Apfelbaum <marcel@redhat.com>
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- 18 7月, 2016 9 次提交
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由 Cao jin 提交于
No need duplicate the judgment, there is one in function entry. Cc: Stefan Hajnoczi <stefanha@redhat.com> Cc: Kevin Wolf <kwolf@redhat.com> Cc: Max Reitz <mreitz@redhat.com> Signed-off-by: NCao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: NFam Zheng <famz@redhat.com> Message-id: 1468814749-14510-1-git-send-email-caoj.fnst@cn.fujitsu.com Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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由 Jason Wang 提交于
e1000e needs net_tx_pkt.o and net_rx_pkt.o too. Cc: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com> Cc: Leonid Bloch <leonid.bloch@ravellosystems.com> Signed-off-by: NJason Wang <jasowang@redhat.com>
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由 Paolo Bonzini 提交于
This is not dereferencing the pointer, and instead checking only the value of the pointer. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NJason Wang <jasowang@redhat.com>
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由 Bharata B Rao 提交于
If CPU core addition or removal is allowed in random order leading to holes in the core id range (and hence in the cpu_index range), migration can fail as migration with holes in cpu_index range isn't yet handled correctly. Prevent this situation by enforcing the addition in contiguous order and removal in LIFO order so that we never end up with holes in cpu_index range. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
This ioctl() call to VFIO_IOMMU_SPAPR_TCE_REMOVE was left over from an earlier version of the code and has since been folded into vfio_spapr_remove_window(). It wasn't caught because although the argument structure has been removed, the libc function remove() means this didn't trigger a compile failure. The ioctl() was also almost certain to fail silently and harmlessly with the bogus argument, so this wasn't caught in testing. Suggested-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
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由 Mark Cave-Ayland 提交于
Otherwise MacOS 9 hangs upon shutdown. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Mark Cave-Ayland 提交于
This fixes MacOS 9 whereby it continually flushes and polls the status bits until they are set to indicate a successful flush. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Mark Cave-Ayland 提交于
The values to read/write to/from physical memory are copied directly to the physical address with no endian swapping required. Also add some extra information to debugging output while we are here. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Mark Cave-Ayland 提交于
The current DBDMA command is stored in little-endian format, so make sure we convert it to match our CPU when updating the DBDMA_CMDPTR_LO register. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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