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qemu

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  1. 15 1月, 2011 12 次提交
  3. 14 1月, 2011 1 次提交
  5. 13 1月, 2011 9 次提交
  7. 12 1月, 2011 8 次提交
  9. 11 1月, 2011 4 次提交
  11. 10 1月, 2011 6 次提交
    • A
      slirp: fix unaligned access in bootp code · 8aaf42ed
      由 Aurelien Jarno 提交于 
      Slirp code tries to be smart an avoid data copy by using pointer to
the data. This solution leads to unaligned access, in this case
preq_addr, which is a 32-bit long structure. There is no real point
of avoiding data copy in a such case, as the value itself is smaller
or the same size as a pointer.

The patch replaces pointers to the preq_addr structure by the strcture
itself, and use the address 0.0.0.0 if no address has been requested
(this is not a valid address in such a request). It compares it with
htonl(0L) for correctness reasons, in case a code checker look for such
mistakes. It also uses memcpy() for copying the data, which takes care
of alignement issues.

This fixes an unaligned access on IA64 host while requesting a DHCP
address.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      8aaf42ed
    • A
      bswap.h: add cpu_to_be64wu() · 102c2976
      由 Aurelien Jarno 提交于 
      Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      102c2976
    • A
      tcg/arm: improve constant loading · 0f11f25a
      由 Aurelien Jarno 提交于 
      Improve constant loading in two ways:
- On all ARM versions, it's possible to load 0xffffff00 = -0x100 using
  the mvn rd, #0. Fix the conditions.
- On <= ARMv6 versions, where movw and movt are not available, load the
  constants using mov and orr with rotations depending on the constant
  to load. This is very useful for example to load constants where the
  low byte is 0. This reduce the generated code size by about 7%.

Also fix the coding style at the same time.

Cc: Andrzej Zaborowski <balrog@zabor.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      0f11f25a
    • A
      tcg/ia64: remove an unnecessary stop bit · a3e28aa5
      由 Aurelien Jarno 提交于 
      Spotted by Richard Henderson.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      a3e28aa5
    • A
      target-sh4: improve TLB · 829a4927
      由 Aurelien Jarno 提交于 
      SH4 is using 16-bit instructions which means most of the constants are
loaded through a constant pool at the end of the subroutine. The same
memory page is therefore accessed in exec and read mode.

With the current implementation, a QEMU TLB entry is set to read or
read/write mode after an UTLB search and to exec mode after an ITLB
search, which causes a lot of TLB exceptions to switch from read or
read/write to exec and vice versa.

This patch optimizes that by already setting the QEMU TLB entry in read
or read/write mode when an UTLB entry is copied into ITLB (during an
ITLB miss). This improve the emulation speed by about 14%.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      829a4927
    • A
      target-sh4: implement writes to mmaped ITLB · c0f809c4
      由 Aurelien Jarno 提交于 
      Some Linux kernels seems to implement ITLB/UTLB flushing through by
writing all TLB entries through the memory mapped interface instead
of writing one to MMUCR.TI.

Implement memory mapped ITLB write interface so that such kernels can
boot. This fixes https://bugs.launchpad.net/bugs/700774 .
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      c0f809c4