Use PRIx64 to print 64 bit values to avoid truncation
on 32 bit hosts.
Reviewed-by: NAnthony Liguori <aliguori@us.ibm.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

* origin/master:
  fix BCD mask for date (Solaris 2.5 guest hang fix)

Fix BCD mask for date. The most visible effect of this patch is
Solaris 2.5.1 doesn't hang at boot if the day of month is >21.
Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

* origin/master: (27 commits)
  target-arm: Move reset handling to arm_cpu_reset
  target-arm: Drop cpu_reset_model_id()
  target-arm: Move cache ID register setup to cpu specific init fns
  target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset
  target-arm: Move feature register setup to per-CPU init fns
  target-arm: Move iWMMXT wCID reset to cpu_state_reset
  target-arm: Drop JTAG_ID documentation
  target-arm: Move SCTLR reset value setup to per cpu init fns
  target-arm: Move CTR setup to per cpu init fns
  target-arm: Move MVFR* setup to per cpu init fns
  target-arm: Move FPSID config to cpu init fns
  target-arm: Move feature bit settings to CPU init fns
  target-arm: Add QOM subclasses for each ARM cpu implementation
  target-arm: remind to keep arm features in sync with linux-user/elfload.c
  tci: GETPC() macro must return an uintptr_t
  gdbstub: Synchronize CPU state unconditionally in gdb_set_cpu_pc
  softfloat: make USE_SOFTFLOAT_STRUCT_TYPES compile
  target-xtensa: add tests for LOOPNEZ and LOOPGTZ
  target-xtensa: fix LOOPNEZ/LOOPGTZ translation
  qtest: add m48t59 tests for Sparc
  ...

* sstabellini/build_fix:
  xen: add a dummy xc_hvm_inject_msi for Xen < 4.2
  xen,configure: detect Xen 4.2

* stefanha/trivial-patches:
  Add .gitignore for tests/
  e1000: Fix spelling (segmentaion -> segmentation) in debug output
  spice-qemu-char.c: Show what name is unsupported
  pflash_cfi01: remove redundant line
  qxl: Add missing GCC_FMT_ATTR and fix format specifier
  fix block_job_set_speed name in documentation
  error.c: don't return value for void function

* mdroth/qga-pull-4-19-12:
  qemu-ga: fix help output
  qemu-ga: generate missing stubs for fsfreeze

* bonzini/nbd-next:
  nbd: obey FUA on reads
  nbd: do not include block_int.h
  nbd: do not block in nbd_wr_sync if no data at all is available
  nbd: consistently return negative errno values
  nbd: consistently check for <0 or >=0
  nbd: consistently use ssize_t
  nbd: avoid out of bounds access to recv_coroutine array

* bonzini/scsi-next:
  scsi: add SANITIZE command
  SCSI emulation: should tell the guest that we actually support thin provisioning
  SCSI emulation: Support unmap via WRITE_SAME_10.
  scsi: advertise DPOFUA
  scsi: small refactoring of MMC mode-sense
  scsi: support FUA on reads
  scsi: add a started field to SCSIDiskReq
  scsi: force unit access on VERIFY
  scsi: add support for FUA on writes
  scsi: move scsi_flush_complete around
  scsi: make code more homogeneous in AIO callback functions
  scsi: add missing test for cancelled request
  virtio-scsi: add multiqueue capability
  virtio: add virtio_queue_get_id
  virtio-scsi: prepare migration format for multiqueue
  scsi: fix memory leak

* stefanha/tracing:
  tracetool: handle DTrace keywords 'in', 'next', 'self'
  tracetool: Add MAINTAINERS info
  tracetool: Add support for the 'dtrace' backend
  tracetool: Add support for the 'ust' backend
  tracetool: Add support for the 'simple' backend
  tracetool: Add support for the 'stderr' backend
  tracetool: Add module for the 'h' format
  tracetool: Add module for the 'c' format
  tracetool: Rewrite infrastructure as python modules

Now that cpu_reset_model_id() has gone we can move the
reset code over to the class reset function and have cpu_state_reset
simply do a reset on the CPU QOM object.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>

cpu_reset_model_id() is now empty and we can remove it.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>

Move cache ID register reset out of cpu_reset_model_id() by
creating a field for the reset value in ARMCPU and setting it
up in the cpu specific init functions.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>

Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset;
since these registers are only accessible on CPUs with the
OMAPCP feature set there's no need to guard this reset with
either a CPUID or feature bit check.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NAndreas Färber <afaerber@suse.de>

Move feature register value setup to per-CPU init functions.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>

Move the iWMMXT wCID reset to cpu_state_reset(). Since
we use the same value for all CPUs with this feature
(with the major/minor revision fields set to the QEMU
specific 'Q' value) there's no need to create an ARMCPU
field just for this.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NAndreas Färber <afaerber@suse.de>

None of the machines in QEMU offer a JTAG debug interface, so this info
was unused. Further, the PXA250 ID contradicts the February 2002
Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision.
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Move the reset value of SCTLR to ARMCPU, initialised in
the per-cpu init functions. It can then be reset by a
simple copy, and we can drop the code from cpu_reset_model_id().
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>

Move CTR (cache type register) value to an ARMCPU field
set up by per-cpu init fns.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>

Move the MVFR* VFP feature register values to ARMCPU,
so they are set up by the implementation-specific instance
init functions rather than in cpu_reset_model_id().
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>

Move the reset FPSID to the ARMCPU struct, and set it in the
per-implementation instance init function. At reset we then
just copy the reset value into the CPUARMState field.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>

Move the setting of the feature bits from cpu_reset_model_id()
to each CPU's instance init function. This requires us to move
the features field in CPUARMState so that it is not cleared
on reset.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>

Register subclasses for each ARM CPU implementation.

Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,
except for special value "any".

Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the
CPUID (aka MIDR, Main ID Register) value in the class.
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Signed-off-by: NBenoit Canet <benoit.canet@gmail.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm:
  versatiblepb: add NOR flash support
  hw/arm_mptimer: Reset the qemu_timer at reset
  versatilepb: add ds1338 rtc device
  realview: break out versatile i2c controller code

Change the data type of tci_tb_ptr, so GETPC() returns an
uintptr_t now (like for all other TCG targets).

This completes commit 20503968
and fixes builds with TCI.
Signed-off-by: NStefan Weil <sw@weilnetz.de>
Reviewed-by: NEric Blake <eblake@redhat.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Synchronize the CPU state via cpu_sychronize_state() unconditionally
in gdb_set_cpu_pc() rather than only in some of the target ifdef
ladder cases.

We can divide the CPUs into three categories:
 * non-KVM targets: no change of behaviour since we will use the
   kvm-stub.c no-op function.
 * i386 and s390: no change of behaviour since they were already
   calling this function
 * PPC (in KVM mode): this fixes an error: failing to synchronise
   was accidental and probably a bug.

This also paves the way for other targets (specifically ARM) which
can add KVM support in future without having to add another target
specific change to this bit of code.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

This change makes it compile and return the same value than the #undef one.
Signed-off-by: NJuan Quintela <quintela@redhat.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Acked-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Translation of LOOP instructions used to call LEND SR write handler to
update LEND and invalidate relevant TBs. Now that LEND SR write handler
ends TB, LOOPNEZ and LOOPGTZ generate wrong code (same as for simple
LOOP). Fix it by calling wsr_lend helper directly.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Add simple m48t59 qtests, enable test only for Sparc32
and Sparc64. On PPC, the device is behind PCI bus.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- add support for the 64MB NOR CFI01 flash available at
0x34000000 on the versatilepb board
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0225d/BBAJIHEC.html

- tested with barebox bootloader
Signed-off-by: NEric Bénard <eric@eukrea.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

On reset of the mpcore timer/watchdog block we need to
delete the qemu_timer in case it was running.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add ds1338 rtc attached on i2c.
Signed-off-by: NOskar Andero <oskar.andero@gmail.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

The versatile i2c controller implementation was separated to
its own file called versatile_i2c.c. This is done as a preparation
for adding i2c support to the versatilepb board.
Signed-off-by: NOskar Andero <oskar.andero@gmail.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

The new autotests in tests/ generate a number of files, both
executable and source, which are not caught by the existing .gitignore
files.  This patch adds a new .gitignore in tests/ which covers these.

[Changed 'rtc-test' to '*-test' so future tests do not need to be added
to .gitignore on a case-by-case basis.  Stefan]
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>

This was reported by https://bugs.launchpad.net/qemu/+bug/984476.

I also changed the case for 'error'.
Signed-off-by: NStefan Weil <sw@weilnetz.de>
Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>

Signed-off-by: NEduardo Elias Ferreira <edusf@linux.vnet.ibm.com>
Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>

Signed-off-by: NEric Bénard <eric@eukrea.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>

val is an uint64_t, therefore %d was not correct.
Signed-off-by: NStefan Weil <sw@weilnetz.de>
Acked-by: NGerd Hoffmann <kraxel@redhat.com>
Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>