- 19 10月, 2018 40 次提交
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由 Markus Armbruster 提交于
The previous commit changed vfio's warning messages from vfio warning: DEV-NAME: Could not frobnicate to warning: vfio DEV-NAME: Could not frobnicate To match this change, change error messages from vfio error: DEV-NAME: On fire to vfio DEV-NAME: On fire Note the loss of "error". If we think marking error messages that way is a good idea, we should mark *all* error messages, i.e. make error_report() print it. Cc: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Acked-by: NAlex Williamson <alex.williamson@redhat.com> Message-Id: <20181017082702.5581-7-armbru@redhat.com>
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由 Markus Armbruster 提交于
The vfio code reports warnings like error_report(WARN_PREFIX "Could not frobnicate", DEV-NAME); where WARN_PREFIX is defined so the message comes out as vfio warning: DEV-NAME: Could not frobnicate This usage predates the introduction of warn_report() & friends in commit 97f40301. It's time to convert to that interface. Since these functions already prefix the message with "warning: ", replace WARN_PREFIX by VFIO_MSG_PREFIX, so the messages come out like warning: vfio DEV-NAME: Could not frobnicate The next commit will replace ERR_PREFIX. Cc: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Acked-by: NAlex Williamson <alex.williamson@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> Message-Id: <20181017082702.5581-6-armbru@redhat.com>
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由 Markus Armbruster 提交于
Calling error_report() in a function that takes an Error ** argument is suspicious. Convert a few that are actually warnings to warn_report(). While there, split a warning consisting of multiple sentences to conform to conventions spelled out in warn_report()'s contract. Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Fam Zheng <famz@redhat.com> Cc: Wei Huang <wei@redhat.com> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Acked-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20181017082702.5581-5-armbru@redhat.com>
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由 Markus Armbruster 提交于
Calling error_report() in a function that takes an Error ** argument is suspicious. Convert a few that are actually warnings to warn_report(). While there, split warnings consisting of multiple sentences to conform to conventions spelled out in warn_report()'s contract, and improve a rather useless warning in sheepdog.c. Cc: Kevin Wolf <kwolf@redhat.com> Cc: Ronnie Sahlberg <ronniesahlberg@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Lieven <pl@kamp.de> Cc: Liu Yuan <namei.unix@gmail.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> Message-Id: <20181017082702.5581-4-armbru@redhat.com> Drop changes to "without an explicit read-only=on" warnings, because there's a series removing them pending. Also drop a cc: to a former Sheepdog maintainer. Reviewed-by: NKevin Wolf <kwolf@redhat.com>
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由 Markus Armbruster 提交于
Add a slight improvement of the Coccinelle semantic patch from commit 007b0657, and use it to clean up. It leaves dead Error * variables behind, cleaned up manually. Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alexander Graf <agraf@suse.de> Cc: Eric Blake <eblake@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> Acked-by: NDavid Gibson <david@gibson.dropbear.id.au> Message-Id: <20181017082702.5581-3-armbru@redhat.com>
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由 Markus Armbruster 提交于
From include/qapi/error.h: * Pass an existing error to the caller with the message modified: * error_propagate(errp, err); * error_prepend(errp, "Could not frobnicate '%s': ", name); Fei Li pointed out that doing error_propagate() first doesn't work well when @errp is &error_fatal or &error_abort: the error_prepend() is never reached. Since I doubt fixing the documentation will stop people from getting it wrong, introduce error_propagate_prepend(), in the hope that it lures people away from using its constituents in the wrong order. Update the instructions in error.h accordingly. Convert existing error_prepend() next to error_propagate to error_propagate_prepend(). If any of these get reached with &error_fatal or &error_abort, the error messages improve. I didn't check whether that's the case anywhere. Cc: Fei Li <fli@suse.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> Message-Id: <20181017082702.5581-2-armbru@redhat.com>
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由 Philippe Mathieu-Daudé 提交于
When using an incorrect backend for the debugcon, QEMU exits silently without any error indication, which is confusing. Add a message that the character backend is invalid. Signed-off-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20181011171254.32428-1-philmd@redhat.com> Reviewed-by: NMarc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com>
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由 Alberto Garcia 提交于
qerror.h contains leftovers from the now-defunct QError API. There's only a handful of string macros left, and no one is supposed to add anything else. The check-qerror.sh script was used to make sure that all definitions on the qerror.c and qerror.h files were sorted alphabetically. The former was removed three years ago, and the latter is now in a different location, so the script doesn't even work (as a matter of fact the alphabetical order was broken last time someone added a macro -also in 2015- and no one seemed to notice). There's no point in fixing this script so let's just remove it. The rogue macro is also moved to its correct location. Signed-off-by: NAlberto Garcia <berto@igalia.com> Message-Id: <20181017151738.20299-1-berto@igalia.com> Reviewed-by: NMarkus Armbruster <armbru@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com>
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由 Peter Maydell 提交于
Add a workaround for clang bug and remove misleading comment (sparc) # gpg: Signature made Thu 18 Oct 2018 20:00:17 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-3.1-pull-request: linux-user/sparc/signal.c: Remove unnecessary comment linux-user: Suppress address-of-packed-member warnings in __get/put_user_e Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
MIPS queue October 2018, part1, v2 # gpg: Signature made Thu 18 Oct 2018 19:39:00 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-october-2018-part1-v2: (28 commits) target/mips: Add opcodes for nanoMIPS EVA instructions target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> target/mips: Implement hardware page table walker for MIPS32 target/mips: Add reset state for PWSize and PWField registers target/mips: Add CP0 PWCtl register target/mips: Add CP0 PWSize register target/mips: Add CP0 PWField register target/mips: Add CP0 PWBase register target/mips: Add CP0 Config2 to DisasContext target/mips: Improve DSP R2/R3-related naming target/mips: Add availability control for DSP R3 ASE target/mips: Add bit definitions for DSP R3 ASE target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags) target/mips: Increase 'supported ISAs/ASEs' flag holder size target/mips: Add opcode values of MXU ASE target/mips: Add organizational chart of MXU ASE target/mips: Add assembler mnemonics list for MXU ASE target/mips: Add basic description of MXU ASE target/mips: Add a comment before each CP0 register section in cpu.h ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dimitrije Nikolic 提交于
Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE, LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NDimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Fix misplaced 'break' in handling of NM_SHRA_R_PH. Found by Coverity (CID 1395627). Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Matthew Fortune 提交于
Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> instructions. Their handling was permuted. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NMatthew Fortune <matthew.fortune@mips.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Yongbok Kim 提交于
Implement hardware page table walker. This implementation is limiter only to MIPS32. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NYongbok Kim <yongbok.kim@mips.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Yongbok Kim 提交于
Add reset state for PWSize and PWField registers. The reset state is different for pre-R6 and R6 (and post-R6) ISAa. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NYongbok Kim <yongbok.kim@mips.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Yongbok Kim 提交于
Add PWCtl register (CP0 Register 5, Select 6). The PWCtl register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: PWEn (31) - Hardware Page Table walker enable PWDirExt (30) - If 1, 4-th level implemented (MIPS64 only) XK (28) - If 1, walker handles xkseg (MIPS64 only) XS (27) - If 1, walker handles xsseg (MIPS64 only) XU (26) - If 1, walker handles xuseg (MIPS64 only) DPH (7) - Dual Page format of Huge Page support HugePg (6) - Huge Page PTE supported in Directory levels PSn (5..0) - Bit position of PTEvld in Huge Page PTE Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NYongbok Kim <yongbok.kim@mips.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Yongbok Kim 提交于
Add PWSize register (CP0 Register 5, Select 7). The PWSize register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: BDW (37..32) Base Directory index width (MIPS64 only) GDW (29..24) Global Directory index width UDW (23..18) Upper Directory index width MDW (17..12) Middle Directory index width PTW (11..6 ) Page Table index width PTEW ( 5..0 ) Left shift applied to the Page Table index Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NYongbok Kim <yongbok.kim@mips.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Yongbok Kim 提交于
Add PWField register (CP0 Register 5, Select 6). The PWField register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: MIPS64: BDI (37..32) - Base Directory index GDI (29..24) - Global Directory index UDI (23..18) - Upper Directory index MDI (17..12) - Middle Directory index PTI (11..6 ) - Page Table index PTEI ( 5..0 ) - Page Table Entry shift MIPS32: GDW (29..24) - Global Directory index UDW (23..18) - Upper Directory index MDW (17..12) - Middle Directory index PTW (11..6 ) - Page Table index PTEW ( 5..0 ) - Page Table Entry shift Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NYongbok Kim <yongbok.kim@mips.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Yongbok Kim 提交于
Add PWBase register (CP0 Register 5, Select 5). The PWBase register contains the Page Table Base virtual address. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NYongbok Kim <yongbok.kim@mips.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Add field corresponding to CP0 Config2 to DisasContext. This is needed for availability control via Config2 bits. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Do following replacements: ASE_DSPR2 -> ASE_DSP_R2 ASE_DSPR3 -> ASE_DSP_R3 MIPS_HFLAG_DSPR2 -> MIPS_HFLAG_DSP_R2 MIPS_HFLAG_DSPR3 -> MIPS_HFLAG_DSP_R3 check_dspr2() -> check_dsp_r2() check_dspr3() -> check_dsp_r3() and several other similar minor replacements. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Add infrastructure for availability control for DSP R3 ASE MIPS instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but this is likely to be changed in near future. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Add DSP R3 ASE related bit definition for insn_flags and hflags. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Philippe Mathieu-Daudé 提交于
Distribute bits 56-63 vendor-specific ASEs as follows: - bits 0-31 MIPS base instruction sets - bits 32-47 MIPS ASEs - bits 48-55 vendor-specific base instruction sets - bits 56-63 vendor-specific ASEs Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Philippe Mathieu-Daudé 提交于
Increase the size of insn_flags holder size to 64 bits. This is needed for future extensions since existing bits are almost all used. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Aleksandar Markovic 提交于
Add opcode values for all instructions in MXU ASE. Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Aleksandar Markovic 提交于
Add a comment that contains an organizational chart of MXU ASE instructions. Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Aleksandar Markovic 提交于
Add a comment that contains a list all MXU instructions, expressed in assembler mnemonics. Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Aleksandar Markovic 提交于
Add a comment that contains a basic description of MXU ASE. Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Aleksandar Markovic 提交于
Add a comment before each CP0 register section in CPUMIPSState definition, thus visually separating these sections. Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Aleksandar Markovic 提交于
Add a comment with an overview of CP0 registers close to the definition of their corresponding fields in CPUMIPSState. Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Add infrastructure for handling MIPS-specific prctl(). This is, for now, just an empty placeholder. The real handling will be implemented in subsequent patches. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Add MIPS-specific prctl() options TARGET_PR_SET_FP_MODE and TARGET_PR_SET_FP_MODE. These values are essentially copied from linux kernel header include/uapi/linux/prctl.h. This is done in a way consistent with a similar case of aarch64-specific prctl() options TARGET_PR_SVE_SET_VL and TARGET_PR_SVE_GET_VL. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Fredrik Noring 提交于
Regarding R5900 CPU, some sources indicate that the Emotion Engine ISA/ASE was designed by Toshiba and licensed to Sony. Others sources claim it was a joint effort. It therefore makes sense to refer to the CPU as "Toshiba/Sony R5900". Also, remove and "'s" in the line for some other CPU, for the sake of consistency. Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reported-by: NMaciej W. Rozycki <macro@linux-mips.org> Signed-off-by: NFredrik Noring <noring@nocrew.org> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Add Mips_elf_abiflags_v0 structure to elf.h. The source of information is kernel header arch/mips/include/asm/elf.h. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Add MIPS_ABI_FP_XXX constants to elf.h. The source of information is kernel header arch/mips/include/asm/elf.h. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Stefan Markovic 提交于
Fix existing and add missing PT_MIPS_XXX constants in elf.h. This is copied from kernel header arch/mips/include/asm/elf.h. Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Aleksandar Markovic 提交于
Yongbok Kim used two email adresses for QEMU contributions - his company changed its ownership/name. Reviewed-by: NStefan Markovic <smarkovic@wavecomp.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com>
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由 Peter Maydell 提交于
Remove a comment suggesting that we need to call tb_flush() after writing the SPARC signal frame trampoline insns. This isn't necessary in QEMU, because (even if the guest architecture requires explicit icache maintenance) we ensure that memory writes result in invalidation of translated code from that memory. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-Id: <20181009184017.15675-1-peter.maydell@linaro.org> Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
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由 Peter Maydell 提交于
Our __get_user_e() and __put_user_e() macros cause newer versions of clang to generate false-positive -Waddress-of-packed-member warnings if they are passed the address of a member of a packed struct (see https://bugs.llvm.org/show_bug.cgi?id=39113). Suppress these using the _Pragma() operator. Unfortunately _Pragma() support in gcc is broken in some gcc versions and in some usage contexts, so we limit the pragma usage here to clang. To put in the pragmas we need to convert the macros from expressions to statements, but all the callsites effectively treat them as statements already so this is OK. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-Id: <20181009161814.21257-1-peter.maydell@linaro.org> Signed-off-by: NLaurent Vivier <laurent@vivier.eu>
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