- 16 10月, 2011 33 次提交
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由 Jan Kiszka 提交于
Introduce a reference to the slave PIC for the few cases we need to access it without a proper pointer at hand and drop PicState2. We could even live without slave_pic if we had a better way of modeling the cascade bus the PICs are attached to (in addition to the ISA bus). Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
This reflects how real PICs indentify their role (in non-buffered mode): Pass the state of the /SP input on pic_init and use it instead of pics_state to differentiate between master and slave mode. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
There is nothing in the i8259 spec that justifies the special pic_intack_read. At least the Linux PREP kernels configure the PICs properly so that pic_read_irq returns identical values, and setting read_reg_select in PIC0 cannot be derived from any special i8259 mode. So switch ppc_prep to pic_read_irq and drop the now unused PIC code. CC: Andreas Färber <andreas.faerber@web.de> Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
Drop redundant local address variable. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
This was probably never used so far: According to the spec, polling means ack'ing the pending IRQ and setting its corresponding bit in isr. Moreover, we have to signal a pending IRQ via bit 7 of the returned value, and we must not return a spurious IRQ if none is pending. This implements the poll command without the help of pic_poll_read which is left untouched as pic_intack_read is still using it. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
This converts pic_update_irq to work against a single PIC instead of the complete cascade. Along this change, the required update after pic_set_irq1 is now moved into that function. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
The ELCR is actually part of the chipset but we model it here for simplicity reasons. The PIIX3 clears the ELCR on reset, which was once broken by 4dbe19e1. Fix this by splitting up pic_init_reset from pic_reset and clearing the register in the latter. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
MIPS and PPC users of the i8259 output signal expect us to report state updates also after reset. As no consumer (including the master PIC) can misinterpret the deassert as an activation event, it is safe to simply update the IRQ state after reset. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
As we want to move the IRQ update to pic_intack, ordering matters: the slave ack must be executed before the master ack to avoid missing further pending slave IRQs. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
If pic_poll_read finds no pending IRQ and return a spurious one instead, no PIC state is changed, thus we do not need to call pic_update_irq. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
As a first step towards more generic master-slave support, remove parent_irq in favor of a per-PIC output interrupt line. The slave's line is attached to IRQ2 of the master, but it remains unused for now. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
We are about to call the latter from the former. No functional changes. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
The compiler is smarter in choosing the right optimization. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
The master PIC is connected to the LINTIN0 of the APICs. As the APIC currently does not track the state of that line, we have to ask the PIC to reinject its IRQ after the CPU picked up an event from the APIC. This introduces pic_get_output to read the master PIC IRQ line state without changing it. The APIC uses this function to decide if a PIC IRQ should be reinjected on apic_update_irq. This reflects better how the real hardware works. The patch fixes some failures of the kvm unit tests apic and eventinj by allowing to enable the proper CPU IRQ deassertion when the guest masks some pending IRQs at PIC level. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
Will be required when we no longer let i8259_init allocate the PIC IRQs but convert that chips to qdev. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
The ISA bus IRQ range is 0..15. What isa_irq_handler and IsaIrqState are actually dealing with are the Global System Interrupts. Refactor the code to clarify this. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
IsaIrqState::ioapic is always non-NULL. Probably, the concrete qemu_irq was supposed to be tested, but that's already done by qemu_set_irq. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
These boards carry similar hardware: SDRAM (48M for LX110, 64M for LX60, 96M for LX200), 16 Mbyte FLASH, FPGA, 10/100 Mbps Ethernet PHY and 16550 UART. FPGA may be loaded with almost any Tensilica processor. It is also used to implement Ethernet MAC, e.g. OpenCores 10/100 Mbps Ethernet MAC and LED/DIP switches access. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
This is OpenCores Ethernet MAC + subset of National Semiconductors DP83838C PHY. OpenCores Ethernet MAC project: http://opencores.org/project,ethmacSigned-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
This is to get aligned with the linux name for this machine. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
This is FSF big endian core implemented through linux overlay. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
This is Diamond 232L Standard Core Rev.B (LE), implemented through linux/gdb overlay. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
Introduce overlay_tool.h that defines core configuration blocks from data available in the linux architecture variant overlay. Overlay data is automatically generated in the core configuration process by Tensilica tools and can be directly converted to qemu xtensa core description by overlay_tool.h Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
Xtensa cores may have different mapping of external interrupt pins to internal IRQ numers. Implement API to acquire core IRQ by its external interrupt number. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
- add separate options for each operation in the MISC_OP; - add an option for MULSH/MULUH; - put S32C1I under conditional store option. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
See ISA, 4.3.7 for the details. - add ACC and MR special registers; - implement MAC16 and all inner MAC* opcode groups. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
We flush coalesced MMIO in the device models now, and VNC - for which this was once introduced - is also fine without it as it has its own refresh timer. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
This is conceptually cleaner and will allow us to drop the nographic timer. Moreover, it will be mandatory to fully exploit future per-device coalesced MMIO rings. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 15 10月, 2011 1 次提交
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由 Anthony Liguori 提交于
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- 14 10月, 2011 6 次提交
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由 Anthony Liguori 提交于
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由 Anthony Liguori 提交于
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由 Anthony Liguori 提交于
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由 Stefan Hajnoczi 提交于
Commit cd74d83345e0e3b708330ab8c4cd9111bb82cda6 ("block: switch bdrv_read()/bdrv_write() to coroutines") removed the bdrv_has_async_rw() callers. This patch removes bdrv_has_async_rw() since it is no longer used. Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: NKevin Wolf <kwolf@redhat.com>
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由 Stefan Hajnoczi 提交于
There is no need to emulate .bdrv_read()/.bdrv_write() since these interfaces are only called if aio and coroutine interfaces are not present. All valid BlockDrivers must implement either sync, aio, or coroutine interfaces. Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: NKevin Wolf <kwolf@redhat.com>
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由 Stefan Hajnoczi 提交于
The raw format delegates all operations to bs->file (the protocol). Previously this block driver exposed both sync and aio interfaces. Since the block layer now works in terms of coroutines, expose the coroutine interfaces and drop the others. This avoids unnecessary emulation of sync and aio interfaces. Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: NKevin Wolf <kwolf@redhat.com>
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