1. 19 5月, 2016 1 次提交
  2. 23 3月, 2016 1 次提交
  3. 23 2月, 2016 1 次提交
  4. 10 11月, 2015 2 次提交
  5. 06 7月, 2015 1 次提交
    • P
      Stop including qemu-common.h in memory.h · fba0a593
      Peter Maydell 提交于
      Including qemu-common.h from other header files is generally a bad
      idea, because it means it's very easy to end up with a circular
      dependency. For instance, if we wanted to include memory.h from
      qom/cpu.h we'd end up with this loop:
       memory.h -> qemu-common.h -> cpu.h -> cpu-qom.h -> qom/cpu.h -> memory.h
      
      Remove the include from memory.h. This requires us to fix up a few
      other files which were inadvertently getting declarations indirectly
      through memory.h.
      
      The biggest change is splitting the fprintf_function typedef out
      into its own header so other headers can get at it without having
      to include qemu-common.h.
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      Message-Id: <1435933104-15216-1-git-send-email-peter.maydell@linaro.org>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      fba0a593
  6. 12 6月, 2015 1 次提交
  7. 28 4月, 2015 1 次提交
  8. 05 3月, 2015 1 次提交
  9. 03 11月, 2014 1 次提交
  10. 19 6月, 2014 1 次提交
  11. 17 6月, 2014 1 次提交
  12. 11 2月, 2014 9 次提交
  13. 20 12月, 2013 1 次提交
    • A
      roms: Flush icache when writing roms to guest memory · 582b55a9
      Alexander Graf 提交于
      We use the rom infrastructure to write firmware and/or initial kernel
      blobs into guest address space. So we're basically emulating the cache
      off phase on very early system bootup.
      
      That phase is usually responsible for clearing the instruction cache for
      anything it writes into cachable memory, to ensure that after reboot we
      don't happen to execute stale bits from the instruction cache.
      
      So we need to invalidate the icache every time we write a rom into guest
      address space. We do not need to do this for every DMA since the guest
      expects it has to flush the icache manually in that case.
      
      This fixes random reboot issues on e5500 (booke ppc) for me.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      582b55a9
  14. 13 12月, 2013 1 次提交
    • A
      roms: Flush icache when writing roms to guest memory · a94b36dd
      Alexander Graf 提交于
      We use the rom infrastructure to write firmware and/or initial kernel
      blobs into guest address space. So we're basically emulating the cache
      off phase on very early system bootup.
      
      That phase is usually responsible for clearing the instruction cache for
      anything it writes into cachable memory, to ensure that after reboot we
      don't happen to execute stale bits from the instruction cache.
      
      So we need to invalidate the icache every time we write a rom into guest
      address space. We do not need to do this for every DMA since the guest
      expects it has to flush the icache manually in that case.
      
      This fixes random reboot issues on e5500 (booke ppc) for me.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      a94b36dd
  15. 04 7月, 2013 2 次提交
  16. 28 6月, 2013 1 次提交
  17. 27 6月, 2013 1 次提交
  18. 29 5月, 2013 2 次提交
  19. 25 5月, 2013 3 次提交
  20. 19 12月, 2012 2 次提交
  21. 02 11月, 2012 1 次提交
  22. 23 10月, 2012 1 次提交
    • A
      Rename target_phys_addr_t to hwaddr · a8170e5e
      Avi Kivity 提交于
      target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
      reserved) and its purpose doesn't match the name (most target_phys_addr_t
      addresses are not target specific).  Replace it with a finger-friendly,
      standards conformant hwaddr.
      
      Outstanding patchsets can be fixed up with the command
      
        git rebase -i --exec 'find -name "*.[ch]"
                              | xargs s/target_phys_addr_t/hwaddr/g' origin
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      a8170e5e
  23. 05 10月, 2012 1 次提交
  24. 02 7月, 2012 2 次提交
  25. 05 6月, 2012 1 次提交