提交 · ba87719cd267e6f07b17f6cda08246bf483146d4 · openeuler / qemu

26 12月, 2018 33 次提交

tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi · ba87719c

由 Richard Henderson 提交于 11月 27, 2018

Pass this through to temp_sync.
Reviewed-by: NEmilio G. Cota <cota@braap.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

ba87719c

tcg: Add preferred_reg argument to temp_sync · 98b4e186

由 Richard Henderson 提交于 11月 27, 2018

Pass this through to tcg_reg_alloc.
Reviewed-by: NEmilio G. Cota <cota@braap.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

98b4e186

tcg: Add preferred_reg argument to temp_load · b722452a

由 Richard Henderson 提交于 11月 27, 2018

Pass this through to tcg_reg_alloc.
Reviewed-by: NEmilio G. Cota <cota@braap.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

b722452a

tcg: Add preferred_reg argument to tcg_reg_alloc · b016486e

由 Richard Henderson 提交于 11月 27, 2018

This new argument will aid register allocation by indicating how
the temporary will be used in future.  If the preference cannot
be satisfied, fall back to the constraints of the current insn.

Short circuit the preference when it cannot be satisfied or if
it does not further constrain the operation.

With an eye toward optimizing function call sequences, optimize
for the preferred_reg set containing a single register.

For the moment, all users pass 0 for preference.
Reviewed-by: NEmilio G. Cota <cota@braap.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

b016486e

tcg: Add reachable_code_pass · b4fc67c7

由 Richard Henderson 提交于 11月 26, 2018

Delete trivially dead code that follows unconditional branches and
noreturn helpers.  These can occur either via optimization or via
the structure of a target's translator following an exception.
Reviewed-by: NEmilio G. Cota <cota@braap.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

b4fc67c7

tcg: Reference count labels · d88a117e

由 Richard Henderson 提交于 11月 26, 2018

Increment when adding branches, and decrement when removing them.
Reviewed-by: NEmilio G. Cota <cota@braap.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

d88a117e

tcg: Add TCG_CALL_NO_RETURN · 15d74092

由 Richard Henderson 提交于 11月 26, 2018

Remember which helpers have been marked noreturn.
Reviewed-by: NEmilio G. Cota <cota@braap.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

15d74092

tcg: Renumber TCG_CALL_* flags · 3b50352b

由 Richard Henderson 提交于 11月 26, 2018

Previously, the low 4 bits were used for TCG_CALL_TYPE_MASK,
which was removed in 6a18ae2d.
Reviewed-by: NEmilio G. Cota <cota@braap.org>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

3b50352b

linux-user: Add safe_syscall for riscv64 host · b8c92c6d

由 Richard Henderson 提交于 12月 20, 2018

Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

b8c92c6d

disas/microblaze: Remove unused REG_SP macro · 11cee55f

由 Richard Henderson 提交于 11月 29, 2018

This causes a build error with debian sid, riscv64 host:

disas/microblaze.c:179: error: "REG_SP" redefined [-Werror]
 #define REG_SP  1 /* stack pointer */

In file included from /usr/include/signal.h:306,
                 from include/qemu/osdep.h:101,
                 from disas/microblaze.c:36:
/usr/include/riscv64-linux-gnu/sys/ucontext.h:36: note: this is the location of the previous definition
 # define REG_SP 2
Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

11cee55f

configure: Add support for building RISC-V host · c4f80543

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <52160afacecc5b109dc43a412fa3e74ddd6277fb.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

c4f80543

disas: Add RISC-V support · 91468b27

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <caa478c8987d6042434bb9582017cdf0ea192208.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

91468b27

tcg: Add RISC-V cpu signal handler · 464e447a

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <c445175310fa836b61fd862a55628907f0093194.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

464e447a

tcg/riscv: Add the target init code · 7a5549f2

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <dd6e439ab81883974b8fd91f904f6de26ab5d697.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

7a5549f2

tcg/riscv: Add the prologue generation and register the JIT · 92c041c5

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <c4d023127967a0217d8d1eabdf5de6c0e8f8c228.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

92c041c5

tcg/riscv: Add the out op decoder · bdf50381

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <7c47f00cb4a9a777120456e0704b4076a5d943ab.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

bdf50381

tcg/riscv: Add direct load and store instructions · 03a7d021

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <2e047a95c39c007c66cda024c095e29b0ac4c43e.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

03a7d021

tcg/riscv: Add slowpath load and store instructions · efbea94c

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <1a0a7e8f3347764f212c5efa5c07c9be17efdec6.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

efbea94c

tcg/riscv: Add branch and jump instructions · 15840069

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <c356657e627168d89cb5b012b7e21e4efbbe83f3.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

15840069

tcg/riscv: Add the add2 and sub2 instructions · 28ca738e

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <5665a57809e32b35775e8e98fdab898853af37b8.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

28ca738e

tcg/riscv: Add the out load and store instructions · 61535d49

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <d5d88ff29163788938368bbdbd18815d59cef6a0.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

61535d49

tcg/riscv: Add the extract instructions · 27fd6414

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <c4d2afba46efefa9388cf3205fcedbb9a5fa411f.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

27fd6414

tcg/riscv: Add the mov and movi instruction · 6cd2eda3

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <bd6a45c73a67b77ddaa2fe590a6bb8ee422b9683.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

6cd2eda3

tcg/riscv: Add the relocation functions · dfa8e74f

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <6ac4f4b0d5ea93cb0ee9a3b8b47ee9f7b3711494.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

dfa8e74f

tcg/riscv: Add the instruction emitters · bedf14e3

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <c740aca183675625bb9cf3ce7b9e8b9d431ca694.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

bedf14e3

tcg/riscv: Add the immediate encoders · 54a9ce0f

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <d54dc56303fd1b0d7ed53869de2dbb59b111c7ca.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

54a9ce0f

tcg/riscv: Add support for the constraints · 8ce23a13

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <dba7315e4e20e879933f72d47ccf98f1cc612b8a.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

8ce23a13

tcg/riscv: Add the tcg target registers · 505e75c5

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <6e43abaa64361d57b9bc9439820d0e7701f2d47e.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

505e75c5

tcg/riscv: Add the tcg-target.h file · fb1f70f3

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <a135ee1a88cd7bd08993a519d4d654da27785254.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

fb1f70f3

exec: Add RISC-V GCC poison macro · e4041f66

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <00d02e34f10b87fd61f8dc69ac93d1eb63df949c.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

e4041f66

linux-user: Add host dependency for RISC-V 64-bit · 511f3138

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <9d777f619840a8dd8e4f3834dcfc3bd28e052ccd.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

511f3138

linux-user: Add host dependency for RISC-V 32-bit · f936eac8

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <76f8f9383a766dbcade883e897dec8cfef669799.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

f936eac8

elf.h: Add the RISCV ELF magic numbers · 6d06fdd1

由 Alistair Francis 提交于 12月 19, 2018

Signed-off-by: NAlistair Francis <alistair.francis@wdc.com>
Signed-off-by: NMichael Clark <mjc@sifive.com>
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
Message-Id: <02fc0b3a733f5f08eb396bee5afd3d327941f0c9.1545246859.git.alistair.francis@wdc.com>
Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>

6d06fdd1

22 12月, 2018 7 次提交

Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging · 9b2e891e

由 Peter Maydell 提交于 12月 22, 2018

RDMA queue
 * Add support for RDMA MAD
 * Various fixes for the pvrdma backend

# gpg: Signature made Sat 22 Dec 2018 09:36:36 GMT
# gpg:                using RSA key 36D4C0F0CF2FE46D
# gpg: Good signature from "Marcel Apfelbaum <marcel.apfelbaum@zoho.com>"
# gpg:                 aka "Marcel Apfelbaum <marcel@redhat.com>"
# gpg:                 aka "Marcel Apfelbaum <marcel.apfelbaum@gmail.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: B1C6 3A57 F92E 08F2 640F  31F5 36D4 C0F0 CF2F E46D

* remotes/marcel/tags/rdma-pull-request: (31 commits)
  pvrdma: check return value from pvrdma_idx_ring_has_ routines
  rdma: remove unused VENDOR_ERR_NO_SGE macro
  pvrdma: release ring object in case of an error
  pvrdma: check number of pages when creating rings
  pvrdma: add uar_read routine
  rdma: check num_sge does not exceed MAX_SGE
  pvrdma: release device resources in case of an error
  docs: Update pvrdma device documentation
  hw/rdma: Do not call rdma_backend_del_gid on an empty gid
  hw/rdma: Do not use bitmap_zero_extend to free bitmap
  hw/pvrdma: Clean device's resource when system is shutdown
  vl: Introduce shutdown_notifiers
  hw/rdma: Remove unneeded code that handles more that one port
  hw/pvrdma: Fill error code in command's response
  hw/pvrdma: Fill all CQE fields
  hw/pvrdma: Make device state depend on Ethernet function state
  hw/rdma: Initialize node_guid from vmxnet3 mac address
  hw/pvrdma: Make sure PCI function 0 is vmxnet3
  vmxnet3: Move some definitions to header file
  hw/pvrdma: Add support to allow guest to configure GID table
  ...
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

9b2e891e

pvrdma: check return value from pvrdma_idx_ring_has_ routines · f1e2e38e

由 Prasad J Pandit 提交于 12月 13, 2018

pvrdma_idx_ring_has_[data/space] routines also return invalid
index PVRDMA_INVALID_IDX[=-1], if ring has no data/space. Check
return value from these routines to avoid plausible infinite loops.
Reported-by: NLi Qiang <liq3ea@163.com>
Signed-off-by: NPrasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: NYuval Shaia <yuval.shaia@oracle.com>
Signed-off-by: NMarcel Apfelbaum <marcel.apfelbaum@gmail.com>

f1e2e38e

rdma: remove unused VENDOR_ERR_NO_SGE macro · 7be3a213

由 Prasad J Pandit 提交于 12月 13, 2018

With commit 4481985c (rdma: check num_sge does not exceed MAX_SGE)
macro VENDOR_ERR_NO_SGE is no longer in use - delete it.
Signed-off-by: NPrasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: NYuval Shaia <yuval.shaia@oracle.com>
Signed-off-by: NMarcel Apfelbaum <marcel.apfelbaum@gmail.com>

7be3a213

pvrdma: release ring object in case of an error · 509f57c9

由 Prasad J Pandit 提交于 12月 13, 2018

create_cq and create_qp routines allocate ring object, but it's
not released in case of an error, leading to memory leakage.
Reported-by: NLi Qiang <liq3ea@163.com>
Signed-off-by: NPrasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: NYuval Shaia <yuval.shaia@oracle.com>
Signed-off-by: NMarcel Apfelbaum <marcel.apfelbaum@gmail.com>

509f57c9

pvrdma: check number of pages when creating rings · 2c858ce5

由 Prasad J Pandit 提交于 12月 13, 2018

When creating CQ/QP rings, an object can have up to
PVRDMA_MAX_FAST_REG_PAGES 8 pages. Check 'npages' parameter
to avoid excessive memory allocation or a null dereference.
Reported-by: NLi Qiang <liq3ea@163.com>
Signed-off-by: NPrasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: NYuval Shaia <yuval.shaia@oracle.com>
Signed-off-by: NMarcel Apfelbaum <marcel.apfelbaum@gmail.com>

2c858ce5

pvrdma: add uar_read routine · 2aa86456

由 Prasad J Pandit 提交于 12月 13, 2018

Define skeleton 'uar_read' routine. Avoid NULL dereference.
Reported-by: NLi Qiang <liq3ea@163.com>
Signed-off-by: NPrasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: NMarcel Apfelbaum <marcel.apfelbaum@gmail.com>
Signed-off-by: NMarcel Apfelbaum <marcel.apfelbaum@gmail.com>

2aa86456

rdma: check num_sge does not exceed MAX_SGE · 0e68373c

由 Prasad J Pandit 提交于 12月 13, 2018

rdma back-end has scatter/gather array ibv_sge[MAX_SGE=4] set
to have 4 elements. A guest could send a 'PvrdmaSqWqe' ring element
with 'num_sge' set to > MAX_SGE, which may lead to OOB access issue.
Add check to avoid it.
Reported-by: NSaar Amar <saaramar5@gmail.com>
Signed-off-by: NPrasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: NYuval Shaia <yuval.shaia@oracle.com>
Signed-off-by: NMarcel Apfelbaum <marcel.apfelbaum@gmail.com>

0e68373c