Correct several deficiencies in the handling of the register pointer:
 * it should wrap around after 0x3f, not 0xff
 * guard against the caller handing us an out of range pointer
   (on h/w this can never happen, because only a 7 bit value is
   transferred over the I2C bus)
 * there was confusion over whether nvram[] holds only the 56 bytes
   of guest-accessible NVRAM, or also the secondary registers
   which hold the value of the clock captured at the start of a
   multibyte read. Correct to consistently be the latter, by fixing
   the array size and the offset used for NVRAM writes.
 * ds1338_send was attempting to use 'data' as both the data and
   the register offset simultaneously, which meant that writes to
   any register were broken; fix to use the register pointer.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

s->cpu_enabled is an array, so s->cpu_enabled ? "En" : "Dis" returns
"En" always. We should use s->cpu_enabled[cpu] here.
Signed-off-by: NEvgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

A missing call to qemu_set_irq() when reading the IRQ register
required SW to write to the IRQ register to acknowledge an
interrupt. With this patch the behavior is fixed:
 - Reading the interrupt register clears it and updates the timers
   interrupt status
 - Writes to the interrupt register are ignored
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Added helper function to automatically connect SPI slaves based on the QOM child
nodes of a device. A SSI master device can call this routine to automatically
hook-up all child nodes to its SPI bus.
Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: NPeter Maydell <peter.maydell@linaro.org>

Added maintainership for SSI, M25P80 and the Xilinx SPI controllers.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Acked-by: NPeter Maydell <peter.maydell@linaro.org>

Added the two SPI controllers to the zynq machine model. Attached two SPI flash
devices to each controller.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Acked-by: NPeter Maydell <peter.maydell@linaro.org>

Added device model for the Xilinx Zynq SPI controller (SPIPS).
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Acked-by: NPeter Maydell <peter.maydell@linaro.org>

Added SPI controller to the reference design, with two n25q128 spi-flashes
connected.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Acked-by: NPeter Maydell <peter.maydell@linaro.org>

Device model for xilinx XPS SPI controller (v2.0)
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>

Added device model for m25p80 style SPI flash family.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>

Added a FIFO API that can be used to create and operate byte FIFOs.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>

Removed the explicit SSI mux and wired the CS line directly up to the SSI
devices.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>

Allow multiple qdev_init_gpio_in() calls for the one device. The first call will
define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled
with different handlers. Needed when two levels of the QOM class heirachy both
define GPIO functionality, as a single GPIO handler with an index selecter is
not possible.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>

Slave creation function that can be used to create an SSI slave without
qdev_init() being called. This give machine models a chance to set properties.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Acked-by: NPeter Maydell <peter.maydell@linaro.org>

Added default CS behaviour for SSI slaves. SSI devices can set a property
to enable CS behaviour which will create a GPIO on the device which is the
CS. Tristating of the bus on SSI transfers is implemented.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Acked-by: NPeter Maydell <peter.maydell@linaro.org>

Removed assertion that only one device is attached to the SSI bus.

When multiple devices are attached, all slaves have their transfer function
called for transfers. Each device is responsible for knowing whether or not its
CS is active, and if not returning 0. The returned data is the logical or of
all responses from the (mulitple) devices.
Signed-off-by: NPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Acked-by: NPeter Maydell <peter.maydell@linaro.org>

* 'master' of git.qemu.org:/pub/git/qemu:
  qemu-barrier: Fix compilation on i386 hosts

Commit 1d31fca4 tried to fix bug
introduced by 610b823e by including
qemu-common.h, which breaks the build further.

Include compiler.h instead, as suggested by Blue Swirl.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Aka "normal" comparisons.  We now have the infrastructure to
pass back non-boolean results from gen_compare.  This will
automatically get used by both branches and conditional moves.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Now that we've cleaned up global temporary allocation, we can
continue translating the fallthru path of a conditional trap.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

There are 6 temporaries that disas_sparc_insn relies on having been
allocated.  Now that they are no longer referenced across branches,
they need not be allocated as local temps.

Move the allocation/free of these temporaries to make it clear that
they are local to the translation of a single insn.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The branches around the exception are maintaining an otherwise
unnecessary use of local temps for the cpu destination.

Note that gen_op_t{add,sub}_cc were identical to gen_op_{add,sub}_cc.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Share more code between unconditional and conditional paths.

Move the computation of the trap number into the conditional BB;
avoid using temporaries that have gone out of scope (cpu_tmp32)
or rely on local temps (cpu_dst).

Fully fold the exception number when the trap number is %g0+imm.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The branches around the exception are maintaining an otherwise
unnecessary use of local temps for the cpu destination.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

For the moment gen_cond et al retain their existing interface,
using setcond to turn a (potential) comparison back into a boolean.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The arguments passed are always the same.
Pass down just DisasContext instead.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Use the cpu_cond global register directly instead of passing it down.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Use the cpu_cond global register directly instead of passing it down.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Use the cpu_cond global register directly instead of passing it down.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

We always pass cpu_cond to the cond parameter.  Use that global
register directly instead of passing it down.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

We always pass cpu_cond to the cond parameter.  Use that global
register directly instead of passing it down.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

We always pass cpu_cond to the r_cond parameter.  Use that global
register directly instead of passing it down.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

No need for ifdefs when the log mask does just as well.
No need to print pc/npc when we're dumping the whole cpu state.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>