- 14 3月, 2018 2 次提交
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由 Max Filippov 提交于
Add arrows that mark beginning of register windows and position of the current window in the windowed register file. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
xtensa_cpu_dump_state outputs CPU physical registers as is, without synchronization from current window. That may result in different values printed for the current window and corresponding physical registers. Synchronize physical registers from window before dumping. Cc: qemu-stable@nongnu.org Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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- 23 1月, 2018 1 次提交
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由 Max Filippov 提交于
Coverity warnings CID 1385146, 1385148 1385149 and 1385150 point that xtensa_opcode_num_operands and xtensa_format_num_slots may return -1 even when xtensa_opcode_decode and xtensa_format_decode succeed. In that case unsigned counters used to iterate through operands/slots will not do the right thing. Make counters and loop bounds signed to fix the warnings. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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- 12 1月, 2018 1 次提交
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由 Peter Maydell 提交于
Some older versions of gcc complain if a typedef is defined twice: target/xtensa/translate.c:81: error: redefinition of typedef 'DisasContext' target/xtensa/cpu.h:339: note: previous declaration of 'DisasContext' was here Remove the now-redundant typedef from the definition of the struct in translate.c. Reported-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1515762528-22818-1-git-send-email-peter.maydell@linaro.org
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- 10 1月, 2018 6 次提交
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由 Max Filippov 提交于
const16 is an opcode that shifts 16 lower bits of an address register to the 16 upper bits and puts its immediate operand into the lower 16 bits. It is not controlled by an Xtensa option and doesn't have a fixed opcode. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
GPIO32 is not in the core ISA, but it was widely used in Diamond Cores. This implementation doesn't do actual I/O and doesn't handle the case of GPIO32 state being a part of coprocessor. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
SALT/SALTU are recent additions to the core Xtensa ISA that do signed/unsigned setcond. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
Add two special registers: MMID and DDR: - MMID is write-only and the only side effect of writing to it is output to the trace port, which is not emulated; - DDR is only accessible in debug mode, which is not emulated. Add two debug-mode-only opcodes: - rfdd and rfdo do return from the debug mode, which is not emulated. Add three internal opcodes for full MMU: - hwwdtlba and hwwitlba are the internal opcodes that write a value into autoupdate DTLB or ITLB entry. - ldpte is internal opcode that loads PTE entry that covers the most recent page fault address. None of these three opcodes may appear in a valid instruction. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
It doesn't help much, always-set bit 0 of the LITBASE SR is easy to compensate with decrement of the l32r immediate argument. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
Replace manual opcode analysis with libisa-based code. This makes it possible to support variable-encoding instructions of the core ISA, like const16, and will allow to support advanced Xtensa features, like FLIX and TIE. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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- 19 12月, 2017 3 次提交
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由 Max Filippov 提交于
FPU2000 implements basic single-precision floating point operations and can be replaced with a different implementation, like DFPU or HiFi. Move FPU2000 opcode translators into separate functions and list them in a separate array. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
Move implementations of core opcodes into separate translation functions. Introduce data structures for mapping opcode name to translator function. Make an array of core opcode/translator structures. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
Currently 'entry' opcode helper accepts frame size divided by 8, as it is encoded in the opcode. Make it more natural and accept actual frame size instead. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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- 25 10月, 2017 4 次提交
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由 Richard Henderson 提交于
Now that every target is using the disas_set_info hook, the flags argument is unused. Remove it. Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Richard Henderson 提交于
This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created by targets. Reviewed-by: NEmilio G. Cota <cota@braap.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Emilio G. Cota 提交于
Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Emilio G. Cota 提交于
Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \ accel/tcg/translator.c | cut -f1 -d':' | sort | uniq) perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
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- 06 9月, 2017 1 次提交
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由 Lluís Vilanova 提交于
Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: NLluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: NEmilio G. Cota <cota@braap.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 20 7月, 2017 1 次提交
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由 Lluís Vilanova 提交于
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NAlex Benneé <alex.benee@linaro.org> Reviewed-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NLluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 17 1月, 2017 1 次提交
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由 Max Filippov 提交于
RER and WER are privileged instructions for accessing external registers. External register address space is local to processor core. There's no alignment requirements, addressable units are 32-bit wide registers. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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- 16 1月, 2017 4 次提交
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由 Max Filippov 提交于
MEMCTL SR controls zero overhead loop buffer and number of ways enabled in L1 caches. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
There's no point in continuing translating guest instructions once an unconditional exception is thrown. There's also no point in updating pc before any instruction is translated, don't do it. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
Delimit each instruction that may access timers or IRQ state with qemu_io_start/qemu_io_end, so that qemu-system-xtensa could be run with -icount option. Raise EXCP_YIELD after CCOMPARE reprogramming to let tcg_cpu_exec recalculate how long this CPU is allowed to run. RSR now may need to terminate TB, but it can't be done in RSR handler because the same handler is used for XSR together with WSR handler, which may also need to terminate TB. Change RSR and WSR handlers return type to bool indicating whether TB termination is needed (RSR) or has been done (WSR), and add TB termination after RSR/WSR dispatcher call. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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由 Max Filippov 提交于
Xtensa cores may have a register (CCOUNT) that counts core clock cycles. It may also have a number of registers (CCOMPAREx); when CCOUNT value passes the value of CCOMPAREx, timer interrupt x is raised. Currently xtensa target counts a number of completed instructions and assumes that for CCOUNT one instruction takes one cycle to complete. It calls helper function to update CCOUNT register at every TB end and raise timer interrupts. This scheme works very predictably and doesn't have noticeable performance impact, but it is hard to use with multiple synchronized processors, especially with coming MTTCG. Derive CCOUNT from the virtual simulation time, QEMU_CLOCK_VIRTUAL. Use native QEMU timers for CCOMPARE timers, one timer for each register. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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- 11 1月, 2017 2 次提交
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 21 12月, 2016 1 次提交
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由 Thomas Huth 提交于
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: NThomas Huth <thuth@redhat.com>
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- 02 11月, 2016 1 次提交
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由 Richard Henderson 提交于
Reuse the existing locking provided by stdio to keep in_asm, cpu, op, op_opt, op_ind, and out_asm as contiguous blocks. While it isn't possible to interleave e.g. in_asm or op_opt logs because of the TB lock protecting all code generation, it is possible to interleave cpu logs, or to interleave a cpu dump with an out_asm dump. For mingw32, we appear to have no viable solution for this. The locking functions are not properly exported from the system runtime library. Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 28 10月, 2016 1 次提交
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由 Anand J 提交于
Some files contain multiple #includes of the same header file. Removed most of those unnecessary duplicate entries using scripts/clean-includes. Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NAnand J <anand.indukala@gmail.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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- 20 6月, 2016 1 次提交
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由 Lluís Vilanova 提交于
Information is tracked inside the TCGContext structure, and later used by tracing events with the 'tcg' and 'vcpu' properties. The 'cpu' field is used to check tracing of translation-time events ("*_trans"). The 'tcg_env' field is used to pass it to execution-time events ("*_exec"). Signed-off-by: NLluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 146549350162.18437.3033661139638458143.stgit@fimbulvetr.bsc.es Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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- 06 6月, 2016 1 次提交
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由 Richard Henderson 提交于
The arm target was handled by 06486077, but other targets were ignored. This handles all the rest which actually support disassembly (that is, skipping moxie and tilegx). Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 19 5月, 2016 1 次提交
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由 Paolo Bonzini 提交于
exec-all.h contains TCG-specific definitions. It is not needed outside TCG-specific files such as translate.c, exec.c or *helper.c. One generic function had snuck into include/exec/exec-all.h; move it to include/qom/cpu.h. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 13 5月, 2016 1 次提交
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由 Sergey Fedorov 提交于
In user mode, there's only a static address translation, TBs are always invalidated properly and direct jumps are reset when mapping change. Thus the destination address is always valid for direct jumps and there's no need to restrict it to the pages the TB resides in. Signed-off-by: NSergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: NSergey Fedorov <sergey.fedorov@linaro.org> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 01 3月, 2016 1 次提交
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由 Lluís Vilanova 提交于
Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The tracing infrastructure later needs to differentiate between regular pointers and pointers to vCPUs. Also changes all targets to use the new 'TCGv_env' type instead of the generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env' translates into 'TCGv_ptr'), but that could change in the future to enforce the difference. Note that a 'TCGv_env' type (for 'CPUState') is not added, since all helpers currently receive the architecture-specific pointer ('CPUArchState'). Signed-off-by: NLluís Vilanova <vilanova@ac.upc.edu> Acked-by: NRichard Henderson <rth@twiddle.net> Message-id: 145641859552.30295.7821536833590725201.stgit@localhost Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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- 09 2月, 2016 1 次提交
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由 Richard Henderson 提交于
Thus, use cpu_env as the parameter, not TCG_AREG0 directly. Update all uses in the translators. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 03 2月, 2016 1 次提交
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由 Paolo Bonzini 提交于
Split the bits that require it to exec/log.h. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NDenis V. Lunev <den@openvz.org> Acked-by: NChristian Borntraeger <borntraeger@de.ibm.com> Message-id: 1452174932-28657-8-git-send-email-den@openvz.org Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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- 29 1月, 2016 1 次提交
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由 Peter Maydell 提交于
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-29-git-send-email-peter.maydell@linaro.org
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- 18 12月, 2015 1 次提交
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由 Paolo Bonzini 提交于
Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 29 10月, 2015 1 次提交
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由 Richard Henderson 提交于
Some targets already had this within their logic, but make sure it's present for all targets. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 22 10月, 2015 1 次提交
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由 Max Filippov 提交于
S32NB provides the same functionality as S32I with two exceptions. First, when its operation leaves the processor, the external transaction is marked Non-Bufferable. Second, it may not be used to write to Instruction RAM. In QEMU S32NB is equivalent to S32I. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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