- 09 12月, 2012 4 次提交
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由 Max Filippov 提交于
The Miscellaneous Special Registers Option provides zero to four scratch registers within the processor readable and writable by RSR, WSR, and XSR. These registers are privileged. They may be useful for some application-specific exception and interrupt processing tasks in the kernel. The MISC registers are undefined after reset. See ISA, 4.7.3 for details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr, xsr) are associated with their corresponding SR and raise illegal opcode exception in case the register is not configured for the core. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
In XEA1, the Options for Memory Protection and Translation and the corresponding TLB management instructions are not available. Instead, functionality similar to the Region Protection Option is available through the cache attribute register. See ISA, A.2.14 for details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Max Filippov 提交于
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory type. See ISA, 4.3.12.4 for details. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 23 9月, 2012 1 次提交
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由 Max Filippov 提交于
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 21 2月, 2012 1 次提交
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由 Max Filippov 提交于
Fill debug configuration from overlay definitions in the DEBUG_SECTION. Add DEBUG_SECTION to DC232B and FSF cores. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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- 18 2月, 2012 1 次提交
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由 Max Filippov 提交于
TLB_TEMPLATE macro specifies TLB geometry in the core configuration. Make TLB_TEMPLATE available for region protection core variants, defining 1 way ITLB and DTLB with 8 entries each. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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- 26 11月, 2011 1 次提交
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由 Max Filippov 提交于
- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively; - ITLB/DTLB way 6 attr field is set to 3 on reset. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 02 11月, 2011 1 次提交
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由 Max Filippov 提交于
Cache options must be enabled for the cores that have cache to avoid illegal instruction exceptions. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
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- 16 10月, 2011 1 次提交
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由 Max Filippov 提交于
Introduce overlay_tool.h that defines core configuration blocks from data available in the linux architecture variant overlay. Overlay data is automatically generated in the core configuration process by Tensilica tools and can be directly converted to qemu xtensa core description by overlay_tool.h Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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