- 07 6月, 2016 9 次提交
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由 Alexey Kardashevskiy 提交于
This will be later used by the "ibm,reset-pe-dma-window" RTAS handler which resets the DMA configuration to the defaults. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Alexey Kardashevskiy 提交于
LoPAPR dictates that during system reset all DMA windows must be removed and the default DMA32 window must be created so does the patch. At the moment there is just one window supported so no change in behaviour is expected. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Alexey Kardashevskiy 提交于
We are going to have multiple DMA windows at different offsets on a PCI bus. For the sake of migration, we will have as many TCE table objects pre-created as many windows supported. So we need a way to map windows dynamically onto a PCI bus when migration of a table is completed but at this stage a TCE table object does not have access to a PHB to ask it to map a DMA window backed by just migrated TCE table. This adds a "root" memory region (UINT64_MAX long) to the TCE object. This new region is mapped on a PCI bus with enabled overlapping as there will be one root MR per TCE table, each of them mapped at 0. The actual IOMMU memory region is a subregion of the root region and a TCE table enables/disables this subregion and maps it at the specific offset inside the root MR which is 1:1 mapping of a PCI address space. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Alexey Kardashevskiy 提交于
The source guest could have reallocated the default TCE table and migrate bigger/smaller table. This adds reallocation in post_load() if the default table size is different on source and destination. This adds @bus_offset, @page_shift to the migration stream as a subsection so when DDW is added, migration to older machines will still be possible. As @bus_offset and @page_shift are not used yet, this makes no change in behavior. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Alexey Kardashevskiy 提交于
Currently TCE tables are created once at start and their sizes never change. We are going to change that by introducing a Dynamic DMA windows support where DMA configuration may change during the guest execution. This changes spapr_tce_new_table() to create an empty zero-size IOMMU memory region (IOMMU MR). Only LIOBN is assigned by the time of creation. It still will be called once at the owner object (VIO or PHB) creation. This introduces an "enabled" state for TCE table objects, some helper functions are added: - spapr_tce_table_enable() receives TCE table parameters, stores in sPAPRTCETable and allocates a guest view of the TCE table (in the user space or KVM) and sets the correct size on the IOMMU MR; - spapr_tce_table_disable() disposes the table and resets the IOMMU MR size; it is made public as the following DDW code will be using it. This changes the PHB reset handler to do the default DMA initialization instead of spapr_phb_realize(). This does not make differenct now but later with more than just one DMA window, we will have to remove them all and create the default one on a system reset. No visible change in behaviour is expected except the actual table will be reallocated every reset. We might optimize this later. The other way to implement this would be dynamically create/remove the TCE table QOM objects but this would make migration impossible as the migration code expects all QOM objects to exist at the receiver so we have to have TCE table objects created when migration begins. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Alexey Kardashevskiy 提交于
This allows dynamic allocation for migrating arrays. Already existing VMSTATE_VARRAY_UINT32 requires an array to be pre-allocated, however there are cases when the size is not known in advance and there is no real need to enforce it. This defines another variant of VMSTATE_VARRAY_UINT32 with WMS_ALLOC flag which tells the receiving side to allocate memory for the array before receiving the data. The first user of it is a dynamic DMA window which existence and size are totally dynamic. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Bharata B Rao 提交于
Introduce kvm_get_max_memslots() API that can be used to obtain the maximum number of memslots supported by KVM. Signed-off-by: NBharata B Rao <bharata@linux.vnet.ibm.com> Acked-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Talha Imran 提交于
With specification at hand from the reference manual from Freescale http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf , I have found a fix to efscmp* instructions handling in QEMU. efscmp* instructions in QEMU set crD (Condition Register nibble) values as (0b0100 << 2) = 0b10000 (consider the HELPER_SINGLE_SPE_CMP macro which left shifts the value returned by efscmp* handler by 2 bits). A value of 0b10000 is not correct according the to the reference manual. The reference manual expects efscmp* instructions to return a value of 0bx1xx. Please find attached a patch which disables left shifting in HELPER_SINGLE_SPE_CMP macro. This macro is used by efscmp* and efstst* instructions only. efstst* instruction handlers, in turn, call efscmp* handlers too. *Explanation:* Traditionally, each crD (condition register nibble) consist of 4 bits, which is set by comparisons as follows: crD = W X Y Z where W = Less than X = Greater than Y = Equal to However, efscmp* instructions being a special case return a binary result. (efscmpeq will set the crD = 0bx1xx iff when op1 == op2 and 0bx0xx otherwise; i.e. there is no notion of different crD values based on Less than, Greater than and Equal to). This effectively means that crD will store a "Greater than" comparison result iff efscmp* instruction comparison is TRUE. Compiler exploits this feature by checking for "Branch if Less than or Equal to" (ble instruction) OR "Branch if Greater than" (bgt instruction) for Branch if FALSE OR Branch if TRUE respectively after an efscmp* instruction. This can be seen in a assembly code snippet below: 27 if (__real__ x != 3.0f || __imag__ x != 4.0f) 10000498: lwz r10,8(r31) 1000049c: lis r9,16448 100004a0: efscmpeq cr7,r10,r9 100004a4: ble- cr7,0x100004b8 <bar+60> //jump to abort() call 100004a8: lwz r10,12(r31) 100004ac: lis r9,16512 100004b0: efscmpeq cr7,r10,r9 100004b4: bgt- cr7,0x100004bc <bar+64> //skip abort() call 28 abort (); 100004b8: bl 0x10000808 <abort> Signed-off-by: NTalha Imran <talha_imran@mentor.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Peter Maydell 提交于
target-arm queue: * support instruction syndrome info for data aborts from A64 to EL2 * add HSTR_EL2 register * fix incorrect ESR IL bits in various syndrome register cases * virt: fix limit of 64-bit ACPI/ECAM PCI MMIO range * gicv2: RAZ/WI non-sec access to sec interrupts * i2c: add aspeed i2c controller * virt: Reject gic-version=host for non-KVM (don't segv on aarch64 host) * xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions * xlnx-zynqmp: Support KVM on AArch64 hosts * ptimer: Various fixes for awkward corner cases * char: QOMify various ARM UART models * char: get rid of qemu_char_get_next_serial * target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation * zynqmp: Add the ZCU102 board # gpg: Signature made Mon 06 Jun 2016 17:01:11 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160606-1: (25 commits) zynqmp: Add the ZCU102 board target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation char: get rid of qemu_char_get_next_serial hw/char: QOM'ify xilinx_uartlite model hw/char: QOM'ify stm32f2xx_usart model hw/char: QOM'ify digic-uart model hw/char: QOM'ify cadence_uart model hw/char: QOM'ify pl011 model hw/ptimer: Introduce ptimer_get_limit hw/ptimer: Support "on the fly" timer mode switch hw/ptimer: Update .delta on period/freq change hw/ptimer: Perform counter wrap around if timer already expired hw/ptimer: Fix issues caused by the adjusted timer limit value xlnx-zynqmp: Use the in kernel GIC model for KVM runs xlnx-zynqmp: Delay realization of GIC until post CPU realization xlnx-zynqmp: Make the RPU subsystem optional xlnx-zynqmp: Add a secure prop to en/disable ARM Security Extensions hw/arm/virt: Reject gic-version=host for non-KVM i2c: add aspeed i2c controller hw/intc/gic: RAZ/WI non-sec access to sec interrupts ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 06 6月, 2016 31 次提交
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由 Alistair Francis 提交于
Most Zynq UltraScale+ users will be targetting and using the ZCU102 board instead of the development focused EP108. To make our QEMU machine names clearer add a ZCU102 machine model. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: cc82eec026b2febfca252d73362bb7084616c1ad.1464213234.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Sergey Sorokin 提交于
Address size is 40-bit for the AArch32 stage 2 translation, and t0sz can be negative (from -8 to 7), so we need to adjust it to use the existing TTBR selecting logic. Signed-off-by: NSergey Sorokin <afarallax@yandex.ru> Message-id: 1464974151-1231644-1-git-send-email-afarallax@yandex.ru Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 xiaoqiang zhao 提交于
since there is no user of qemu_char_get_next_serial any more, it's time to let it go away. Acked-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: Nxiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465028065-5855-7-git-send-email-zxq_yx_007@163.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 xiaoqiang zhao 提交于
* drop qemu_char_get_next_serial and use chardev prop * create xilinx_uartlite_create wrapper function to create xilinx_uartlite device * change affected board code to use the new way Signed-off-by: Nxiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465028065-5855-6-git-send-email-zxq_yx_007@163.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 xiaoqiang zhao 提交于
* drop qemu_char_get_next_serial and use chardev prop * change affected board code to use the new way Signed-off-by: Nxiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465028065-5855-5-git-send-email-zxq_yx_007@163.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 xiaoqiang zhao 提交于
* drop qemu_char_get_next_serial and use chardev prop * change affected board code to use the new way Signed-off-by: Nxiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465028065-5855-4-git-send-email-zxq_yx_007@163.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 xiaoqiang zhao 提交于
* drop qemu_char_get_next_serial and use chardev prop * create cadence_uart_create wrapper function to create cadence_uart_device * change affected board code to use the new way Signed-off-by: Nxiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465028065-5855-3-git-send-email-zxq_yx_007@163.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 xiaoqiang zhao 提交于
* drop qemu_char_get_next_serial and use chardev prop * add pl011_create wrapper function to create pl011 uart device * change affected board code to use the new way Signed-off-by: Nxiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1465028065-5855-2-git-send-email-zxq_yx_007@163.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dmitry Osipenko 提交于
Currently ptimer users are used to store copy of the limit value, because ptimer doesn't provide facility to retrieve the limit. Let's provide it. Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 8f1fa9f90d8dbf8086fb02f3b4835eaeb4089cf6.1464367869.git.digetx@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dmitry Osipenko 提交于
Allow switching between periodic <-> oneshot modes while timer is running. Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: f030be6e28fbd219e1e8d22297aee367bd9af5bb.1464367869.git.digetx@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dmitry Osipenko 提交于
Delta value must be updated on period/freq change, otherwise running timer would be restarted (counter reloaded with old delta). Only m68k/mcf520x and arm/arm_timer devices are currently doing freq change correctly, i.e. stopping the timer. Perform delta update to fix affected devices and eliminate potential further mistakes. Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 4987ef5fdc128bb9a744fd794d3f609135c6a39c.1464367869.git.digetx@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dmitry Osipenko 提交于
ptimer_get_count() might be called while QEMU timer already been expired. In that case ptimer would return counter = 0, which might be undesirable in case of polled timer. Do counter wrap around for periodic timer to keep it distributed. In order to achieve more accurate emulation behaviour of certain hardware, don't perform wrap around when in icount mode and return counter = 0 in that case (that doesn't affect polled counter distribution). Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 4ce381c7d24d85d165ff251d2875d16a4b6a5c04.1464367869.git.digetx@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Dmitry Osipenko 提交于
Multiple issues here related to the timer with a adjusted .limit value: 1) ptimer_get_count() returns incorrect counter value for the disabled timer after loading the counter with a small value, because adjusted limit value is used instead of the original. For instance: 1) ptimer_stop(t) 2) ptimer_set_period(t, 1) 3) ptimer_set_limit(t, 0, 1) 4) ptimer_get_count(t) <-- would return 10000 instead of 0 2) ptimer_get_count() might return incorrect value for the timer running with a adjusted limit value. For instance: 1) ptimer_stop(t) 2) ptimer_set_period(t, 1) 3) ptimer_set_limit(t, 10, 1) 4) ptimer_run(t) 5) ptimer_get_count(t) <-- might return value > 10 3) Neither ptimer_set_period() nor ptimer_set_freq() are adjusting the limit value, so it is still possible to make timer timeout value arbitrary small. For instance: 1) ptimer_set_period(t, 10000) 2) ptimer_set_limit(t, 1, 0) 3) ptimer_set_period(t, 1) <-- bypass limit correction Fix all of the above issues by adjusting timer period instead of the limit. Perform the adjustment for periodic timer only. Use the delta value instead of the limit to make decision whether adjustment is required, as limit could be altered while timer is running, resulting in incorrect value returned by ptimer_get_count. Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: cd141f74f5737480ec586b9c7d18cce1d69884e2.1464367869.git.digetx@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
Use the in kernel GIC model when running with KVM enabled. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 1464173555-12800-5-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
Delay the realization of the GIC until after CPUs are realized. This is needed for KVM as the in-kernel GIC model will fail if it is realized with no available CPUs. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 1464173555-12800-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
The way we currently model the RPU subsystem is of quite limited use. In addition to that, it causes problems for KVM and for GDB debugging. Make the RPU optional by adding a has_rpu property and default to having it disabled. This changes the default setup from having the RPU to not longer having it. Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 1464173555-12800-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
Add a secure prop to en/disable ARM Security Extensions. This is particularly useful for KVM runs. Default to disabled to match the behavior of KVM. This changes the default setup from having the ARM Security Extensions to not longer having them. Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: 1464173555-12800-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cole Robinson 提交于
If you try to gic-version=host with TCG on a KVM aarch64 host, qemu segfaults, since host requires KVM APIs. Explicitly reject gic-version=host if KVM is not enabled https://bugzilla.redhat.com/show_bug.cgi?id=1339977Signed-off-by: NCole Robinson <crobinso@redhat.com> Message-id: b1b3b0dd143b7995a7f4062966b80a2cf3e3c71e.1464273085.git.crobinso@redhat.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
The Aspeed AST2400 integrates a set of 14 I2C/SMBus bus controllers directly connected to the APB bus. They can be programmed as master or slave but the propopsed model only supports the master mode. On the TODO list, we also have : - improve and harden the state machine. - bus recovery support (used by the Linux driver). - transfer mode state machine bits. this is not strictly necessary as it is mostly used for debug. The bus busy bit is deducted from the I2C core engine of qemu. - support of the pool buffer: 2048 bytes of internal SRAM (not used by the Linux driver). Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1464704307-25178-1-git-send-email-clg@kaod.org [PMM: removed unused functions aspeed_i2c_bus_get_state() and aspeed_i2c_bus_set_state()] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jens Wiklander 提交于
Treat non-secure accesses to registers and bits in registers of secure interrupts as RAZ/WI. Signed-off-by: NJens Wiklander <jens.wiklander@linaro.org> Message-id: 1464273945-2055-1-git-send-email-jens.wiklander@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Ard Biesheuvel 提交于
Set the MMIO range limit field to 'base + size - 1' as required. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1463856217-17969-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Remove some incorrect code from arm_cpu_do_interrupt_aarch64() which attempts to set the IL bit in the syndrome register based on the value of env->thumb. This is wrong in several ways: * IL doesn't indicate Thumb-vs-ARM, it indicates instruction length (which may be 16 or 32 for Thumb and is always 32 for ARM) * not every syndrome format uses IL like this -- for some IL is always set, and for some it is always clear * the code is changing esr_el[new_el] even for interrupt entry, which is not supposed to modify ESR_ELx at all Delete the code, and instead rely on the syndrome value in env->exception.syndrome having already been set up with the correct value of IL. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1463487258-27468-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
For some exception syndrome types, the IL bit should always be set. This includes the instruction abort, watchpoint and software step syndrome types; add the missing ARM_EL_IL bit to the syndrome values returned by syn_insn_abort(), syn_swstep() and syn_watchpoint(). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1463487258-27468-2-git-send-email-peter.maydell@linaro.org
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由 Edgar E. Iglesias 提交于
Add support for generating the ISS (Instruction Specific Syndrome) for Data Abort exceptions taken from AArch64. These syndromes are used by hypervisors for example to trap and emulate memory accesses. We save the decoded data out-of-band with the TBs at translation time. When exceptions hit, the extra data attached to the TB is used to recreate the state needed to encode instruction syndromes. This avoids the need to emit moves with every load/store. Based on a suggestion from Peter Maydell. Suggested-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1462464601-10888-2-git-send-email-edgar.iglesias@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Add the Hypervisor System Trap Register for EL2. This register is used early in the Linux boot and without it the kernel aborts with a "Synchronous Abort" error. Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: ea5aae4b10283de4705b864fe9d4bd2eaddaacae.1463174342.git.alistair.francis@xilinx.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
readdir_r() to readdir() conversion, various minor cleanups # gpg: Signature made Mon 06 Jun 2016 10:52:52 BST # gpg: using DSA key 0x02FC3AEB0101DBC2 # gpg: Good signature from "Greg Kurz <gkurz@fr.ibm.com>" # gpg: aka "Greg Kurz <groug@free.fr>" # gpg: aka "Greg Kurz <gkurz@linux.vnet.ibm.com>" # gpg: aka "Gregory Kurz (Groug) <groug@free.fr>" # gpg: aka "Gregory Kurz (Cimai Technology) <gkurz@cimai.com>" # gpg: aka "Gregory Kurz (Meiosys Technology) <gkurz@meiosys.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2BD4 3B44 535E C0A7 9894 DBA2 02FC 3AEB 0101 DBC2 * remotes/gkurz/tags/for-upstream: 9p: switch back to readdir() 9p: add locking to V9fsDir 9p: introduce the V9fsDir type 9p: drop useless out: label 9p: drop useless inclusion of hw/i386/pc.h 9p/fsdev: remove obsolete references to virtio 9p: some more cleanup in #include directives Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
virtio-gpu: scanout fix, live migration support vmsvga: security fixes # gpg: Signature made Mon 06 Jun 2016 08:05:00 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vga-20160606-1: virtio-gpu: add live migration support vmsvga: don't process more than 1024 fifo commands at once vmsvga: shadow fifo registers vmsvga: add more fifo checks vmsvga: move fifo sanity checks to vmsvga_fifo_length virtio-gpu: fix scanout rectangles Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Mark Cave-Ayland 提交于
Commit fcaafb10 accidentally broke reads from scsi-disk devices when being updated from its original form to use the new byte-based block functions. Add the extra missing sector to offset conversion in order to restore read functionality. Signed-off-by: NMark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: NEric Blake <eblake@redhat.com> Tested-by: Nxiaoqiang zhao <zxq_yx_007@163.com> Message-id: 1464931021-25117-1-git-send-email-mark.cave-ayland@ilande.co.uk Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
audio: pa volume fix, some qomifying. # gpg: Signature made Mon 06 Jun 2016 08:01:21 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-audio-20160606-1: hw/audio: QOM'ify milkymist-ac97.c hw/audio: QOM'ify intel-hda hw/audio: QOM cleanup for intel-hda hw/audio: QOM'ify cs4231.c audio: pa: Set volume of recording stream instead of recording device Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Check address ranges for disassembly # gpg: Signature made Sun 05 Jun 2016 17:30:28 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tgt-20160605: target-*: dfilter support for in_asm Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Wu 提交于
While waiting for a gdb response, or while sending an acknowledgement there is not much to do, so do not mark the socket as non-blocking to avoid a busy loop while paused at gdb. This only affects the user-mode emulation (qemu-arm -g 1234 ./a.out). Note that this issue was reported before at https://lists.nongnu.org/archive/html/qemu-devel/2013-02/msg02277.html. While at it, close the gdb client fd on EOF or error while reading. Signed-off-by: NPeter Wu <peter@lekensteyn.nl> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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