- 09 2月, 2018 5 次提交
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由 David Hildenbrand 提交于
Move floating interrupt handling into the flic. Floating interrupts will now be considered by all CPUs, not just CPU #0. While at it, convert I/O interrupts to use a list and make sure we properly consider I/O sub-classes in s390_cpu_has_io_int(). Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-9-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
This is a preparation for floating interrupt support and only applies to MTTCG, single threaded TCG works just fine. If a floating interrupt wakes up a VCPU and the CPU thinks it can run (clearing cs->halted), at the point where the interrupt would be delivered, already another VCPU might have picked up the interrupt, resulting in a wakeup without an interrupt (executing wrong code). It is wrong to let the VCPU continue to execute (the WAIT PSW). Instead, we have to put the VCPU back to sleep. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-8-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Let the flic device handle it internally. This will allow us to later on store floating interrupts in the flic for the TCG case. This now also simplifies kvm.c. All that's left is the fallback interface for floating interrupts, which is now triggered directly via the flic in case anything goes wrong. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-6-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
We currently only support CRW machine checks. This is a preparation for real floating interrupt support. Get rid of the queue and handle it via the bit INTERRUPT_MCHK. We don't rename it for now, as it will be soon gone (when moving crw machine checks into the flic). Please note that this is the same way also KVM handles it: only one instance of a machine check can be pending at a time. So no need for a queue. While at it, make sure we try to deliver only if env->cregs[14] actually indicates that CRWs are accepted. Drop two unused defines on the way (we already have PSW_MASK_...). Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-5-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
We have to consider all deliverable interrupts. We now have to take care of the special scenario, where we first inject an interrupt with a WAIT PSW, followed by a !WAIT PSW. (very unlikely but possible) Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-2-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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- 05 2月, 2018 1 次提交
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由 Philippe Mathieu-Daudé 提交于
changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: NMarcel Apfelbaum <marcel@redhat.com> Acked-by: NDavid Gibson <david@gibson.dropbear.id.au> Acked-by: NCornelia Huck <cohuck@redhat.com> Reviewed-by: NLaurent Vivier <laurent@vivier.eu> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 25 1月, 2018 1 次提交
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由 Laurent Vivier 提交于
The MC68040 MMU provides the size of the access that triggers the page fault. This size is set in the Special Status Word which is written in the stack frame of the access fault exception. So we need the size in m68k_cpu_unassigned_access() and m68k_cpu_handle_mmu_fault(). To be able to do that, this patch modifies the prototype of handle_mmu_fault handler, tlb_fill() and probe_write(). do_unassigned_access() already includes a size parameter. This patch also updates handle_mmu_fault handlers and tlb_fill() of all targets (only parameter, no code change). Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Reviewed-by: NDavid Hildenbrand <david@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
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- 22 1月, 2018 4 次提交
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由 Christian Borntraeger 提交于
stfle.81 (ppa15) is a transparent facility that can be passed to the guest without the need to implement hypervisor support. As this feature can be provided by firmware we add it to all full models. Cc: qemu-stable@nongnu.org Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20180118085628.40798-4-borntraeger@de.ibm.com> Reviewed-by: NHalil Pasic <pasic@linux.vnet.ibm.com> Reviewed-by: NDavid Hildenbrand <david@redhat.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 Christian Borntraeger 提交于
We need to handle the bpb control on reset and migration. Normally stfle.82 is transparent (and the normal guest part works without hypervisor activity). To prevent any issues we require full host kernel support for this feature. Cc: qemu-stable@nongnu.org Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20180118085628.40798-3-borntraeger@de.ibm.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NDavid Hildenbrand <david@redhat.com> [CH: 'Branch Prediction Blocking' -> 'Branch prediction blocking'] Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
CC == 2 can only happen due to a protection exception, not if memory is not available (PGM_ADDRESSING). So all PGM_ADDRESSING exceptions have to be forwarded to the guest. Since the initial definition of TEST PROTECTION, we now read globals (e.g. PSW mask), so we have to correctly mark the instruction (otherwise, e.g. booting fedora 27 fails). Also, the architecture explicitly specifies which exceptions are forwarded to the guest, this makes the code a little nicer. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20180112125452.8569-1-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Linux uses TEST PROTECTION to sense for available memory locations. Let's implement what we can for now (just as for the other instructions, excluding AR mode and special protection mechanisms). Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171218224616.21030-2-david@redhat.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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- 16 1月, 2018 1 次提交
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由 Eric Blake 提交于
The point of writing a macro embedded in a 'do { ... } while (0)' loop (particularly if the macro has multiple statements or would otherwise end with an 'if' statement) is so that the macro can be used as a drop-in statement with the caller supplying the trailing ';'. Although our coding style frowns on brace-less 'if': if (cond) statement; else something else; that is the classic case where failure to use do/while(0) wrapping would cause the 'else' to pair with any embedded 'if' in the macro rather than the intended outer 'if'. But conversely, if the macro includes an embedded ';', then the same brace-less coding style would now have two statements, making the 'else' a syntax error rather than pairing with the outer 'if'. Thus, even though our coding style with required braces is not impacted, ending a macro with ';' makes our code harder to port to projects that use brace-less styles. The change should have no semantic impact. I was not able to fully compile-test all of the changes (as some of them are examples of the ugly bit-rotting debug print statements that are completely elided by default, and I didn't want to recompile with the necessary -D witnesses - cleaning those up is left as a bite-sized task for another day); I did, however, audit that for all files touched, all callers of the changed macros DID supply a trailing ';' at the callsite, and did not appear to be used as part of a brace-less conditional. Found mechanically via: $ git grep -B1 'while (0);' | grep -A1 \\\\ Signed-off-by: NEric Blake <eblake@redhat.com> Acked-by: NCornelia Huck <cohuck@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Acked-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20171201232433.25193-7-eblake@redhat.com> Reviewed-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 30 12月, 2017 1 次提交
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由 Richard Henderson 提交于
These are now trivial sets and tests against NULL. Unwrap. Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
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- 15 12月, 2017 27 次提交
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由 David Hildenbrand 提交于
We are good enough to boot upstream Linux kernels / Fedora 26/27. That should be sufficient for now. As the QEMU CPU model is migration safe, let's add compatibility code. Generate the feature list to reduce the chance of messing things up in the future. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208165529.14124-1-david@redhat.com> [CH: squashed 's390x/cpumodel: make qemu cpu model play with "none" machine' (20171213132407.5227-1-david@redhat.com) and 's390x/tcg: don't include z13 features in the qemu model' (20171213171512.17601-1-david@redhat.com) into patch] Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
The Set-Program-Parameter facility (also known as Load-Program-Parameter facility) provides the LPP instruction used to load the program parameter. We already implement that instruction in TCG, so add it to our list. Note: Not documented in the PoP but in "The Load-Program-Parameter and CPU-Measurement Facilities) - SA23-2260-05 document. While at it, make the whole list ordered (according to cpu_features_def.h). Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-14-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
It only provides the EXTRACT CPU TIME instruction. We can reuse the stpt helper, which calculates the CPU timer value. As the instruction is not privileged, but we don't have a CPU timer value in case of linux user, we simply reuse cpu_get_host_ticks() to produce some descending value. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-13-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
KVM suppresses SIGA, setting cc=3. Let's do the same for TCG, so we're at least equal. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-12-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Just like KVM does, we should suppress this instruction: When this instruction is not provided, it is checked for privileged operation exception and the instruction is suppressed by the machine Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-11-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Let's just wire it up like KVM. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-10-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Let's handle it just like KVM: Depending on the model, this instruction may not be provided. When this instruction is not provided, it is checked for operand exception and privileged-opera- tion exception, and then is suppressed. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-9-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
With this facility, OI/OIY, NI/NIY and XI/XIY are atomic. All operate on one byte (MO_UB). Emulate old behavior. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-8-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
The semantics of ASI/ASGI/ALSI/ALSGI changed. Let's implement them just like LOAD AND ADD, so they are atomic. Emulate old behavior. This fixes random crashes when booting a Linux kernel compiled for z196+ with SMP + MTTCG. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-7-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
CRW machine check handling requires STCRW. So let's wire it up. Reviewed-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-6-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
We were not yet using the value of the TOD Programmable Register. Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-5-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Needed for machine check handling inside Linux (when restoring registers). Except for SIGP and machine checks, we don't make use of the register yet. Sufficient for now. Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-4-david@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
The architecture mode indication wasn't stored. The split of certain 64bit fields was unnecessary. Also, the complete clock comparator, not just bit 0-55 (starting at byte 1) was stored. We now generate a proper MCIC via the same helper we use for KVM. There is more to clean up, but we will change the other parts later on either way. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-3-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
We'll need it later on in two places. Refactor it to just indicate the validity bits. While at it, introduce a define for the used CR14 bit (we'll also need later on). Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-2-david@redhat.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Only one user left, get rid of it so we don't get any new users. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-17-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
All users are gone, we can finally drop it and make sure that all new program interrupt injections are reminded of the retaddr - as they have to use s390_program_interrupt() now. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-16-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
STSI needs some more love, but let's do one step at a time. We can now drop potential_page_fault(). Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-15-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Convert this user, too. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-14-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
We can now drop updating the cc. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-13-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Now we can drop the two save statements in the translate function. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-12-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Now we can drop potential_page_fault(). While at it, move the unlock further up, looks cleaner. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-11-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
As we handle the retaddr in all cases properly now, we can drop it. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-10-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
s390_cpu_virt_mem_rw() must always return, so callers can react on an exception (e.g. see ioinst_handle_stcrw()). Therefore, using program_interrupt() is wrong. Fix that up. Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-9-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
s390_cpu_virt_mem_rw() must always return, so callers can react on an exception (e.g. see ioinst_handle_stcrw()). However, for TCG we always have to exit the cpu loop (and restore the cpu state before that) if we injected a program interrupt. So let's introduce and use s390_cpu_virt_mem_handle_exc() in code that is not purely KVM. Directly pass the retaddr we already have available in these functions. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-8-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Needed to later drop potential_page_fault() from the diag TCG translate function. Convert program_interrupt() to s390_program_interrupt() directly, making use of the passed address. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-7-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
Once we wire up TCG, we will need the retaddr to correctly inject program interrupts. As we want to get rid of the function program_interrupt(), convert PCI code too. For KVM, we can simply use RA_IGNORED. Convert program_interrupt() to s390_program_interrupt() directly, making use of the passed address. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-6-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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由 David Hildenbrand 提交于
TCG needs the retaddr when injecting an interrupt. Let's just pass it along and use RA_IGNORED for KVM. The value will be completely ignored for KVM. Convert program_interrupt() to s390_program_interrupt() directly, making use of the passed address. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Hildenbrand <david@redhat.com> Message-Id: <20171130162744.25442-5-david@redhat.com> Signed-off-by: NCornelia Huck <cohuck@redhat.com>
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