1. 10 3月, 2014 1 次提交
    • P
      target-arm: Fix incorrect setting of E bit in CPSR · af519934
      Peter Maydell 提交于
      Commit 4cc35614 moved the exception mask bits out of env->uncached_cpsr
      and into env->daif. However the env->daif contents are AArch64 style
      mask bits, which include not just the AArch32 AIF bits but also the
      new D bit (masks debug exceptions). This means that when reconstructing
      the AArch32 CPSR value we must not allow the D bit in env->daif to get
      into the CPSR, because the corresponding bit in the CPSR is E, the
      endianness bit.
      
      This bug didn't affect execution under TCG because we don't implement
      endianness-swapping and so simply ignored the E bit; however it meant
      that kernel booting under KVM failed, because KVM does honour the E bit.
      Reported-by: NAlexey Ignatov <lexszero@gmail.com>
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      af519934
  2. 27 2月, 2014 22 次提交
  3. 20 2月, 2014 9 次提交
  4. 11 2月, 2014 3 次提交
  5. 31 1月, 2014 2 次提交
  6. 09 1月, 2014 3 次提交