- 22 1月, 2019 4 次提交
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由 Eric Blake 提交于
The next commit will add an EXAMPLES section to qemu-nbd.8; for that to work, we need to recognize EXAMPLES in texi2pod. We also need to add a dependency from all man pages against the generator script, since a change to the generator may cause the resulting man page to differ. Signed-off-by: NEric Blake <eblake@redhat.com> Reviewed-by: NRichard W.M. Jones <rjones@redhat.com> Message-Id: <20190117193658.16413-3-eblake@redhat.com> Reviewed-by: NVladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
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由 Eric Blake 提交于
We have a race between the nbd server and the client both trying to report errors at once which can make the test sometimes fail if the output lines swap order under load. Break the race by collecting server messages into a file and then replaying that at the end of the test. We may yet want to fix the server to not output ANYTHING for a client action except when -v was used (to avoid malicious clients from being able to DoS a server by filling up its logs), but that is saved for a future patch. Signed-off-by: NEric Blake <eblake@redhat.com> CC: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20190117193658.16413-2-eblake@redhat.com> Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com>
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由 Peter Maydell 提交于
MIPS queue for January 17, 2019 - v2 # gpg: Signature made Fri 18 Jan 2019 15:55:35 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-january-17-2019-v2: target/mips: Introduce 32 R5900 multimedia registers target/mips: Rename 'rn' to 'register_name' target/mips: Add CP0 register MemoryMapID target/mips: Amend preprocessor constants for CP0 registers target/mips: Update ITU to handle bus errors target/mips: Update ITU to utilize SAARI and SAAR CP0 registers target/mips: Add field and R/W access to ITU control register ICR0 target/mips: Provide R/W access to SAARI and SAAR CP0 registers target/mips: Add fields for SAARI and SAAR CP0 registers target/mips: Use preprocessor constants for 32 major CP0 registers target/mips: Add preprocessor constants for 32 major CP0 registers target/mips: Move comment containing summary of CP0 registers Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
In virtio_balloon_get_config() we initialize a struct virtio_balloon_config which we then copy to guest memory. However, the local variable is not zero initialized. This works OK at the moment because we initialize all the fields in it; however an upcoming kernel header change will add some new fields. If we don't zero out the whole struct then we will start leaking a small amount of the contents of QEMU's stack to the guest as soon as we update linux-headers/ to a set of headers that includes the new fields. Cc: qemu-stable@nongnu.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190118183603.24757-1-peter.maydell@linaro.org
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- 21 1月, 2019 36 次提交
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由 Alex Bennée 提交于
The %lu format string is different depending on the host architecture which causes builds like the debian-armhf-cross build to fail. Use the correct PRi64 format string. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NPaul Durrant <paul.durrant@citrix.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190116121350.23863-1-alex.bennee@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
target-arm queue: * hw/char/stm32f2xx_usart: Do not update data register when device is disabled * hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node * target/arm: Allow Aarch32 exception return to switch from Mon->Hyp * ftgmac100: implement the new MDIO interface on Aspeed SoC * implement the ARMv8.3-PAuth extension * improve emulation of the ARM PMU # gpg: Signature made Mon 21 Jan 2019 10:42:11 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190121: (48 commits) target/arm: Implement PMSWINC target/arm: PMU: Set PMCR.N to 4 target/arm: PMU: Add instruction and cycle events target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] target/arm: Define FIELDs for ID_DFR0 target/arm: Implement PMOVSSET target/arm: Allow AArch32 access for PMCCFILTR target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Swap PMU values before/after migrations target/arm: Reorganize PMCCNTR accesses migration: Add post_save function to VMStateDescription target/arm: Tidy TBI handling in gen_a64_set_pc target/arm: Enable PAuth for user-only target/arm: Enable PAuth for -cpu max target/arm: Add PAuth system registers target/arm: Implement pauth_computepac target/arm: Implement pauth_addpac target/arm: Implement pauth_auth ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
The ipmi-bt-test fails intermittently, especially on the NetBSD VM. The frequency of this failure has recently gone up sharply to the point that I'm having to retry the NetBSD build multiple times to get a pass when merging pull requests. Disable the test until we can figure out why it's failing. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190118185402.3065-1-peter.maydell@linaro.org
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由 Aaron Lindsay 提交于
Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-14-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
This both advertises that we support four counters and enables them because the pmu_num_counters() reads this value from PMCR. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-13-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-12-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
Add arrays to hold the registers, the definitions themselves, access functions, and logic to reset counters when PMCR.P is set. Update filtering code to support counters other than PMCCNTR. Support migration with raw read/write functions. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-11-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Because the value of PMCEID[01] depends upon which events are supported at runtime, generate it dynamically. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-10-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-9-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
This is immediately necessary for the PMUv3 implementation to check ID_DFR0.PerfMon to enable/disable specific features, but defines the full complement of fields for possible future use elsewhere. Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-8-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
Add an array for PMOVSSET so we only define it for v7ve+ platforms Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-7-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-6-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only return 'true' if the specified counter is enabled and neither prohibited or filtered. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Signed-off-by: NAaron Lindsay <aclindsa@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-5-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in pmu_op_start/finish functions which can be called before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: NAaron Lindsay <aclindsa@gmail.com> Signed-off-by: NAaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-4-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. Consolidate the duplicated code into two functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to c15_ccnt in CPUARMState so that we can simultaneously save both the architectural register value and the last underlying cycle count - this ensures time isn't lost and will also allow us to access the 'old' architectural register value in order to detect overflows in later patches. Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Signed-off-by: NAaron Lindsay <aclindsa@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-3-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aaron Lindsay 提交于
In some cases it may be helpful to modify state before saving it for migration, and then modify the state back after it has been saved. The existing pre_save function provides half of this functionality. This patch adds a post_save function to provide the second half. Signed-off-by: NAaron Lindsay <aclindsa@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 20181211151945.29137-2-aaron@os.amperecomputing.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
We can perform this with fewer operations. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-32-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Add 4 attributes that controls the EL1 enable bits, as we may not always want to turn on pointer authentication with -cpu max. However, by default they are enabled. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-31-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-30-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-29-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
This is the main crypto routine, an implementation of QARMA. This matches, as much as possible, ARM pseudocode. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-28-richard.henderson@linaro.org [PMM: fixed minor checkpatch nits] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
This is not really functional yet, because the crypto is not yet implemented. This, however follows the AddPAC pseudo function. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-27-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
This is not really functional yet, because the crypto is not yet implemented. This, however follows the Auth pseudo function. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-26-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Stripping out the authentication data does not require any crypto, it merely requires the virtual address parameters. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-25-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-24-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Use TBID in aa64_va_parameters depending on the data parameter. This automatically updates all existing users of the function. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-23-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
We will want to check TBI for I and D simultaneously. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-22-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
We need to reuse this from helper-a64.c. Provide a stub definition for CONFIG_USER_ONLY. This matches the stub definitions that we removed for arm_regime_tbi{0,1} before. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-21-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
We will shortly want to talk about TBI as it relates to data. Passing around a pair of variables is less convenient than a single variable. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-20-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Split out functions to extract the virtual address parameters. Let the functions choose T0 or T1 address space half, if present. Extract (most of) the control bits that vary between EL or Tx. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-19-richard.henderson@linaro.org [PMM: fixed minor checkpatch comment nits] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
While we could expose stage_1_mmu_idx, the combination is probably going to be more useful. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-18-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
The pattern ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); is computing the full ARMMMUIdx, stripping off the ARM bits, and then putting them back. Avoid the extra two steps with the appropriate helper function. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-17-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
This function is, or will shortly become, too big to inline. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-16-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Not that there are any stores involved, but why argue with ARM's naming convention. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-15-richard.henderson@linaro.org [fixed trivial comment nit] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-14-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
This will enable PAuth decode in a subsequent patch. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-13-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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