1. 10 5月, 2018 1 次提交
    • P
      Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-2.13-minor-fixes-3' into staging · a8a94ef7
      Peter Maydell 提交于
      RISC-V: QEMU 2.13 Minor Fixes
      
      * Require libfdt when configuring for 'riscv*-softmmu'
      * Increase HTIF priority and allow zero base address
      
      # gpg: Signature made Wed 09 May 2018 11:15:33 BST
      # gpg:                using DSA key 6BF1D7B357EF3E4F
      # gpg: Good signature from "Michael Clark <michaeljclark@mac.com>"
      # gpg:                 aka "Michael Clark <mjc@sifive.com>"
      # gpg:                 aka "Michael Clark <michael@metaparadigm.com>"
      # gpg: WARNING: This key is not certified with a trusted signature!
      # gpg:          There is no indication that the signature belongs to the owner.
      # Primary key fingerprint: 7C99 930E B17C D8BA 073D  5EFA 6BF1 D7B3 57EF 3E4F
      
      * remotes/riscv/tags/riscv-qemu-2.13-minor-fixes-3:
        riscv: requires libfdt
        riscv: htif: increase the priority of the htif subregion
        riscv: spike: allow base == 0
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      a8a94ef7
  2. 09 5月, 2018 4 次提交
    • K
      riscv: requires libfdt · a666409f
      KONRAD Frederic 提交于
      When compiling on a machine without libfdt installed the configure script
      should try to get libfdt from the git or should die because otherwise
      CONFIG_LIBFDT is not set and the build process end in an error in the link
      phase.. eg:
      
      hw/riscv/virt.o: In function `riscv_virt_board_init':
      qemu/src/hw/riscv/virt.c:317: undefined reference to `qemu_fdt_setprop_cell'
      qemu/src/hw/riscv/virt.c:319: undefined reference to `qemu_fdt_setprop_cell'
      qemu/src/hw/riscv/virt.c:345: undefined reference to `qemu_fdt_dumpdtb'
      collect2: error: ld returned 1 exit status
      make[1]: *** [qemu-system-riscv64] Error 1
      make: *** [subdir-riscv64-softmmu] Error 2
      
      Cc: qemu-stable@nongnu.org
      Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Reviewed-by: NMichael Clark <mjc@sifive.com>
      Signed-off-by: NKONRAD Frederic <frederic.konrad@adacore.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      
      Message-Id: <1525360636-18229-4-git-send-email-frederic.konrad@adacore.com>
      a666409f
    • K
      riscv: htif: increase the priority of the htif subregion · 6fad7d18
      KONRAD Frederic 提交于
      The htif device is supposed to be mapped over an other subregion. So increase
      its priority to one to avoid any conflict.
      
      Here is the output of info mtree:
      
      Before:
      (qemu) info mtree
       address-space: memory
         0000000000000000-ffffffffffffffff (prio 0, i/o): system
           0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
           0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
           0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
           0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
      
       address-space: I/O
         0000000000000000-000000000000ffff (prio 0, i/o): io
      
       address-space: cpu-memory-0
         0000000000000000-ffffffffffffffff (prio 0, i/o): system
           0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
           0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
           0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
           0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
      
      After:
       (qemu) info mtree
       address-space: memory
         0000000000000000-ffffffffffffffff (prio 0, i/o): system
           0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
           0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
           0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
           0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
      
       address-space: I/O
         0000000000000000-000000000000ffff (prio 0, i/o): io
      
       address-space: cpu-memory-0
         0000000000000000-ffffffffffffffff (prio 0, i/o): system
           0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
           0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
           0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
           0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
      Reviewed-by: NMichael Clark <mjc@sifive.com>
      Signed-off-by: NKONRAD Frederic <frederic.konrad@adacore.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      
      Message-Id: <1525360636-18229-3-git-send-email-frederic.konrad@adacore.com>
      6fad7d18
    • K
      riscv: spike: allow base == 0 · 17b9751e
      KONRAD Frederic 提交于
      The sanity check on base doesn't allow htif to be mapped @0. Check if the
      symbol exists instead so we can map it where we want.
      Reviewed-by: NMichael Clark <mjc@sifive.com>
      Signed-off-by: NKONRAD Frederic <frederic.konrad@adacore.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      
      Message-Id: <1525360636-18229-2-git-send-email-frederic.konrad@adacore.com>
      17b9751e
    • P
      Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into staging · e5cd6952
      Peter Maydell 提交于
      # gpg: Signature made Tue 08 May 2018 16:18:22 BST
      # gpg:                using RSA key BDBE7B27C0DE3057
      # gpg: Good signature from "Jeffrey Cody <jcody@redhat.com>"
      # gpg:                 aka "Jeffrey Cody <jeff@codyprime.org>"
      # gpg:                 aka "Jeffrey Cody <codyprime@gmail.com>"
      # Primary key fingerprint: 9957 4B4D 3474 90E7 9D98  D624 BDBE 7B27 C0DE 3057
      
      * remotes/cody/tags/block-pull-request:
        sheepdog: Fix sd_co_create_opts() memory leaks
        iotests: Add test for cancelling a mirror job
        block/mirror: Make cancel always cancel pre-READY
        block/mirror: honor ratelimit again
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      e5cd6952
  3. 08 5月, 2018 9 次提交
    • K
      sheepdog: Fix sd_co_create_opts() memory leaks · a2cb9239
      Kevin Wolf 提交于
      Both the option string for the 'redundancy' option and the
      SheepdogRedundancy object that is created accordingly could be leaked in
      error paths. This fixes the memory leaks.
      
      Reported by Coverity (CID 1390614 and 1390641).
      Signed-off-by: NKevin Wolf <kwolf@redhat.com>
      Message-id: 20180503153509.22223-1-kwolf@redhat.com
      Reviewed-by: NJeff Cody <jcody@redhat.com>
      Signed-off-by: NJeff Cody <jcody@redhat.com>
      a2cb9239
    • M
      iotests: Add test for cancelling a mirror job · dc885fff
      Max Reitz 提交于
      We already have an extensive mirror test (041) which does cover
      cancelling a mirror job, especially after it has emitted the READY
      event.  However, it does not check what exact events are emitted after
      block-job-cancel is executed.  More importantly, it does not use
      throttling to ensure that it covers the case of block-job-cancel before
      READY.
      
      It would be possible to add this case to 041, but considering it is
      already our largest test file, it makes sense to create a new file for
      these cases.
      Signed-off-by: NMax Reitz <mreitz@redhat.com>
      Message-id: 20180501220509.14152-3-mreitz@redhat.com
      Signed-off-by: NJeff Cody <jcody@redhat.com>
      dc885fff
    • M
      block/mirror: Make cancel always cancel pre-READY · eb36639f
      Max Reitz 提交于
      Commit b76e4458 made the mirror block
      job respect block-job-cancel's @force flag: With that flag set, it would
      now always really cancel, even post-READY.
      
      Unfortunately, it had a side effect: Without that flag set, it would now
      never cancel, not even before READY.  Considering that is an
      incompatible change and not noted anywhere in the commit or the
      description of block-job-cancel's @force parameter, this seems
      unintentional and we should revert to the previous behavior, which is to
      immediately cancel the job when block-job-cancel is called before source
      and target are in sync (i.e. before the READY event).
      
      Cc: qemu-stable@nongnu.org
      Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1572856Reported-by: NYanan Fu <yfu@redhat.com>
      Signed-off-by: NMax Reitz <mreitz@redhat.com>
      Reviewed-by: NEric Blake <eblake@redhat.com>
      Message-id: 20180501220509.14152-2-mreitz@redhat.com
      Reviewed-by: NJeff Cody <jcody@redhat.com>
      Signed-off-by: NJeff Cody <jcody@redhat.com>
      eb36639f
    • S
      block/mirror: honor ratelimit again · ddc4115e
      Stefan Hajnoczi 提交于
      Commit b76e4458 ("block/mirror: change
      the semantic of 'force' of block-job-cancel") accidentally removed the
      ratelimit in the mirror job.
      
      Reintroduce the ratelimit but keep the block-job-cancel force=true
      behavior that was added in commit
      b76e4458.
      
      Note that block_job_sleep_ns() returns immediately when the job is
      cancelled.  Therefore it's safe to unconditionally call
      block_job_sleep_ns() - a cancelled job does not sleep.
      
      This commit fixes the non-deterministic qemu-iotests 185 output.  The
      test relies on the ratelimit to make the job sleep until the 'quit'
      command is processed.  Previously the job could complete before the
      'quit' command was received since there was no ratelimit.
      
      Cc: Liang Li <liliang.opensource@gmail.com>
      Cc: Jeff Cody <jcody@redhat.com>
      Cc: Kevin Wolf <kwolf@redhat.com>
      Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
      Message-id: 20180424123527.19168-1-stefanha@redhat.com
      Signed-off-by: NJeff Cody <jcody@redhat.com>
      ddc4115e
    • P
      Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging · cc8f8ba7
      Peter Maydell 提交于
      Machine queue, 2018-05-07
      
      * pc-dimm: factor out MemoryDevice
        (virtio-pmem and virtio-mem will make use of the new abstraction later)
      * scripts/device-crash-test: Removed fixed CAN entries
      
      # gpg: Signature made Mon 07 May 2018 18:01:42 BST
      # gpg:                using RSA key 2807936F984DC5A6
      # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
      # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6
      
      * remotes/ehabkost/tags/machine-next-pull-request:
        scripts/device-crash-test: Removed fixed CAN entries
        vl: allow 'maxmem' without 'slot'
        spapr: rename "hotplug memory" terminology to "device memory"
        pc: rename "hotplug memory" terminology to "device memory"
        machine: rename MemoryHotplugState to DeviceMemoryState
        pc-dimm: move actual plug/unplug of a memory region to MemoryDevice
        pc-dimm: factor out capacity and slot checks into MemoryDevice
        pc-dimm: factor out address search into MemoryDevice code
        pc-dimm: pass in the machine and to the MemoryHotplugState
        pc-dimm: no need to pass the memory region
        machine: make MemoryHotplugState accessible via the machine
        pc-dimm: factor out MemoryDevice interface
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      cc8f8ba7
    • P
      Merge remote-tracking branch 'remotes/kraxel/tags/vga-20180507-pull-request' into staging · d01beac1
      Peter Maydell 提交于
      qxl: fix local renderer crash
      
      # gpg: Signature made Mon 07 May 2018 10:52:09 BST
      # gpg:                using RSA key 4CB6D8EED3E87138
      # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
      # gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
      # gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
      # Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138
      
      * remotes/kraxel/tags/vga-20180507-pull-request:
        qxl: fix local renderer crash
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      d01beac1
    • P
      Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-2.13-pull-20180506' into staging · 3add3f7e
      Peter Maydell 提交于
      RISC-V: QEMU 2.13 Privileged ISA emulation updates
      
      Several code cleanups, minor specification conformance changes,
      fixes to make ROM read-only and add device-tree size checks.
      
      * Honour privileged ISA v1.10 counter enable CSRs.
      * Implements WARL behavior for CSRs that don't support writes
        * Past behavior of raising traps was non-conformant
          with the RISC-V Privileged ISA Specification v1.10.
      * Allow S-mode access to sstatus.MXR when priv ISA >= v1.10
      * Sets mtval/stval to zero on exceptions without addresses
        * Past behavior of leaving the last value was non-conformant
          with the RISC-V Privileged ISA Specition v1.10. mtval/stval
          must be set on all exceptions; to zero if not supported.
      * Make ROMs read-only and implement device-tree size checks
        * Uses memory_region_init_rom and rom_add_blob_fixed_as
      * Adds hexidecimal instruction bytes to disassembly output.
      * Fixes missing break statement for rv128 disassembly.
      * Several code cleanups
        * Replacing hard-coded constants with enums
        * Dead-code elimination
      
      This is an incremental pull that contains 20 reviewed changes out
      of 38 changes currently queued in the qemu-2.13-for-upstream branch.
      
      # gpg: Signature made Sun 06 May 2018 00:27:37 BST
      # gpg:                using DSA key 6BF1D7B357EF3E4F
      # gpg: Good signature from "Michael Clark <michaeljclark@mac.com>"
      # gpg:                 aka "Michael Clark <mjc@sifive.com>"
      # gpg:                 aka "Michael Clark <michael@metaparadigm.com>"
      # gpg: WARNING: This key is not certified with a trusted signature!
      # gpg:          There is no indication that the signature belongs to the owner.
      # Primary key fingerprint: 7C99 930E B17C D8BA 073D  5EFA 6BF1 D7B3 57EF 3E4F
      
      * remotes/riscv/tags/riscv-qemu-2.13-pull-20180506:
        RISC-V: Mark ROM read-only after copying in code
        RISC-V: No traps on writes to misa,minstret,mcycle
        RISC-V: Make mtvec/stvec ignore vectored traps
        RISC-V: Add mcycle/minstret support for -icount auto
        RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10
        RISC-V: Allow S-mode mxr access when priv ISA >= v1.10
        RISC-V: Clear mtval/stval on exceptions without info
        RISC-V: Hardwire satp to 0 for no-mmu case
        RISC-V: Update E and I extension order
        RISC-V: Remove erroneous comment from translate.c
        RISC-V: Remove EM_RISCV ELF_MACHINE indirection
        RISC-V: Make virt header comment title consistent
        RISC-V: Make some header guards more specific
        RISC-V: Fix missing break statement in disassembler
        RISC-V: Include instruction hex in disassembly
        RISC-V: Remove unused class definitions
        RISC-V: Remove identity_translate from load_elf
        RISC-V: Use ROM base address and size from memmap
        RISC-V: Make virt board description match spike
        RISC-V: Replace hardcoded constants with enum values
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      3add3f7e
    • P
      Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180507-pull-request' into staging · 302a84e8
      Peter Maydell 提交于
      usb: fixes for mtp and host.
      
      # gpg: Signature made Mon 07 May 2018 10:44:26 BST
      # gpg:                using RSA key 4CB6D8EED3E87138
      # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
      # gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
      # gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
      # Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138
      
      * remotes/kraxel/tags/usb-20180507-pull-request:
        usb-host: skip open on pending postload bh
        usb-mtp: Unconditionally check for the readonly bit
        usb-mtp: Add some NULL checks for issues pointed out by coverity
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      302a84e8
    • G
      ppc: e500: use g_strdup_printf() instead of snprintf() · 2fb513d3
      Greg Kurz 提交于
      qemu-system-ppc fails to build with GCC 8.0.1:
      
      /home/hsp/src/qemu-master/hw/ppc/e500.c: In function ‘ppce500_load_device_tree’:
      /home/hsp/src/qemu-master/hw/ppc/e500.c:442:37: error: ‘/pic@’
      directive output may be truncated writing 5 bytes into a region of
      size between 1 and 128 [-Werror=format-truncation=]
           snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
                                           ^~~~~
      In file included from /usr/include/stdio.h:862,
                       from /home/hsp/src/qemu-master/include/qemu/osdep.h:68,
                       from /home/hsp/src/qemu-master/hw/ppc/e500.c:17:
      /usr/include/bits/stdio2.h:64:10: note: ‘__builtin___snprintf_chk’
      output between 11 and 138 bytes into a destination of size 128
         return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1,
                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
              __bos (__s), __fmt, __va_arg_pack ());
              ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      /home/hsp/src/qemu-master/hw/ppc/e500.c:470:39: error:
      ‘/global-utilities@’ directive output may be truncated writing 18
      bytes into a region of size between 1 and 128
      [-Werror=format-truncation=]
           snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
                                             ^~~~~~~~~~~~~~~~~~
      In file included from /usr/include/stdio.h:862,
                       from /home/hsp/src/qemu-master/include/qemu/osdep.h:68,
                       from /home/hsp/src/qemu-master/hw/ppc/e500.c:17:
      /usr/include/bits/stdio2.h:64:10: note: ‘__builtin___snprintf_chk’
      output between 24 and 151 bytes into a destination of size 128
         return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1,
                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
              __bos (__s), __fmt, __va_arg_pack ());
              ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      /home/hsp/src/qemu-master/hw/ppc/e500.c:477:36: error: ‘/msi@’
      directive output may be truncated writing 5 bytes into a region of
      size between 0 and 127 [-Werror=format-truncation=]
           snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
                                          ^~~~~
      In file included from /usr/include/stdio.h:862,
                       from /home/hsp/src/qemu-master/include/qemu/osdep.h:68,
                       from /home/hsp/src/qemu-master/hw/ppc/e500.c:17:
      /usr/include/bits/stdio2.h:64:10: note: ‘__builtin___snprintf_chk’
      output between 12 and 139 bytes into a destination of size 128
         return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1,
                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
              __bos (__s), __fmt, __va_arg_pack ());
              ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      
      Fix this by converting e500 to use g_strdup_printf()+g_free() instead
      of snprintf(). This is done globally, even for call sites that don't
      break build, since this is the preferred practice in QEMU.
      Reported-by: NHoward Spoelstra <hsp.cat7@gmail.com>
      Signed-off-by: NGreg Kurz <groug@kaod.org>
      Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Reviewed-by: NEric Blake <eblake@redhat.com>
      Message-id: 152568372989.443627.900708381919207053.stgit@bahia.lan
      Cc: qemu-stable@nongnu.org
      Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      2fb513d3
  4. 07 5月, 2018 16 次提交
  5. 06 5月, 2018 10 次提交
    • M
      RISC-V: Mark ROM read-only after copying in code · 5aec3247
      Michael Clark 提交于
      The sifive_u machine already marks its ROM readonly however
      it has the wrong base address for its mask ROM. This patch
      fixes the sifive_u mask ROM base address.
      
      This commit makes all other boards consistently use mask_rom
      as the variable name for their ROMs. Boards that use device
      tree now check that that the device tree fits in the assigned
      ROM space using the new qemu_fdt_totalsize(void *fdt)
      interface, adding a bounds check and error message. This
      can detect truncation.
      
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      Reviewed-by: NAlistair Francis <Alistair.Francis@wdc.com>
      5aec3247
    • M
      RISC-V: No traps on writes to misa,minstret,mcycle · b8643bd6
      Michael Clark 提交于
      These fields are marked WARL (Write Any Values, Reads
      Legal Values) in the RISC-V Privileged Architecture
      Specification so instead of raising exceptions,
      illegal writes are silently dropped.
      
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      b8643bd6
    • M
      RISC-V: Make mtvec/stvec ignore vectored traps · 1d1ee552
      Michael Clark 提交于
      Vectored traps for asynchrounous interrupts are optional.
      The mtvec/stvec mode field is WARL and hence does not trap
      if an illegal value is written. Illegal values are ignored.
      
      Later we can add RISCV_FEATURE_VECTORED_TRAPS however
      until then the correct behavior for WARL (Write Any, Read
      Legal) fields is to drop writes to unsupported bits.
      
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      1d1ee552
    • M
      RISC-V: Add mcycle/minstret support for -icount auto · 6fce529c
      Michael Clark 提交于
      Previously the mycycle/minstret CSRs and rdcycle/rdinstret
      psuedo instructions would return the time as a proxy for an
      increasing instruction counter in the absence of having a
      precise instruction count. If QEMU is invoked with -icount,
      the mcycle/minstret CSRs and rdcycle/rdinstret psuedo
      instructions will return the instruction count.
      
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
      6fce529c
    • M
      RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 · 8c59f5c1
      Michael Clark 提交于
      Privileged ISA v1.9.1 defines mscounteren and mucounteren:
      
      * mscounteren contains a mask of counters available to S-mode
      * mucounteren contains a mask of counters available to U-mode
      
      Privileged ISA v1.10 defines mcounteren and scounteren:
      
      * mcounteren contains a mask of counters available to S-mode
      * scounteren contains a mask of counters available to U-mode
      
      mcounteren and scounteren CSR registers were implemented
      however they were not honoured for counter accesses when
      the privilege ISA was >= v1.10. This fix solves the issue
      by coalescing the counter enable registers. In addition
      the code now  generates illegal instruction exceptions
      for accesses to the counter enabled registers depending
      on the privileged ISA version.
      
      - Coalesce mscounteren and mcounteren into one variable
      - Coalesce mucounteren and scounteren into one variable
      - Makes mcounteren and scounteren CSR accesses generate
        illegal instructions when the privileged ISA <= v1.9.1
      - Makes mscounteren and mucounteren CSR accesses generate
        illegal instructions when the privileged ISA >= v1.10
      
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      8c59f5c1
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      RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 · e2165905
      Michael Clark 提交于
      The mstatus.MXR alias in sstatus should only be writable
      by S-mode if the privileged ISA version >= v1.10. Also MXR
      was masked in sstatus CSR read but not sstatus CSR writes.
      Now we correctly mask sstatus.mxr in both read and write.
      
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
      e2165905
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      RISC-V: Clear mtval/stval on exceptions without info · 67185dad
      Michael Clark 提交于
      mtval/stval must be set on all exceptions but zero is
      a legal value if there is no exception specific info.
      Placing the instruction bytes for illegal instruction
      exceptions in mtval/stval is an optional feature and
      is currently not supported by QEMU RISC-V.
      
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
      67185dad
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      RISC-V: Hardwire satp to 0 for no-mmu case · 33e3bc8d
      Michael Clark 提交于
      satp is WARL so it should not trap on illegal writes, rather
      it can be hardwired to zero and silently ignore illegal writes.
      
      It seems the RISC-V WARL behaviour is preferred to having to
      trap overhead versus simply reading back the value and checking
      if the write took (saves hundreds of cycles and more complex
      trap handling code).
      
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
      33e3bc8d
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      RISC-V: Update E and I extension order · 79f86934
      Michael Clark 提交于
      Section 22.8 Subset Naming Convention of the RISC-V ISA Specification
      defines the canonical order for extensions in the ISA string. It is
      silent on the position of the E extension however E is a substitute
      for I so it must come early in the extension list order. A comment
      is added to state E and I are mutually exclusive, as the E extension
      will be added to the RISC-V port in the future.
      
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
      79f86934
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      RISC-V: Remove erroneous comment from translate.c · 8d196c43
      Michael Clark 提交于
      Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
      Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Alistair Francis <Alistair.Francis@wdc.com>
      Signed-off-by: NMichael Clark <mjc@sifive.com>
      Reviewed-by: NPalmer Dabbelt <palmer@sifive.com>
      Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
      8d196c43