If slirp needs to emulate tcp timeout, then the timeout value
for mainloop should be more precise, which is determined by
slirp's fasttimo or slowtimo. Achieve this by swap the logic
sequence of slirp_pollfds_fill and slirp_update_timeout.
Signed-off-by: NLiu Ping Fan <pingfank@linux.vnet.ibm.com>
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>

Signed-off-by: NLiu Ping Fan <pingfank@linux.vnet.ibm.com>
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>

Each slirp has its own time to caculate timeout.
Signed-off-by: NLiu Ping Fan <pingfank@linux.vnet.ibm.com>
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>

ARM queue:
 * aarch64 preparation patchset (excluding the defconfigs, so this
   doesn't actually enable the new targets yet)
 * minor bugfixes and cleanups
 * disable "-cpu any" in system emulation mode
 * fix ARMv7M stack alignment on reset

# gpg: Signature made Tue 10 Sep 2013 01:46:11 PM CDT using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found

# By Alexander Graf (13) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-20130910: (28 commits)
  configure: Add handling code for AArch64 targets
  linux-user: Add AArch64 support
  linux-user: Allow targets to specify a minimum uname release
  linux-user: Add AArch64 termbits.h definitions
  linux-user: Implement cpu_set_tls() and cpu_clone_regs() for AArch64
  linux-user: Make sure NWFPE code is 32 bit ARM only
  linux-user: Add signal handling for AArch64
  linux-user: Fix up AArch64 syscall handlers
  linux-user: Add syscall number definitions for AArch64
  linux-user: Add cpu loop for AArch64
  linux-user: Don't treat AArch64 cpu names specially
  target-arm: Add AArch64 gdbstub support
  target-arm: Add AArch64 translation stub
  target-arm: Prepare translation for AArch64 code
  target-arm: Disable 32 bit CPUs in 64 bit linux-user builds
  target-arm: Add new AArch64CPUInfo base class and subclasses
  target-arm: Pass DisasContext* to gen_set_pc_im()
  target-arm: Fix target_ulong/uint32_t confusions
  target-arm: Export cpu_env
  target-arm: Extract the disas struct to a header file
  ...

Message-id: 1378839142-7726-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>

# By Cole Robinson
# Via Luiz Capitulino
* luiz/queue/qmp:
  qapi-types.py: Fix enum struct sizes on i686

Message-id: 1378822364-13887-1-git-send-email-lcapitulino@redhat.com
Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>

# By Gerd Hoffmann (2) and Christophe Fergeau (1)
# Via Gerd Hoffmann
* spice/spice.v73:
  qxl: fix local renderer
  qxl: trace io port name
  spice-core: Use g_strdup_printf instead of snprintf

Message-id: 1378807572-27902-1-git-send-email-kraxel@redhat.com
Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>

# By Gerd Hoffmann (2) and Miroslav Rezanina (2)
# Via Gerd Hoffmann
* kraxel/usb.89:
  ehci: save device pointer in EHCIState
  Remove dev-bluetooth.c dependency from vl.c
  Preparation for usb-bt-dongle conditional build
  usb: sanity check setup_index+setup_len in post_load

Message-id: 1378806073-25197-1-git-send-email-kraxel@redhat.com
Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>

# By Tomoki Sekiyama (10) and Paul Burton (1)
# Via Michael Roth
* mdroth/qga-pull-2013-9-9:
  QMP/qemu-ga-client: Make timeout longer for guest-fsfreeze-freeze command
  qemu-ga: Install Windows VSS provider on `qemu-ga -s install'
  qemu-ga: Call Windows VSS requester in fsfreeze command handler
  qemu-ga: Add Windows VSS provider and requester as DLL
  error: Add error_set_win32 and error_setg_win32
  qemu-ga: Add configure options to specify path to Windows/VSS SDK
  Add a script to extract VSS SDK headers on POSIX system
  checkpatch.pl: Check .cpp files
  Add c++ keywords to QAPI helper script
  configure: Support configuring C++ compiler
  mips_malta: support up to 2GiB RAM

Message-id: 1378755701-2051-1-git-send-email-mdroth@linux.vnet.ibm.com
Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>

# By Anthony PERARD
# Via Stefano Stabellini
* sstabellini/xen-2013-09-09:
  pc_q35: Initialize Xen.
  pc: Initializing ram_memory under Xen.

Message-id: alpine.DEB.2.02.1309091718030.6397@kaball.uk.xensource.com
Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>

# By Paolo Bonzini (21) and others
# Via Stefan Hajnoczi
* stefanha/block: (42 commits)
  qemu-iotests: Fixed test case 026
  qemu-iotests: Whitespace cleanup
  dataplane: Fix startup race.
  block: look for zero blocks in bs->file
  block: add default get_block_status implementation for protocols
  raw-posix: report unwritten extents as zero
  raw-posix: return get_block_status data and flags
  docs, qapi: document qemu-img map
  qemu-img: add a "map" subcommand
  block: return BDRV_BLOCK_ZERO past end of backing file
  block: use bdrv_has_zero_init to return BDRV_BLOCK_ZERO
  block: return get_block_status data and flags for formats
  block: define get_block_status return value
  block: introduce bdrv_get_block_status API
  block: make bdrv_has_zero_init return false for copy-on-write-images
  qemu-img: always probe the input image for allocated sectors
  block: expect errors from bdrv_co_is_allocated
  block: remove bdrv_is_allocated_above/bdrv_co_is_allocated_above distinction
  block: do not use ->total_sectors in bdrv_co_is_allocated
  block: make bdrv_co_is_allocated static
  ...

Message-id: 1378481953-23099-1-git-send-email-stefanha@redhat.com
Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>

# By Brad Smith (2) and others
# Via Stefan Hajnoczi
* stefanha/net:
  ne2000: mark I/O as LITTLE_ENDIAN
  vmxnet3: Eliminate __packed redefined warning
  e1000: add interrupt mitigation support
  net: Rename send_queue to incoming_queue
  tap: Use numbered tap/tun devices on all *BSD OS's

Message-id: 1378481624-20964-1-git-send-email-stefanha@redhat.com
Signed-off-by: NAnthony Liguori <anthony@codemonkey.ws>

Add the necessary code to configure to handle AArch64 as a target
CPU (we already have some code for supporting it as host). Note
that this doesn't enable the AArch64 targets yet.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-23-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-12-git-send-email-john.rigby@linaro.org
[PMM:
 * don't need to set TARGET_ABI_DIR to aarch64 as that is the default
 * don't build nwfpe -- this is 32 bit legacy only
 * rewrite commit message
 * add aarch64 to the list of "fdt required" targets
]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

This patch adds support for AArch64 in all the small corners of
linux-user (primarily in image loading and startup code).
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-22-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-11-git-send-email-john.rigby@linaro.org
[PMM:
 * removed some unnecessary #defines from syscall.h
 * catch attempts to use a 32 bit only cpu with aarch64-linux-user
 * termios stuff moved into its own patch
 * we specify our minimum uname version here now
]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

For newer target architectures, glibc can be picky about the kernel
version: for example, it will not run on an aarch64 system unless
the kernel reports itself as at least 3.8.0. Accommodate this by
enhancing the existing support for faking the kernel version so
that each target can optionally specify a minimum version: if
the user doesn't force a specific fake version then we will override
with the minimum required version only if the real host kernel
version is insufficient.

Use this facility to let aarch64 report a minimum of 3.8.0.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-21-git-send-email-peter.maydell@linaro.org

Add the AArch64 termbits.h with all the target's termios related
constants and structures.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-20-git-send-email-peter.maydell@linaro.org
[PMM: split out from another patch]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-19-git-send-email-peter.maydell@linaro.org
[PMM: pulled out from another patch; don't use is_a64() here;
 moved to linux-user from target-arm]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

On ARM, linux-user emulation includes NWFPE support for emulating the
ancient FPA floating point coprocessor. This has long since been
superseded by VFP and is only required for legacy binaries. The
AArch64 linux-user target doesn't compile in NWFPE support, so make
sure the relevant code is protected by suitable ifdefs.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-18-git-send-email-peter.maydell@linaro.org

This patch adds signal handling for AArch64. The code is based on the
respective source in the Linux kernel.
Signed-off-by: NAndreas Schwab <schwab@suse.de>
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-17-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-10-git-send-email-john.rigby@linaro.org
[PMM: fixed style nits: tabs, long lines;
 pulled target_signal.h in from a later patch; it fits better here]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Some syscall handlers have special code for ARM enabled that we don't
need on AArch64. Exclude AArch64 in those cases. In other places we
can share struct definitions with other targets or have to provide our
own.

With this patch applied, most syscall definitions in linux-user should
be sound for AArch64.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-16-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-9-git-send-email-john.rigby@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

The AArch64 syscall definitions are all publicly available in the Linux
kernel. Let's add them to our linux-user emulation target, so that we
can easily handle AArch64 syscalls.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-15-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-8-git-send-email-john.rigby@linaro.org
[PMM: changes relating to cpu_loop() removed as they are superseded
 by an earlier patch]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add the main linux-user cpu loop for AArch64. Since AArch64
has a different system call interface, doesn't need to worry
about FPA emulation and may in the future keep the prefetch/data
abort information in different system registers, it's simplest
just to use a completely separate loop from the 32 bit ARM
target, rather than peppering it with ifdefs.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-14-git-send-email-peter.maydell@linaro.org

32-bit ARM has a lot of different names for different types of CPUs it supports.
On AArch64, we don't have this, so we really don't want to execute the 32-bit
logic. Stub it out for AArch64 linux-user guests.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-13-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-7-git-send-email-john.rigby@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

We want to be able to debug AArch64 guests. So let's add the respective gdb
stub functions and xml descriptions that allow us to do so.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-12-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-6-git-send-email-john.rigby@linaro.org
[PMM: dropped unused fp regs XML for now; moved 64 bit only functions
 to new gdbstub64.c; these are hooked up in AArch64CPU, not via
 ifdefs in ARMCPU]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode,
registers look vastly different, instruction encoding is completely different,
basically the system turns into a different machine.

So let's do a simple if() in translate.c to decide whether we can handle the
current code in the legacy AArch32 code or in the new AArch64 code.

So far, the translation always complains about unallocated instructions. There
is no emulator functionality in this patch!
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-11-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-5-git-send-email-john.rigby@linaro.org
[PMM:
 * provide no-op versions of a64 functions ifndef TARGET_AARCH64;
   this lets us avoid #ifdefs in translate.c
 * insert the missing call to disas_a64_insn()
 * stash the insn in the DisasContext rather than reloading it in
   real_unallocated_encoding()
]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

This patch adds all the prerequisites for AArch64 support that didn't
fit into split up patches. It extends important bits in the core cpu
headers to also take AArch64 mode into account.

Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag
indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org
[PMM:
 * rearranged tbflags so AArch64? is bit 31 and if it is set then
  30..0 are freely available for whatever makes most sense for that mode
 * added version bump since we change VFP migration state
 * added a comment about how VFP/Neon register state works
 * physical address space is 48 bits, not 64
 * added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs
]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

If we're building aarch64-linux-user then the 32 bit CPUs are
all unwanted, because they can't possibly execute the 64 bit
binaries we will be running; disable them.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-9-git-send-email-peter.maydell@linaro.org

Create a new AArch64CPU class; all 64-bit capable ARM
CPUs are subclasses of this. (Currently we only support
one, the "any" CPU used by linux-user.)
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-8-git-send-email-peter.maydell@linaro.org

We want gen_set_pc_im() to work for both AArch64 and AArch32, but
to do this we'll need the DisasContext* so we can tell which mode
we're in, so pass it in as a parameter.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-7-git-send-email-peter.maydell@linaro.org

Correct a few places that were using uint32_t or a 32 bit
only format string to handle something that should be a target_ulong.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-6-git-send-email-peter.maydell@linaro.org
[PMM: split out to separate patch; added gen_goto_tb() and
gen_set_pc_im() dest params to list of things to change.]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

The cpu_env tcg variable will be used by both the AArch32 and AArch64
handling code. Unstaticify it, so that both sides can make use of it.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-5-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-3-git-send-email-john.rigby@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

We will need to share the disassembly status struct between AArch32 and
AArch64 modes. So put it into a header file that both sides can use.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-4-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-2-git-send-email-john.rigby@linaro.org
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

AArch32 code (ie traditional 32 bit world) expects to be
able to pass a vaddr in a TCGv_i32. However when QEMU is
compiled with TARGET_LONG_BITS=32 the TCG load/store
functions take a TCGv_i64. Abstract out load/store with
a 32 bit vaddr so we have a place to put the zero extension
of the vaddr and the extension/truncation of the data value.

Apart from the function definitions most of this patch is
a simple s/tcg_gen_qemu_/gen_aa32_/.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-3-git-send-email-peter.maydell@linaro.org

The ARM EABI specifies that 64 bit integers should be
8 aligned; remove our incorrect setting of 4 alignment.
This has no actual effect since it only set the alignment
for the 'abi_ullong' and 'abi_llong' types, which are used
only inside code which is MIPS-specific, but it will
avoid problems later if we use the types elsewhere.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Clarify a comment about the ID register value presented by
the PL110 variant present on the VersatilePB board (based
on testing what the actual hardware does), to indicate that
this is not an error in our emulation, and to remove an #if-0.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Libvirt uses this to introspect available CPU models.
Signed-off-by: NCole Robinson <crobinso@redhat.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Message-id: c0bdcd6c7ea6a085a6902ccaa73180fd771c8267.1378303555.git.crobinso@redhat.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

When the initial SP is loaded from the vector table on ARMv7M systems the two
least significant bits are ignored as the stack is always aligned at a four byte
boundary (see ARM DDI 0403C, B1.4.1 and B1.5.5). So far QEMU did not ignore
these bits leading to a stack alignment inconsitent with real hardware for
binaries that rely on this behaviour. This patch fixes this issue by masking the
two least significant bits when loading the SP.
Signed-off-by: NSebastian Ottlik <ottlik@fzi.de>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1378286595-27072-1-git-send-email-ottlik@fzi.de
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Avoid the undefined behaviour of "1 << 31" by using 1U to make
the shift be of an unsigned value rather than shifting into the
sign bit of a signed integer. For consistency, we make all the
CPSR_* constants unsigned, though the only one which triggers
undefined behaviour is CPSR_N.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 1378391908-22137-3-git-send-email-peter.maydell@linaro.org

In the decode of ARM B and BL insns, swap the order of the
"append 2 implicit zeros to imm24" and the sign extend, and
use the new sextract32() utility function to do the latter.
This avoids a direct dependency on the undefined C behaviour
of shifting into the sign bit of an integer.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Message-id: 1378391908-22137-2-git-send-email-peter.maydell@linaro.org

Make the 'any' CPU for target-arm available only in linux-user mode.
The ARM target provides a CPU named "any", which turns on support for
all user-level instruction set extensions we know about. This is
intended for linux-user emulation mode, where it is the default CPU type.
It makes no sense to try to use this for system emulation, since we don't
initialize it with any system-level information like feature register
values or implementation specific cp15 registers. (Unsurprisingly, some
boards won't boot at all, though you might get lucky in some cases where
the guest doesn't happen to prod things that aren't there.)

Prevent users from making this command line error by removing the
CPU definition from the softmmu build.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Message-id: 1378213995-12945-1-git-send-email-peter.maydell@linaro.org

Unlike other list types, enum wasn't adding any padding, which caused
a mismatch between the generated struct size and GenericList struct
size. More details in a678e26c

This crashed qemu if calling qmp query-tpm-types for example, which
upsets libvirt capabilities probing. Reproducer on i686:

(sleep 5; printf '{"execute":"qmp_capabilities"}\n{"execute":"query-tpm-types"}\n') | ./i386-softmmu/qemu-system-i386 -S -nodefaults -nographic -M none -qmp stdio

https://bugs.launchpad.net/qemu/+bug/1219207

Cc: qemu-stable@nongnu.org
Signed-off-by: NCole Robinson <crobinso@redhat.com>
Reviewed-by: NEric Blake <eblake@redhat.com>
Tested-by: NRichard W.M. Jones <rjones@redhat.com>
Signed-off-by: NLuiz Capitulino <lcapitulino@redhat.com>