- 04 2月, 2014 7 次提交
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由 Orit Wasserman 提交于
Signed-off-by: NOrit Wasserman <owasserm@redhat.com> Reviewed-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: NJuan Quintela <quintela@redhat.com>
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由 Orit Wasserman 提交于
Signed-off-by: NOrit Wasserman <owasserm@redhat.com> Reviewed-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: NJuan Quintela <quintela@redhat.com>
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由 Gonglei (Arei) 提交于
When qemu do live migration with xbzrle, qemu malloc decoded_buf at destination end but free it at source end. It will crash qemu by double free error in some scenarios. Splitting the XBZRLE structure for clear logic distinguishing src/dst side. Signed-off-by: NChenLiang <chenliang88@huawei.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NOrit Wasserman <owasserm@redhat.com> Signed-off-by: NGongLei <arei.gonglei@huawei.com> Signed-off-by: NJuan Quintela <quintela@redhat.com>
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由 Orit Wasserman 提交于
Signed-off-by: NOrit Wasserman <owasserm@redhat.com> Reviewed-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NJuan Quintela <quintela@redhat.com>
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由 Orit Wasserman 提交于
Signed-off-by: NOrit Wasserman <owasserm@redhat.com> Reviewed-by: NJuan Quintela <quintela@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> Signed-off-by: NJuan Quintela <quintela@redhat.com>
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由 Alexey Kardashevskiy 提交于
The ae2810c4 patch introduced optimization for ram_list.dirty_memory update. However it can only work correctly if hpratio is 1 as the @bitmap parameter stores 1 bits per system page size (may vary, 4K or 64K on PPC64) and ram_list.dirty_memory stores 1 bit per TARGET_PAGE_SIZE (which is hardcoded to 4K). This fixes hpratio!=1 case to fall back to the slow path. Signed-off-by: NAlexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: NJuan Quintela <quintela@redhat.com>
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由 Peter Maydell 提交于
The VMSTATE_STRUCT_POINTER macros are a bit odd in that they must be passed an argument "FooType *" rather than just taking the FooType. They're only used in one place, so it's easy to tidy this up. This also lets us use the macro to replace the hand-rolled VMSTATE_PTIMER. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NJuan Quintela <quintela@redhat.com>
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- 03 2月, 2014 6 次提交
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由 Stefan Weil 提交于
__put_user can write bytes, words (2 bytes) or longwords (4 bytes). Here obviously words should have been written, but bytes were written, so values like 0x9c5f were truncated to 0x5f. Fix this by changing retcode from uint8_t to to uint16_t in target_signal_frame and also in the unused rt_signal_frame. This problem was reported by static code analysis (smatch). Cc: qemu-stable@nongnu.org Signed-off-by: NStefan Weil <sw@weilnetz.de> Acked-by: NRiku Voipio <riku.voipio@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Tested-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Edgar E. Iglesias 提交于
Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Edgar E. Iglesias 提交于
Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Edgar E. Iglesias 提交于
Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Edgar E. Iglesias 提交于
This is an internal error as the CRISv10 should mask interrupts while executing delay slots. Bail out sooner rather than later. Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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由 Edgar E. Iglesias 提交于
Reviewed-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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- 02 2月, 2014 4 次提交
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由 Peter Maydell 提交于
* qmp-unstable/queue/qmp: monitor: Cleanup mon->outbuf on write error virtio_rng: replace custom backend API with UserCreatable.complete() callback add optional 2nd stage initialization to -object/object-add commands vl.c: -object: don't ignore duplicate 'id' object_add: consolidate error handling Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
target-arm queue: * implementation of first part of the A64 Neon instruction set * v8 AArch32 rounding and 16<->64 fp conversion instructions * fix MIDR value on Zynq boards * some minor bugfixes/code cleanups # gpg: Signature made Fri 31 Jan 2014 15:06:34 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * pmaydell/tags/pull-target-arm-20140131: (34 commits) arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes arm_gic: Introduce define for GIC_NR_SGIS target-arm: A64: Add SIMD shift by immediate target-arm: A64: Add simple SIMD 3-same floating point ops target-arm: A64: Add integer ops from SIMD 3-same group target-arm: A64: Add logic ops from SIMD 3 same group target-arm: A64: Add top level decode for SIMD 3-same group target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops target-arm: A64: Add SIMD three-different ABDL instructions target-arm: A64: Add SIMD three-different multiply accumulate insns target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ target-arm: Add set_neon_rmode helper target-arm: Add support for AArch32 SIMD VRINTX target-arm: Add support for AArch32 FP VRINTX target-arm: Add support for AArch32 FP VRINTZ target-arm: Add support for AArch32 FP VRINTR target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM target-arm: Move arm_rmode_to_sf to a shared location. ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
vfio-pci updates include: - Destroy MemoryRegions on device teardown - Print warnings around PCI option ROM failures - Skip bogus mappings from 64bit BAR sizing - Act on DMA mapping failures - Fix alignment to avoid MSI-X table mapping - Fix debug macro typo # gpg: Signature made Tue 28 Jan 2014 15:27:47 GMT using RSA key ID 3BB08B22 # gpg: Can't check signature: public key not found * remotes/awilliam/tags/vfio-pci-for-qemu-20140128.0: vfio: correct debug macro typo vfio: fix mapping of MSIX bar kvm: initialize qemu_host_page_size vfio-pci: Fail initfn on DMA mapping errors vfio: Filter out bogus mappings vfio: Do not reattempt a failed rom read vfio: warn if host device rom can't be read vfio: Destroy memory regions Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
* remotes/sstabellini/xen-140130: address_space_translate: do not cross page boundaries Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 31 1月, 2014 23 次提交
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由 Christoffer Dall 提交于
Fix two bugs that would allow changing the state of SGIs through the ICPENDR and ISPENDRs. Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
Instead of hardcoding 16 various places in the code, use a define to make it more clear what is going on. Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alex Bennée 提交于
This implements a subset of the AdvSIMD shift operations (namely all the none saturating or narrowing ones). The actual shift generation code itself is common for both the scalar and vector cases but wrapped with either vector element iteration or the fp reg access. The rounding operations need to take special care to correctly reflect the result of adding rounding bits on high bits as the intermediates do not truncate. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Implement a simple subset of the SIMD 3-same floating point operations. This includes a common helper function used for both scalar and vector ops; FABD is the only currently implemented shared op. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Add some of the integer operations in the SIMD 3-same group: specifically, the comparisons, addition and subtraction. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL, BIT and BIF) from the SIMD 3 register same group (C3.6.16). Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Add top level decode for the A64 SIMD three regs same group (C3.6.16), splitting it into the pairwise, logical, float and integer subgroups. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Implement the add, sub and compare ops from the SIMD "scalar three same" group. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Implement the absolute-difference instructions in the SIMD three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL, SABDL2, UABDL, UABDL2. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Add support for the multiply-accumulate instructions from the SIMD three-different instructions group (C3.6.15): * skeleton decode of unallocated encodings and split of the group into its three sub-parts * framework for handling the 64x64->128 widening subpart * implementation of the multiply-accumulate instructions SMLAL, SMLAL2, UMLAL, UMLAL2, SMLSL, SMLSL2, UMLSL, UMLSL2, UMULL, UMULL2, SMULL, SMULL2 Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Will Newton 提交于
Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP and VCVTM instructions. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP and VCVTM instructions. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP VRINTM and VRINTZ instructions. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
This helper sets the rounding mode in the standard_fp_status word to allow NEON instructions to modify the rounding mode whilst using the standard FPSCR values for everything else. Signed-off-by: NWill Newton <will.newton@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
Add support for the AArch32 Advanced SIMD VRINTX instruction. Signed-off-by: NWill Newton <will.newton@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
Add support for the AArch32 floating-point VRINTX instruction. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
Add support for the AArch32 floating-point VRINTZ instruction. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
Add support for the AArch32 floating-point VRINTR instruction. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM instructions. Signed-off-by: NWill Newton <will.newton@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Will Newton 提交于
This function will be needed for AArch32 ARMv8 support, so move it to helper.c where it can be used by both targets. Also moves the code out of line, but as it is quite a large function I don't believe this should be a significant performance impact. Signed-off-by: NWill Newton <will.newton@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Paolo Bonzini 提交于
For blizzard, pl110 and tc6393xb this is harmless, but for pxa2xx Coverity noticed that it is used inside an "if" statement. Fix it because it's the file with the highest number of defects in the whole QEMU tree! Use "do...while (0)", or just remove the semicolon if there's a single statement in the macro. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
This patch uses the fact that the midr variable is now a property This patch sets the midr variable to the boards custom midr Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Message-id: a3754b10d150af72e4688a993e484fa2b9b8fa21.1390176489.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Convert the MIDR register to a property. This allows boards to later set a custom MIDR value. This has been done in such a way to maintain compatibility with all existing CPUs and boards Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 878613f2f12d4162f12629522fd99de8df904856.1390176489.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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