- 06 9月, 2017 1 次提交
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由 Richard Henderson 提交于
Fold DISAS_EXC and DISAS_TB_JUMP into DISAS_NORETURN. In both cases all following code is dead. In the first case because we have exited the TB via exception; in the second case because we have exited the TB via goto_tb and its associated machinery. Reviewed-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 05 9月, 2017 1 次提交
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由 Richard Henderson 提交于
For "ldp x0, x1, [x0]", if the second load is on a second page and the second page is unmapped, the exception would be raised with x0 already modified. This means the instruction couldn't be restarted. Cc: qemu-arm@nongnu.org Cc: qemu-stable@nongnu.org Reported-by: NAndrew <andrew@fubar.geek.nz> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20170825224833.4463-1-richard.henderson@linaro.org Fixes: https://bugs.launchpad.net/qemu/+bug/1713066Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> [PMM: tweaked comment format] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 16 8月, 2017 2 次提交
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由 Alistair Francis 提交于
According to the ARM ARM exclusive loads require the same alignment as exclusive stores. Let's update the memops used for the load to match that of the store. This adds the alignment requirement to the memops. Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20170815145714.17635-4-richard.henderson@linaro.org [rth: Require 16-byte alignment for 64-bit LDXP.] Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
We are not providing the required single-copy atomic semantics for the 64-bit operation that is the 32-bit paired load. At the same time, leave the entire 64-bit value in cpu_exclusive_val and stop writing to cpu_exclusive_high. This means that we do not have to re-assemble the 64-bit quantity when it comes time to store. At the same time, drop a redundant temporary and perform all loads directly into the cpu_exclusive_* globals. Tested-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20170815145714.17635-3-richard.henderson@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 15 8月, 2017 1 次提交
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由 Alistair Francis 提交于
When we perform the atomic_cmpxchg operation we want to perform the operation on a pair of 32-bit registers. Previously we were just passing the register size in which was set to MO_32. This would result in the high register to be ignored. To fix this issue we hardcode the size to be 64-bits long when operating on 32-bit pairs. Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NPortia Stephens <portia.stephens@xilinx.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 20170815145714.17635-2-richard.henderson@linaro.org Message-Id: <bc18dddca56e8c2ea4a3def48d33ceb5d21d1fff.1502488636.git.alistair.francis@xilinx.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 25 7月, 2017 1 次提交
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由 Emilio G. Cota 提交于
Fix a TCG temporary leak in the new aarch64 rev16 handling. Signed-off-by: NEmilio G. Cota <cota@braap.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 20 7月, 2017 2 次提交
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由 Lluís Vilanova 提交于
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NAlex Benneé <alex.benee@linaro.org> Reviewed-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NLluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
It is much shorter to reverse all 4 half-words in parallel than extract, reverse, and deposit each in turn. Suggested-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 17 7月, 2017 3 次提交
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由 Alex Bennée 提交于
Previously DISAS_JUMP did ensure this but with the optimisation of 8a6b28c7 (optimize indirect branches) we might not leave the loop. This means if any pending interrupts are cleared by changing IRQ flags we might never get around to servicing them. You usually notice this by seeing the lookup_tb_ptr() helper gainfully chaining TBs together while cpu->interrupt_request remains high and the exit_request has not been set. This breaks amongst other things the OPTEE test suite which executes an eret from the secure world after a non-secure world IRQ has gone pending which then never gets serviced. Instead of using the previously implied semantics of DISAS_JUMP we use DISAS_EXIT which will always exit the run-loop. CC: Etienne Carriere <etienne.carriere@linaro.org> CC: Joakim Bech <joakim.bech@linaro.org> CC: Jaroslaw Pelczar <j.pelczar@samsung.com> CC: Peter Maydell <peter.maydell@linaro.org> CC: Emilio G. Cota <cota@braap.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-7-alex.bennee@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alex Bennée 提交于
While an ISB will ensure any raised IRQs happen on the next instruction it doesn't cause any to get raised by itself. We can therefore use a simple tb exit for ISB instructions and rely on the exit_request check at the top of each TB to deal with exiting if needed. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-6-alex.bennee@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alex Bennée 提交于
DISAS_UPDATE should be used when the wider CPU state other than just the PC has been updated and we should therefore exit the TCG runtime and return to the main execution loop rather assuming DISAS_JUMP would do that. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-id: 20170713141928.25419-3-alex.bennee@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 20 6月, 2017 1 次提交
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由 Richard Henderson 提交于
Exit to cpu loop so we reevaluate cpu_arm_hw_interrupts. Tested-by: NEmilio G. Cota <cota@braap.org> Tested-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NEmilio G. Cota <cota@braap.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 06 6月, 2017 2 次提交
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由 Emilio G. Cota 提交于
Measurements: [Baseline performance is that before applying this and the previous commit] - NBench, aarch64-softmmu. Host: Intel i7-4790K @ 4.00GHz 1.7x +-+--------------------------------------------------------------------------------------------------------------+-+ | | | cross | 1.6x +cross+jr.................................................####...................................................+-+ | #++# | | # # | 1.5x +-+...................................................*****..#...................................................+-+ | *+++* # | | * * # | 1.4x +-+...................................................*...*..#...................................................+-+ | * * # | | ##### * * # | 1.3x +-+................................****+++#...........*...*..#...................................................+-+ | *++* # * * # | | * * # * * # | 1.2x +-+................................*..*...#...........*...*..#...................................................+-+ | * * # * * # | | #### * * # * * # | 1.1x +-+.......................+++#..#..*..*...#...........*...*..#...................................................+-+ | **** # * * # * * # ****#### | | * * # * * # * * # ****### +++#### ****### * * # | 1x +-++-++++++-++++****###++-*++*++#++*++*+-+#++****+++++*+++*++#++*++*-+#++*****++#++****###-++*++*-+#++*+-*+++#+-++-+ | *****### * * # * * # * * # *++*### * * # * * # * * # * *++# * * # * * # | | * *++# * * # * * # * * # * * # * * # * * # * * # * * # * * # * * # | 0.9x +-+---*****###--****###---****###--****####--****###--*****###--****###--*****###--****###---****###--****####---+-+ ASSIGNMENT BITFIELD FOURFP EMULATION HUFFMAN LU DECOMPOSITIONNEURAL NUMERIC SORSTRING SORT hmean png: http://imgur.com/qO9ubtk NB. cross here represents the previous commit. - SPECint06 (test set), aarch64-linux-user. Host: Intel i7-4790K @ 4.00GHz 1.5x +-+--------------------------------------------------------------------------------------------------------------+-+ | ***** | | *+++* jr | | * * | 1.4x +-+.....................................................................*...*.....................+++............+-+ | * * | | | ***** * * | | | * * * * ***** | 1.3x +-+....................................*...*............................*...*....................*.|.*...........+-+ | +++ * * * * * | * | | ***** * * * * *+++* | | * * * * * * * * | 1.2x +-+....................*...*...........*...*............................*...*...........*****....*...*...........+-+ | ***** * * * * * * * * * * +++ | | * * * * * * * * * * * * ***** | | * * * * ***** * * * * * * * * * * | 1.1x +-+...*...*............*...*...*...*...*...*............................*...*....+++....*...*....*...*...*...*...+-+ | * * * * * * * * * * ***** * * * * * * | | * * * * * * * * ***** * * * * * * * * * * | | * * ***** * * * * * * * * ****** * * * * * * * * * * | 1x +-++-+*+++*-++*+++*++++*+-+*+++*-++*+++*-++*+++*+++*++-*++++*-++*****+++*++-*+++*++-*+++*+-+*++++*+++*++-*+++*+-++-+ | * * * * * * * * * * * * * * *+++* * * * * * * * * * * | | * * * * * * * * * * * * * * * * * * * * * * * * * * | | * * * * * * * * * * * * * * * * * * * * * * * * * * | 0.9x +-+---*****---*****----*****---*****---*****---*****---******---*****---*****---*****---*****----*****---*****---+-+ astar bzip2 gcc gobmk h264ref hmmlibquantum mcf omnetpperlbench sjengxalancbmk hmean png: http://imgur.com/3Dp4vvq - SPECint06 (train set), aarch64-linux-user. Host: Intel i7-4790K @ 4.00GHz 1.7x +-+--------------------------------------------------------------------------------------------------------------+-+ | | | jr | 1.6x +-+...............................................................................................+++............+-+ | ***** | | *+++* | | * * | 1.5x +-+..............................................................................................*...*...........+-+ | +++ * * | | ***** * * | 1.4x +-+.....................................................................*+++*....................*...*...........+-+ | * * * * | | ***** * * * * | | * * * * ***** * * | 1.3x +-+....................................*...*............................*...*...*...*............*...*...........+-+ | +++ * * * * * * * * | | ***** * * * * * * ***** * * | 1.2x +-+....................*...*...........*...*............................*...*...*...*...*+++*....*...*...*****...+-+ | * * * * * * * * * * * * *+++* | | ***** * * ***** * * * * * * * * * * * * | | * * * * *+++* * * * * * * * * * * * * | 1.1x +-+...*...*............*...*...*...*...*...*............................*...*...*...*...*...*....*...*...*...*...+-+ | * * ***** * * * * * * ***** * * * * * * * * * * | | * * * * * * * * * * +++ ****** *+++* * * * * * * * * * * | 1x +-+---*****---*****----*****---*****---*****---*****---******---*****---*****---*****---*****----*****---*****---+-+ astar bzip2 gcc gobmk h264ref hmmlibquantum mcf omnetpperlbench sjengxalancbmk hmean png: http://imgur.com/vRrdc9jSigned-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Emilio G. Cota 提交于
Perf numbers in next commit's log. Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 02 6月, 2017 1 次提交
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由 Peter Maydell 提交于
The M profile CPU's MPU has an awkward corner case which we would like to implement with a different MMU index. We can avoid having to bump the number of MMU modes ARM uses, because some of our existing MMU indexes are only used by non-M-profile CPUs, so we can borrow one. To avoid that getting too confusing, clean up the code to try to keep the two meanings of the index separate. Instead of ARMMMUIdx enum values being identical to core QEMU MMU index values, they are now the core index values with some high bits set. Any particular CPU always uses the same high bits (so eventually A profile cores and M profile cores will use different bits). New functions arm_to_core_mmu_idx() and core_to_arm_mmu_idx() convert between the two. In general core index values are stored in 'int' types, and ARM values are stored in ARMMMUIdx types. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1493122030-32191-3-git-send-email-peter.maydell@linaro.org
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- 28 2月, 2017 1 次提交
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由 Nick Reilly 提交于
The aarch64 crypto instructions for AES and SHA are missing the check for if the FPU is enabled. Signed-off-by: NNick Reilly <nreilly@blackberry.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 24 2月, 2017 1 次提交
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由 Alex Bennée 提交于
The WFE and YIELD instructions are really only hints and in TCG's case they were useful to move the scheduling on from one vCPU to the next. In the parallel context (MTTCG) this just causes an unnecessary cpu_exit and contention of the BQL. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
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- 08 2月, 2017 1 次提交
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由 Peter Maydell 提交于
Add support for generating the ISS (Instruction Specific Syndrome) for Data Abort exceptions taken from AArch32. These syndromes are used by hypervisors for example to trap and emulate memory accesses. This is the equivalent for AArch32 guests of the work done for AArch64 guests in commit aaa1f954. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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- 14 1月, 2017 1 次提交
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由 Richard Henderson 提交于
The patch in 59a71b4c suffered from a merge failure when compared to the original patch in http://lists.nongnu.org/archive/html/qemu-devel/2016-12/msg00137.htmlSigned-off-by: NRichard Henderson <rth@twiddle.net>
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- 11 1月, 2017 3 次提交
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由 Richard Henderson 提交于
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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由 Richard Henderson 提交于
Use the new primitives for UBFX and SBFX. Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 27 12月, 2016 2 次提交
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由 Richard Henderson 提交于
We add s->be_data within do_vec_ld/st. Adding it here means that we have the wrong bits set in SIZE for a big-endian host, leading to g_assert_not_reached in write_vec_element and read_vec_element. Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-3-git-send-email-rth@twiddle.net Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Richard Henderson 提交于
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used for a big-endian host doesn't do what's intended. Fix this by adding in the vfp.regs offset after computing the inter-register offset. Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-2-git-send-email-rth@twiddle.net Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 21 12月, 2016 1 次提交
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由 Thomas Huth 提交于
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: NThomas Huth <thuth@redhat.com>
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- 06 12月, 2016 1 次提交
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由 Alex Bennée 提交于
While testing rth's latest TCG patches with risu I found ldaxp was broken. Investigating further I found it was broken by 1dd089d0 when the cmpxchg atomic work was merged. As part of that change the code attempted to be clever by doing a single 64 bit load and then shuffle the data around to set the two 32 bit registers. As I couldn't quite follow the endian magic I've simply partially reverted the change to the original code gen_load_exclusive code. This doesn't affect the cmpxchg functionality as that is all done on in gen_store_exclusive part which is untouched. I've also restored the comment that was removed (with a slight tweak to mention cmpxchg). Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Acked-by: NRichard Henderson <rth@twiddle.net> Message-id: 20161202173454.19179-1-alex.bennee@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 02 11月, 2016 1 次提交
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由 Richard Henderson 提交于
Reuse the existing locking provided by stdio to keep in_asm, cpu, op, op_opt, op_ind, and out_asm as contiguous blocks. While it isn't possible to interleave e.g. in_asm or op_opt logs because of the TB lock protecting all code generation, it is possible to interleave cpu logs, or to interleave a cpu dump with an out_asm dump. For mingw32, we appear to have no viable solution for this. The locking functions are not properly exported from the system runtime library. Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 26 10月, 2016 1 次提交
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由 Emilio G. Cota 提交于
Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. Portable parallel code, however, is written assuming only cmpxchg--and not LL/SC--is available. This means that in practice emulating LL/SC with cmpxchg is a viable alternative. The appended emulates LL/SC pairs in aarch64 with cmpxchg helpers. This works in both user and system mode. In usermode, it avoids pausing all other CPUs to perform the LL/SC pair. The subsequent performance and scalability improvement is significant, as the plots below show. They plot the throughput of atomic_add-bench compiled for ARM and executed on a 64-core x86 machine. Hi-res plots: http://imgur.com/a/JVc8Y atomic_add-bench: 1000000 ops/thread, [0,1] range 18 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 16 ++master +-H--+ ++ || | 14 ++ ++ | | | 12 ++| ++ | | | 10 ++++ ++ 8 ++E ++ |+++ | 6 ++ | ++ | | | 4 ++ | ++ | | | 2 +H++E+--- ++ + | +E++----+E+---+--+E+----++E+------+E+------+E++----+E+---+--+E| 0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,2] range 18 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 16 ++master +-H--+ ++ | | | 14 ++E ++ | | | 12 ++| ++ |+++ | 10 ++ | ++ 8 ++ | ++ | | | 6 ++ | ++ | | | 4 ++ | ++ | +E+--- | 2 +H+ +E+-----+++ +++ +++ ---+E+-----+E+------+++ +++ + +E+---+--+E+----++E+------+E+--- ++++ +++ + +E| 0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,128] range 70 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 60 ++master +-H--+ +++ ---+E+-----+E+------+E+ | +E+------E-------+E+--- | | --- +++ | 50 ++ +++--- ++ | -+E+ | 40 ++ +++---- ++ | E- | | --| | 30 ++ -- +++ ++ | +E+ | 20 ++E+ ++ |E+ | | | 10 ++ ++ + + + + + + + | 0 +HH-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,1024] range 160 ++---------+---------+----------+---------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 140 ++master +-H--+ +++ +++ | -+E+-----+E+-------E| 120 ++ +++ ---- +++ | +++ ----E-- | 100 ++ --E--- +++ ++ | +++ ---- +++ | 80 ++ --E-- ++ | ---- +++ | | -+E+ | 60 ++ ---- +++ ++ | +E+- | 40 ++ -- ++ | +E+ | 20 +EE+ ++ +++ + + + + + + | 0 +HH-H---H--+-----H---+----------+---------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads [rth: Rearrange 128-bit cmpxchg helper. Enforce alignment on LL.] Signed-off-by: NEmilio G. Cota <cota@braap.org> Message-Id: <1467054136-10430-28-git-send-email-cota@braap.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 18 10月, 2016 3 次提交
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由 Thomas Hanson 提交于
3 cases in a switch in disas_exc() require reference to the ARM ARM spec in order to determine what case they're handling. Signed-off-by: NThomas Hanson <thomas.hanson@linaro.org> Message-id: 1476301853-15774-5-git-send-email-thomas.hanson@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Thomas Hanson 提交于
For BR, BLR and RET instructions, if tagged addresses are enabled, the tag field in the address must be cleared out prior to loading the address into the PC. Depending on the current EL, it will be set to either all 0's or all 1's. Signed-off-by: NThomas Hanson <thomas.hanson@linaro.org> Message-id: 1476301853-15774-3-git-send-email-thomas.hanson@linaro.org [PMM: remove unnecessary gen_a64_set_pc_reg() wrapper, rename gen_a64_set_pc_var() to gen_a64_set_pc(), fix stray misindentation] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Thomas Hanson 提交于
When capturing the current CPU state for the TB, extract the TBI0 and TBI1 values from the correct TCR for the current EL and then add them to the TB flags field. Then, at the start of code generation for the block, copy the TBI fields into the DisasContext structure. Signed-off-by: NThomas Hanson <thomas.hanson@linaro.org> Message-id: 1476301853-15774-2-git-send-email-thomas.hanson@linaro.org [PMM: drop useless 'extern' keyword on function prototypes; provide CONFIG_USER_ONLY trivial versions of arm_regime_tbi[01]()] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 04 10月, 2016 1 次提交
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由 Edgar E. Iglesias 提交于
Fix the decoding of iss_sf in disas_ld_lit. The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome) is a bit that specifies the width of the register that the instruction loads to. If cleared it specifies 32 bits. If set it specifies 64 bits. Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1475230780-8669-1-git-send-email-edgar.iglesias@gmail.com [PMM: tweaked phrasing per on-list discussion] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 16 9月, 2016 1 次提交
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由 Pranith Kumar 提交于
Signed-off-by: NPranith Kumar <bobby.prani@gmail.com> Message-Id: <20160714202026.9727-14-bobby.prani@gmail.com> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 06 6月, 2016 1 次提交
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由 Edgar E. Iglesias 提交于
Add support for generating the ISS (Instruction Specific Syndrome) for Data Abort exceptions taken from AArch64. These syndromes are used by hypervisors for example to trap and emulate memory accesses. We save the decoded data out-of-band with the TBs at translation time. When exceptions hit, the extra data attached to the TB is used to recreate the state needed to encode instruction syndromes. This avoids the need to emit moves with every load/store. Based on a suggestion from Peter Maydell. Suggested-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1462464601-10888-2-git-send-email-edgar.iglesias@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 19 5月, 2016 1 次提交
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由 Paolo Bonzini 提交于
exec-all.h contains TCG-specific definitions. It is not needed outside TCG-specific files such as translate.c, exec.c or *helper.c. One generic function had snuck into include/exec/exec-all.h; move it to include/qom/cpu.h. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 13 5月, 2016 1 次提交
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由 Sergey Fedorov 提交于
In user mode, there's only a static address translation, TBs are always invalidated properly and direct jumps are reset when mapping change. Thus the destination address is always valid for direct jumps and there's no need to restrict it to the pages the TB resides in. Signed-off-by: NSergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: NSergey Fedorov <sergey.fedorov@linaro.org> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net>
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- 12 5月, 2016 2 次提交
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由 Edgar E. Iglesias 提交于
The various load/store variants under disas_ldst_reg can all reuse the same decoding for opc, size, rt and is_vector. This patch unifies the decoding in preparation for generating instruction syndromes for data aborts. This will allow us to reduce the number of places to hook in updates to the load/store state needed to generate the insn syndromes. No functional change. Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1461931684-1867-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Edgar E. Iglesias 提交于
Use extract32 instead of open coding the bit masking when decoding is_signed and is_extended. This streamlines the decoding with some of the other ldst variants. No functional change. Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1461931684-1867-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 23 3月, 2016 1 次提交
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由 Alex Bennée 提交于
Each individual architecture needs to use the qemu_log_in_addr_range() feature for enabling in_asm output as it is part of the frontend. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Reviewed-by: NRichard Henderson <rth@twiddle.net> Message-Id: <1458052224-9316-9-git-send-email-alex.bennee@linaro.org> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 04 3月, 2016 1 次提交
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由 Peter Crosthwaite 提交于
Introduce a tbflags for endianness, set based upon the CPUs current endianness. This in turn propagates through to the disas endianness flag. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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