- 18 12月, 2013 40 次提交
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-6-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-5-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1387159292-10436-4-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-3-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Add support for defining a vmstate field which is an array of pointers to structures, and use this to define a VMSTATE_PTIMER_ARRAY() which allows an array of ptimer_state* to be used by devices. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1387159292-10436-2-git-send-email-lig.fnst@cn.fujitsu.com
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由 Antony Pavlov 提交于
Signed-off-by: NAntony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-7-git-send-email-antonynpavlov@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Antony Pavlov 提交于
Signed-off-by: NAntony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-6-git-send-email-antonynpavlov@gmail.com [PMM: don't try to load ROM blob if qtest_enabled()] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Antony Pavlov 提交于
Signed-off-by: NAntony Pavlov <antonynpavlov@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-5-git-send-email-antonynpavlov@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Antony Pavlov 提交于
Signed-off-by: NAntony Pavlov <antonynpavlov@gmail.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-4-git-send-email-antonynpavlov@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Antony Pavlov 提交于
Also this patch adds initial support for Canon PowerShot A1100 IS compact camera. Signed-off-by: NAntony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-3-git-send-email-antonynpavlov@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Antony Pavlov 提交于
DIGIC is Canon Inc.'s name for a family of SoC for digital cameras and camcorders. There is no publicly available specification for DIGIC chips. All information about DIGIC chip internals is based on reverse engineering efforts made by CHDK (http://chdk.wikia.com) and Magic Lantern (http://www.magiclantern.fm) projects contributors. Signed-off-by: NAntony Pavlov <antonynpavlov@gmail.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-2-git-send-email-antonynpavlov@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
This patch adds support for C3.4.4 Logical (immediate), which include AND, ANDS, ORR, EOR. Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: adapted to new decoder, function renaming, removed a TCG temp variable] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> [PMM: cleaned up some unnecessary code in logic_imm_decode_wmask and added clarifying commentary on what it's actually doing. Dropped an ext32u that's not needed if we've just done an AND.] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Claudio Fontana 提交于
this patch adds support for the CLS instruction. Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Claudio Fontana 提交于
this patch introduces wrappers for the clrsb builtins, which count the leading redundant sign bits. Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Claudio Fontana 提交于
This patch implements the C3.4.2 Bitfield instructions: SBFM, BFM, UBFM. Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Claudio Fontana 提交于
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16. Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
This adds support for the C5.6.147 RBIT instruction. Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use bswap64, make RBIT part standalone from the rest of the patch, splitting REV into a separate patch] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Claudio Fontana 提交于
This patch adds support for decoding 1-src data processing insns, and the first user, C5.6.40 CLZ (count leading zeroes). Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
This adds 2-src variable shift register instructions: C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: adapted to new decoder, use enums for shift types] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
This patch adds support for decoding 2-src data processing insns, and the first users, UDIV and SDIV. Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: adapted to new decoder adding the 2-src decoding level, always zero-extend result in 32bit mode] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
This patch adds emulation support for the EXTR instruction. Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: adapted for new decoder, removed a few temporaries, fixed the 32bit bug, added checks for more unallocated cases] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
Add support for the instructions described in "C3.4.6 PC-rel. addressing" (ADR and ADRP). Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
Add support for the instructions described in "C3.5.10 Logical (shifted register)". We store the flags in the same locations as the 32 bit decoder. This is slightly awkward when calculating 64 bit results, but seems a better tradeoff than having to rework the whole 32 bit decoder and also make 32 bit result calculation in A64 awkward. Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: some refactoring to avoid hidden allocation of temps, rework flags, use enums for shift types, renaming of functions] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> [PMM: Use TCG's andc/orc/eqv ops rather than manually inverting] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Claudio Fontana 提交于
This patch adds support for the instruction group "C3.5.6 Conditional select": CSEL, CSINC, CSINV, CSNEG. Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> [PMM: Improved code generated in the nomatch case as per RTH suggestions] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
This patch adds emulation for the compare and branch insns, CBZ and CBNZ. Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
This patch adds emulation for the test and branch insns, TBZ and TBNZ. Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: adapted for new decoder always compare with 0 remove a TCG temporary ] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
This patch adds emulation for the conditional branch (b.cond) instruction. Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: adapted to new decoder structure, reused arm infrastructure for checking the flags] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
Implement BR, BLR and RET. This is all of the 'unconditional branch (register)' instruction category except for ERET and DPRS (which are system mode only). Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: reimplemented on top of new decoder structure] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
Implement the B and BL instructions (PC relative branches and calls). For convenience in managing TCG temporaries which might be generated if a source register is the zero-register XZR, we provide a simple mechanism for creating a new temp which is automatically freed at the end of decode of the instruction. Signed-off-by: NAlexander Graf <agraf@suse.de> [claudio: renamed functions, adapted to new decoder layout] Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Claudio Fontana 提交于
Decode the various kinds of system instructions: hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL sync instructions, which include CLREX, DSB, DMB, ISB msr_i, which move immediate to processor state field sys, which include all SYS and SYSL instructions msr, which move from a gp register to a system register mrs, which move from a system register to a gp register Provide implementations where they are trivial nops. Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Claudio Fontana 提交于
Provide a skeleton for a64 instruction decoding in translate-a64.c, by dividing instructions into the classes defined by the ARM Architecture Reference Manual(DDI0487A_a) section C3. Signed-off-by: NClaudio Fontana <claudio.fontana@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
We will need helpers that only make sense with AArch64. Add helper-a64.{c,h} files as stubs that we can fill with these helpers in the following patches. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Register the aarch64-fpu XML and implement the necessary read/write handlers so we can support reading and writing of FP registers in the gdb stub. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
The information which AArch32 holds in the FPSCR is split for AArch64 into two logically distinct registers, FPSR and FPCR. Since they are carefully arranged to use non-overlapping bits, we leave the underlying state in the same place, and provide accessor functions which just update the appropriate bits via vfp_get_fpscr() and vfp_set_fpscr(). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Alexander Graf 提交于
When executing translation blocks we need to be able to recover our program counter. Add a method to set it for AArch64 CPUs. This covers user-mode, but for system mode emulation we will need to check if the CPU is in an AArch32 execution state. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
The A32/T32 gen_intermediate_code_internal() is complicated because it has to deal with: * conditionally executed instructions * Thumb IT blocks * kernel helper page * M profile exception-exit special casing None of these apply to A64, so putting the "this is A64 so call the A64 decoder" check in the middle of the A32/T32 loop is confusing and means the A64 decoder's handling of things like conditional jump and singlestepping has to take account of the conditional-execution jumps the main loop might emit. Refactor the code to give A64 its own gen_intermediate_code_internal function instead. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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由 Peter Maydell 提交于
Add a config for aarch64-softmmu; this enables building of this target. The resulting executable doesn't know about any 64 bit CPUs, but all the 32 bit CPUs and board models work. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-8-git-send-email-peter.maydell@linaro.org Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Mian M. Hamayun 提交于
This commit adds support for booting a single AArch64 CPU by setting appropriate registers. The bootloader includes placeholders for Board-ID that are used to implement uniform indexing across different bootloaders. Signed-off-by: NMian M. Hamayun <m.hamayun@virtualopensystems.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-7-git-send-email-peter.maydell@linaro.org [PMM: * updated to use ARMInsnFixup style bootloader fragments * dropped virt.c additions * use runtime checks for "is this an AArch64 core" rather than ifdefs * drop some unnecessary setting of registers in reset hook ] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
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由 Peter Maydell 提交于
For AArch64 we will obviously require a different set of primary and secondary boot loader code fragments. However currently we hardcode the offsets into the loader code where we must write the entrypoint and other data into arm_load_kernel(). This makes it hard to substitute a different loader fragment, so switch to a more flexible scheme where instead of a raw array of instructions we use an array of (instruction, fixup-type) pairs that indicate which words need special action or data written into them. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-6-git-send-email-peter.maydell@linaro.org Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Enable KVM if the host and target CPU are both aarch64. Note that host aarch64 + target arm is not valid for KVM acceleration: the 64 bit kernel does not support the ioctl interface for 32 bit CPUs. 32 bit VMs on 64 bit hosts need to be created using the 64 bit ioctl interface; when QEMU supports this it will be on the arch64-softmmu target with a -cpu parameter for a 32 bit CPU, which is still an aarch64/aarch64 combination as far as configure is concerned. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-5-git-send-email-peter.maydell@linaro.org Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
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