- 02 3月, 2017 3 次提交
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由 Ben Warren 提交于
This implements the VM Generation ID feature by passing a 128-bit GUID to the guest via a fw_cfg blob. Any time the GUID changes, an ACPI notify event is sent to the guest The user interface is a simple device with one parameter: - guid (string, must be "auto" or in UUID format xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx) Signed-off-by: NBen Warren <ben@skyportsystems.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Tested-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Ben Warren 提交于
This allows them to be centrally initialized and destroyed The "AcpiBuildTables.vmgenid" array will be used to construct the "etc/vmgenid_guid" fw_cfg blob. Its contents will be linked into fw_cfg after being built on the pc_machine_done() -> acpi_setup() -> acpi_build() call path, and dropped without use on the subsequent, guest triggered, acpi_build_update() -> acpi_build() call path. Signed-off-by: NBen Warren <ben@skyportsystems.com> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Tested-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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由 Ben Warren 提交于
This is similar to the existing 'add pointer' functionality, but instead of instructing the guest (BIOS or UEFI) to patch memory, it instructs the guest to write the pointer back to QEMU via a writeable fw_cfg file. Signed-off-by: NBen Warren <ben@skyportsystems.com> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Tested-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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- 01 3月, 2017 36 次提交
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由 Cédric Le Goater 提交于
It provides a better monitor output of the ICP and ICS objects, else the objects are printed out of order. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
The ICS object uses a post_load() handler which is implicitly relying on the fact that the internal state of the ICS and ICP objects has been restored but this is not guaranteed. So, let's move the code under the post_load() handler of the machine where we know the objects have been fully restored. The icp_resend() handler of the XICSFabric QOM interface is also removed as it is now obsolete. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
The XICSState classes are not used anymore. They have now been fully deprecated by the XICSFabric QOM interface. Do the cleanups. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
There is nothing left related to the XICS object in the realize functions of the KVMXICSState and XICSState class. So adapt the interfaces to call these routines directly from the sPAPR machine init sequence. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
This is the last step to remove the XICSState abstraction and have the machine hold all the objects related to interrupts : ICSs and ICPs. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
spapr_dt_xics() only needs the number of servers to build the device tree nodes. Let's change the routine interface to reflect that. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
Also introduce a xics_icp_get() helper to simplify the changes. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
The cpu_setup() handler is currently under the XICSState class but it really belongs under ICPState as it is setting up an individual vCPU. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
The cpu_setup() handler currently takes a 'XICSState *' argument to grab the kernel ICP file descriptor. This interface can be simplified by using the 'xics' backlink of the ICP object. This change is also required by subsequent patches which makes use of the QOM interface for XICS. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
Let's add two new handlers for ICPs. One is to get an ICP object from a server number and a second is to resend the irqs when needed. The icp_resend() handler is a temporary workaround needed by the ics-simple post_load() handler. It will be removed when the post_load portion can be done at the machine level. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
This is not used anymore. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
It is not used anymore now that we have the QOM interface for XICS. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
Also change the ICPState 'xics' backlink to be a XICSFabric, this removes the need of using qdev_get_machine() to get the QOM interface in some of the routines. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
Add 'ics_get' and 'ics_resend' handlers to the sPAPR machine. These are relatively simple for a single ICS. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
This interface provides two simple handlers. One is to get an ICS (Interrupt Source Controller) object from an irq number and a second to resend the irqs when needed. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
A list of ICS objects was introduced under the XICS object for the PowerNV machine but, for the sPAPR machine, it brings extra complexity as there is only a single ICS. To simplify the code, let's add the ICS pointer under the sPAPR machine and try to reduce the use of this list where possible. Also, change the xics_spapr_*() routines to use an ICS object instead of an XICSState and change their name to reflect that these are specific to the sPAPR ICS object. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
Today, the ICP (Interrupt Controller Presenter) objects are created by the 'nr_servers' property handler of the XICS object and a class handler. They are realized in the XICS object realize routine. Let's simplify the process by creating the ICP objects along with the XICS object at the machine level. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Cédric Le Goater 提交于
Today, the ICS (Interrupt Controller Source) object is created and realized by the init and realize routines of the XICS object, but some of the parameters are only known at the machine level. These parameters are passed from the sPAPR machine to the ICS object in a rather convoluted way using property handlers and a class handler of the XICS object. The number of irqs required to allocate the IRQ state objects in the ICS realize routine is one of them. Let's simplify the process by creating the ICS object along with the XICS object at the machine level and link the ICS into the XICS list of ICSs at this level also. In the sPAPR machine, there is only a single ICS but that will change with the PowerNV machine. Also, QOMify the creation of the objects and get rid of the superfluous code. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 David Gibson 提交于
Currently xics - the component of the IBM POWER interrupt controller representing the overall interrupt fabric / architecture is represented as a descendent of SysBusDevice. However, this is not really correct - the xics presents nothing in MMIO space so it should be an "unattached" device in the current QOM model. Since this device will always be created by the machine type, not created specifically from the command line, and because it has no migrated state it should be safe to move it around the device composition tree. Therefore this patch changes it to a descendent of TYPE_DEVICE, and makes it an unattached device. So that its reset handler still gets called correctly, we add a qdev_set_parent_bus() to attach it to sysbus. It's not really clear that's correct (instead of using register_reset()) but it appears to a common technique. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> [clg corrected problems with reset] Signed-off-by: NCédric Le Goater <clg@kaod.org> [dwg folded together and updated commit message] Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Greg Kurz 提交于
Since commit 1d2d9742 "spapr_pci: enumerate and add PCI device tree", QEMU populates the PCI device tree in the opposite order compared to SLOF. Before 1d2d9742: Populating /pci@800000020000000 00 0000 (D) : 1af4 1000 virtio [ net ] 00 0800 (D) : 1af4 1001 virtio [ block ] 00 1000 (D) : 1af4 1009 virtio [ network ] Populating /pci@800000020000000/unknown-legacy-device@2 7e5294b8 : /pci@800000020000000 7e52b998 : |-- ethernet@0 7e52c0c8 : |-- scsi@1 7e52c7e8 : +-- unknown-legacy-device@2 ok Since 1d2d9742: Populating /pci@800000020000000 00 1000 (D) : 1af4 1009 virtio [ network ] Populating /pci@800000020000000/unknown-legacy-device@2 00 0800 (D) : 1af4 1001 virtio [ block ] 00 0000 (D) : 1af4 1000 virtio [ net ] 7e5e8118 : /pci@800000020000000 7e5ea6a0 : |-- unknown-legacy-device@2 7e5eadb8 : |-- scsi@1 7e5eb4d8 : +-- ethernet@0 ok This behaviour change is not actually a bug since no assumptions should be made on DT ordering. But it has no real justification either, other than being the consequence of the way fdt_add_subnode() inserts new elements to the front of the FDT rather than adding them to the tail. This patch reverts to the historical SLOF ordering by walking PCI devices in reverse order. This reconciles pseries with x86 machine types behavior. It is expected to make things easier when porting existing applications to power. Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com> Tested-by: NThomas Huth <thuth@redhat.com> Reviewed-by: NNikunj A Dadhania <nikunj@linux.vnet.ibm.com> (slight update to the changelog) Signed-off-by: NGreg Kurz <groug@kaod.org> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Laurent Vivier 提交于
To allow QEMU to add PCI entries in device tree, we must have a more exhaustive list of PCI class IDs. This patch synchronizes as much as possible with pci_ids.h and add some missing IDs from SLOF. Signed-off-by: NLaurent Vivier <lvivier@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
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由 Marc-André Lureau 提交于
Spotted by ASAN. Signed-off-by: NMarc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Kevin Wolf 提交于
By default, don't allow another writer for block devices that are attached to a guest device. For the cases where this setup is intended (e.g. using a cluster filesystem on the disk), the new option can be used to allow it. This change affects only devices using DEFINE_BLOCK_PROPERTIES(). Devices directly using DEFINE_PROP_DRIVE() still accept writers unconditionally. Signed-off-by: NKevin Wolf <kwolf@redhat.com> Reviewed-by: NMax Reitz <mreitz@redhat.com> Acked-by: NFam Zheng <famz@redhat.com>
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由 Kevin Wolf 提交于
This makes all device emulations with a qdev drive property request permissions on their BlockBackend. The only thing we block at this point is resizing images for some devices that can't support it. Signed-off-by: NKevin Wolf <kwolf@redhat.com> Acked-by: NFam Zheng <famz@redhat.com> Reviewed-by: NMax Reitz <mreitz@redhat.com>
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由 Clement Deschamps 提交于
This adds the bcm2835_sdhost and bcm2835_gpio to the BCM2835 platform. For supporting the SD controller selection (alternate function of GPIOs 48-53), the bcm2835_gpio now exposes an sdbus. It also has a link to both the sdbus of sdhci and sdhost controllers, and the card is reparented from one bus to another when the alternate function of GPIOs 48-53 is modified. Signed-off-by: NClement Deschamps <clement.deschamps@antfield.fr> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1488293711-14195-5-git-send-email-peter.maydell@linaro.org Message-id: 20170224164021.9066-5-clement.deschamps@antfield.fr Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Clement Deschamps 提交于
This adds the BCM2835 GPIO controller. It currently implements: - The 54 GPIOs as outputs (qemu_irq) - The SD controller selection via alternate function of GPIOs 48-53 Signed-off-by: NClement Deschamps <clement.deschamps@antfield.fr> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1488293711-14195-4-git-send-email-peter.maydell@linaro.org Message-id: 20170224164021.9066-4-clement.deschamps@antfield.fr Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Clement Deschamps 提交于
Provide a new function sdbus_reparent_card() in sd core for reparenting a card from a SDBus to another one. This function is required by the raspi platform, where the two SD controllers can be dynamically switched. Signed-off-by: NClement Deschamps <clement.deschamps@antfield.fr> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1488293711-14195-3-git-send-email-peter.maydell@linaro.org Message-id: 20170224164021.9066-3-clement.deschamps@antfield.fr Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> [PMM: added a doc comment to the header file; changed to use new behaviour of qdev_set_parent_bus()] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Vijaya Kumar K 提交于
To Save and Restore ICC_SRE_EL1 register introduce vmstate subsection and load only if non-zero. Also initialize icc_sre_el1 with to 0x7 in pre_load function. Signed-off-by: NVijaya Kumar K <Vijaya.Kumar@cavium.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEric Auger <eric.auger@redhat.com> Message-id: 1487850673-26455-3-git-send-email-vijay.kilari@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Switch the stm32f205 SoC to create the armv7m object directly rather than via the armv7m_init() wrapper. This fits better with the SoC model's very QOMified design. In particular this means we can push loading the guest image out to the top level board code where it belongs, rather than the SoC object having a QOM property for the filename to load. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-11-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The SysTick timer isn't really part of the NVIC proper; we just modelled it that way back when we couldn't easily have devices that only occupied a small chunk of a memory region. Split it out into its own device. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1487604965-23220-10-git-send-email-peter.maydell@linaro.org Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
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由 Peter Maydell 提交于
Instead of the bitband device doing a cpu_physical_memory_read/write, make it take a MemoryRegion which specifies where it should be accessing, and use address_space_read/write to access the corresponding AddressSpace. Since this entails pretty much a rewrite, convert away from old_mmio in the process. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-8-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Make the ARMv7M object take a memory region link which it uses to wire up the bitband rather than having them always put themselves in the system address space. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-6-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Create a proper QOM object for the armv7m container, which holds the CPU, the NVIC and the bitband regions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Move the NVICState struct definition into a header, so we can embed it into other QOM objects like SoCs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Abstract the "load kernel" code out of armv7m_init() into its own function. This includes the registration of the CPU reset function, to parallel how we handle this for A profile cores. We make the function public so that boards which choose to directly instantiate an ARMv7M device object can call it. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-2-git-send-email-peter.maydell@linaro.org
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- 28 2月, 2017 1 次提交
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由 Clement Deschamps 提交于
This adds the BCM2835 SDHost controller from Arasan. Signed-off-by: NClement Deschamps <clement.deschamps@antfield.fr> Message-id: 20170224164021.9066-2-clement.deschamps@antfield.fr Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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